cpu_subr.c revision 1.31
1 /* $NetBSD: cpu_subr.c,v 1.31 2007/06/25 11:16:48 aymeric Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.31 2007/06/25 11:16:48 aymeric Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <powerpc/oea/hid.h> 52 #include <powerpc/oea/hid_601.h> 53 #include <powerpc/spr.h> 54 55 #include <dev/sysmon/sysmonvar.h> 56 57 static void cpu_enable_l2cr(register_t); 58 static void cpu_enable_l3cr(register_t); 59 static void cpu_config_l2cr(int); 60 static void cpu_config_l3cr(int); 61 static void cpu_probe_speed(struct cpu_info *); 62 static void cpu_idlespin(void); 63 #if NSYSMON_ENVSYS > 0 64 static void cpu_tau_setup(struct cpu_info *); 65 static int cpu_tau_gtredata __P((struct sysmon_envsys *, 66 struct envsys_tre_data *)); 67 static int cpu_tau_streinfo __P((struct sysmon_envsys *, 68 struct envsys_basic_info *)); 69 #endif 70 71 int cpu; 72 int ncpus; 73 74 struct fmttab { 75 register_t fmt_mask; 76 register_t fmt_value; 77 const char *fmt_string; 78 }; 79 80 static const struct fmttab cpu_7450_l2cr_formats[] = { 81 { L2CR_L2E, 0, " disabled" }, 82 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 83 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 84 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 85 { L2CR_L2E, ~0, " 256KB L2 cache" }, 86 { 0, 0, NULL } 87 }; 88 89 static const struct fmttab cpu_7448_l2cr_formats[] = { 90 { L2CR_L2E, 0, " disabled" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 94 { L2CR_L2E, ~0, " 1MB L2 cache" }, 95 { 0, 0, NULL } 96 }; 97 98 static const struct fmttab cpu_7457_l2cr_formats[] = { 99 { L2CR_L2E, 0, " disabled" }, 100 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 101 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 102 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 103 { L2CR_L2E, ~0, " 512KB L2 cache" }, 104 { 0, 0, NULL } 105 }; 106 107 static const struct fmttab cpu_7450_l3cr_formats[] = { 108 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 109 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 110 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 111 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 112 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 113 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 114 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 115 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 116 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 117 { L3CR_L3SIZ, ~0, " L3 cache" }, 118 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 119 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 120 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 121 { L3CR_L3CLK, ~0, " at" }, 122 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 123 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 124 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 125 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 126 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 127 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 128 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 129 { L3CR_L3CLK, ~0, " ratio" }, 130 { 0, 0, NULL }, 131 }; 132 133 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 134 { L2CR_L2E, 0, " disabled" }, 135 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 136 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 137 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 138 { 0, ~0, " 512KB" }, 139 { L2CR_L2WT, L2CR_L2WT, " WT" }, 140 { L2CR_L2WT, 0, " WB" }, 141 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 142 { 0, ~0, " L2 cache" }, 143 { 0, 0, NULL } 144 }; 145 146 static const struct fmttab cpu_l2cr_formats[] = { 147 { L2CR_L2E, 0, " disabled" }, 148 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 149 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 150 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 151 { L2CR_L2PE, L2CR_L2PE, " parity" }, 152 { L2CR_L2PE, 0, " no-parity" }, 153 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 154 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 155 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 156 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 157 { L2CR_L2WT, L2CR_L2WT, " WT" }, 158 { L2CR_L2WT, 0, " WB" }, 159 { L2CR_L2E, ~0, " L2 cache" }, 160 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 161 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 162 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 163 { L2CR_L2CLK, ~0, " at" }, 164 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 165 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 166 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 167 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 168 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 169 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 170 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 171 { L2CR_L2CLK, ~0, " ratio" }, 172 { 0, 0, NULL } 173 }; 174 175 static void cpu_fmttab_print(const struct fmttab *, register_t); 176 177 struct cputab { 178 const char name[8]; 179 uint16_t version; 180 uint16_t revfmt; 181 }; 182 #define REVFMT_MAJMIN 1 /* %u.%u */ 183 #define REVFMT_HEX 2 /* 0x%04x */ 184 #define REVFMT_DEC 3 /* %u */ 185 static const struct cputab models[] = { 186 { "601", MPC601, REVFMT_DEC }, 187 { "602", MPC602, REVFMT_DEC }, 188 { "603", MPC603, REVFMT_MAJMIN }, 189 { "603e", MPC603e, REVFMT_MAJMIN }, 190 { "603ev", MPC603ev, REVFMT_MAJMIN }, 191 { "G2", MPCG2, REVFMT_MAJMIN }, 192 { "604", MPC604, REVFMT_MAJMIN }, 193 { "604e", MPC604e, REVFMT_MAJMIN }, 194 { "604ev", MPC604ev, REVFMT_MAJMIN }, 195 { "620", MPC620, REVFMT_HEX }, 196 { "750", MPC750, REVFMT_MAJMIN }, 197 { "750FX", IBM750FX, REVFMT_MAJMIN }, 198 { "7400", MPC7400, REVFMT_MAJMIN }, 199 { "7410", MPC7410, REVFMT_MAJMIN }, 200 { "7450", MPC7450, REVFMT_MAJMIN }, 201 { "7455", MPC7455, REVFMT_MAJMIN }, 202 { "7457", MPC7457, REVFMT_MAJMIN }, 203 { "7447A", MPC7447A, REVFMT_MAJMIN }, 204 { "7448", MPC7448, REVFMT_MAJMIN }, 205 { "8240", MPC8240, REVFMT_MAJMIN }, 206 { "8245", MPC8245, REVFMT_MAJMIN }, 207 { "970", IBM970, REVFMT_MAJMIN }, 208 { "970FX", IBM970FX, REVFMT_MAJMIN }, 209 { "", 0, REVFMT_HEX } 210 }; 211 212 213 #ifdef MULTIPROCESSOR 214 struct cpu_info cpu_info[CPU_MAXNUM]; 215 #else 216 struct cpu_info cpu_info[1]; 217 #endif 218 219 int cpu_altivec; 220 int cpu_psluserset, cpu_pslusermod; 221 char cpu_model[80]; 222 223 void 224 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 225 { 226 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 227 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 228 (data & fmt->fmt_mask) == fmt->fmt_value) 229 aprint_normal("%s", fmt->fmt_string); 230 } 231 } 232 233 void 234 cpu_idlespin(void) 235 { 236 register_t msr; 237 238 if (powersave <= 0) 239 return; 240 241 __asm volatile( 242 "sync;" 243 "mfmsr %0;" 244 "oris %0,%0,%1@h;" /* enter power saving mode */ 245 "mtmsr %0;" 246 "isync;" 247 : "=r"(msr) 248 : "J"(PSL_POW)); 249 } 250 251 void 252 cpu_probe_cache(void) 253 { 254 u_int assoc, pvr, vers; 255 256 pvr = mfpvr(); 257 vers = pvr >> 16; 258 259 260 /* Presently common across almost all implementations. */ 261 curcpu()->ci_ci.dcache_line_size = CACHELINESIZE; 262 curcpu()->ci_ci.icache_line_size = CACHELINESIZE; 263 264 265 switch (vers) { 266 #define K *1024 267 case IBM750FX: 268 case MPC601: 269 case MPC750: 270 case MPC7447A: 271 case MPC7448: 272 case MPC7450: 273 case MPC7455: 274 case MPC7457: 275 curcpu()->ci_ci.dcache_size = 32 K; 276 curcpu()->ci_ci.icache_size = 32 K; 277 assoc = 8; 278 break; 279 case MPC603: 280 curcpu()->ci_ci.dcache_size = 8 K; 281 curcpu()->ci_ci.icache_size = 8 K; 282 assoc = 2; 283 break; 284 case MPC603e: 285 case MPC603ev: 286 case MPC604: 287 case MPC8240: 288 case MPC8245: 289 case MPCG2: 290 curcpu()->ci_ci.dcache_size = 16 K; 291 curcpu()->ci_ci.icache_size = 16 K; 292 assoc = 4; 293 break; 294 case MPC604e: 295 case MPC604ev: 296 curcpu()->ci_ci.dcache_size = 32 K; 297 curcpu()->ci_ci.icache_size = 32 K; 298 assoc = 4; 299 break; 300 case IBM970: 301 case IBM970FX: 302 curcpu()->ci_ci.dcache_size = 32 K; 303 curcpu()->ci_ci.icache_size = 64 K; 304 curcpu()->ci_ci.dcache_line_size = 128; 305 curcpu()->ci_ci.icache_line_size = 128; 306 assoc = 2; 307 break; 308 309 default: 310 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 311 curcpu()->ci_ci.icache_size = PAGE_SIZE; 312 assoc = 1; 313 #undef K 314 } 315 316 /* 317 * Possibly recolor. 318 */ 319 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 320 } 321 322 struct cpu_info * 323 cpu_attach_common(struct device *self, int id) 324 { 325 struct cpu_info *ci; 326 u_int pvr, vers; 327 328 ci = &cpu_info[id]; 329 #ifndef MULTIPROCESSOR 330 /* 331 * If this isn't the primary CPU, print an error message 332 * and just bail out. 333 */ 334 if (id != 0) { 335 aprint_normal(": ID %d\n", id); 336 aprint_normal("%s: processor off-line; multiprocessor support " 337 "not present in kernel\n", self->dv_xname); 338 return (NULL); 339 } 340 #endif 341 342 ci->ci_cpuid = id; 343 ci->ci_intrdepth = -1; 344 ci->ci_dev = self; 345 ci->ci_idlespin = cpu_idlespin; 346 347 pvr = mfpvr(); 348 vers = (pvr >> 16) & 0xffff; 349 350 switch (id) { 351 case 0: 352 /* load my cpu_number to PIR */ 353 switch (vers) { 354 case MPC601: 355 case MPC604: 356 case MPC604e: 357 case MPC604ev: 358 case MPC7400: 359 case MPC7410: 360 case MPC7447A: 361 case MPC7448: 362 case MPC7450: 363 case MPC7455: 364 case MPC7457: 365 mtspr(SPR_PIR, id); 366 } 367 cpu_setup(self, ci); 368 break; 369 default: 370 if (id >= CPU_MAXNUM) { 371 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 372 panic("cpuattach"); 373 } 374 #ifndef MULTIPROCESSOR 375 aprint_normal(" not configured\n"); 376 return NULL; 377 #else 378 mi_cpu_attach(ci); 379 break; 380 #endif 381 } 382 return (ci); 383 } 384 385 void 386 cpu_setup(self, ci) 387 struct device *self; 388 struct cpu_info *ci; 389 { 390 u_int hid0, pvr, vers; 391 const char *bitmask; 392 char hidbuf[128]; 393 char model[80]; 394 395 pvr = mfpvr(); 396 vers = (pvr >> 16) & 0xffff; 397 398 cpu_identify(model, sizeof(model)); 399 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 400 cpu_number() == 0 ? " (primary)" : ""); 401 402 #if defined (PPC_OEA) || defined (PPC_OEA64) 403 hid0 = mfspr(SPR_HID0); 404 #elif defined (PPC_OEA64_BRIDGE) 405 hid0 = mfspr(SPR_HID0); 406 #endif 407 408 cpu_probe_cache(); 409 410 /* 411 * Configure power-saving mode. 412 */ 413 switch (vers) { 414 case MPC604: 415 case MPC604e: 416 case MPC604ev: 417 /* 418 * Do not have HID0 support settings, but can support 419 * MSR[POW] off 420 */ 421 powersave = 1; 422 break; 423 424 case MPC603: 425 case MPC603e: 426 case MPC603ev: 427 case MPC750: 428 case IBM750FX: 429 case MPC7400: 430 case MPC7410: 431 case MPC8240: 432 case MPC8245: 433 case MPCG2: 434 /* Select DOZE mode. */ 435 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 436 hid0 |= HID0_DOZE | HID0_DPM; 437 powersave = 1; 438 break; 439 440 case MPC7447A: 441 case MPC7448: 442 case MPC7457: 443 case MPC7455: 444 case MPC7450: 445 /* Enable the 7450 branch caches */ 446 hid0 |= HID0_SGE | HID0_BTIC; 447 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 448 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 449 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 450 hid0 &= ~HID0_BTIC; 451 /* Select NAP mode. */ 452 hid0 &= ~(HID0_HIGH_BAT_EN | HID0_SLEEP); 453 hid0 |= HID0_NAP | HID0_DPM /* | HID0_XBSEN */; 454 powersave = 1; 455 break; 456 457 case IBM970: 458 case IBM970FX: 459 default: 460 /* No power-saving mode is available. */ ; 461 } 462 463 #ifdef NAPMODE 464 switch (vers) { 465 case IBM750FX: 466 case MPC750: 467 case MPC7400: 468 /* Select NAP mode. */ 469 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 470 hid0 |= HID0_NAP; 471 break; 472 } 473 #endif 474 475 switch (vers) { 476 case IBM750FX: 477 case MPC750: 478 hid0 &= ~HID0_DBP; /* XXX correct? */ 479 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 480 break; 481 482 case MPC7400: 483 case MPC7410: 484 hid0 &= ~HID0_SPD; 485 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 486 hid0 |= HID0_EIEC; 487 break; 488 } 489 490 #if defined (PPC_OEA) 491 mtspr(SPR_HID0, hid0); 492 __asm volatile("sync;isync"); 493 #endif 494 495 switch (vers) { 496 case MPC601: 497 bitmask = HID0_601_BITMASK; 498 break; 499 case MPC7450: 500 case MPC7455: 501 case MPC7457: 502 bitmask = HID0_7450_BITMASK; 503 break; 504 case IBM970: 505 case IBM970FX: 506 bitmask = 0; 507 break; 508 default: 509 bitmask = HID0_BITMASK; 510 break; 511 } 512 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 513 aprint_normal("%s: HID0 %s, powersave: %d\n", self->dv_xname, hidbuf, powersave); 514 515 ci->ci_khz = 0; 516 517 /* 518 * Display speed and cache configuration. 519 */ 520 switch (vers) { 521 case MPC604: 522 case MPC604e: 523 case MPC604ev: 524 case MPC750: 525 case IBM750FX: 526 case MPC7400: 527 case MPC7410: 528 case MPC7447A: 529 case MPC7448: 530 case MPC7450: 531 case MPC7455: 532 case MPC7457: 533 aprint_normal("%s: ", self->dv_xname); 534 cpu_probe_speed(ci); 535 aprint_normal("%u.%02u MHz", 536 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 537 538 if (vers == IBM750FX || vers == MPC750 || 539 vers == MPC7400 || vers == MPC7410 || MPC745X_P(vers)) { 540 if (MPC745X_P(vers)) { 541 cpu_config_l3cr(vers); 542 } else { 543 cpu_config_l2cr(pvr); 544 } 545 } 546 aprint_normal("\n"); 547 break; 548 } 549 550 #if NSYSMON_ENVSYS > 0 551 /* 552 * Attach MPC750 temperature sensor to the envsys subsystem. 553 * XXX the 74xx series also has this sensor, but it is not 554 * XXX supported by Motorola and may return values that are off by 555 * XXX 35-55 degrees C. 556 */ 557 if (vers == MPC750 || vers == IBM750FX) 558 cpu_tau_setup(ci); 559 #endif 560 561 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 562 NULL, self->dv_xname, "clock"); 563 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 564 NULL, self->dv_xname, "soft clock"); 565 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 566 NULL, self->dv_xname, "soft net"); 567 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 568 NULL, self->dv_xname, "soft serial"); 569 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 570 NULL, self->dv_xname, "traps"); 571 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 572 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 573 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 574 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 575 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 576 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 577 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 578 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 579 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 580 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 581 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 582 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 583 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 584 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 585 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 586 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 587 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 588 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 589 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 590 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 591 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 592 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 593 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 594 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 595 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 596 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 597 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 598 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 599 #ifdef ALTIVEC 600 if (cpu_altivec) { 601 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 602 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 603 } 604 #endif 605 } 606 607 void 608 cpu_identify(char *str, size_t len) 609 { 610 u_int pvr, major, minor; 611 uint16_t vers, rev, revfmt; 612 const struct cputab *cp; 613 const char *name; 614 size_t n; 615 616 pvr = mfpvr(); 617 vers = pvr >> 16; 618 rev = pvr; 619 620 switch (vers) { 621 case MPC7410: 622 minor = (pvr >> 0) & 0xff; 623 major = minor <= 4 ? 1 : 2; 624 break; 625 default: 626 major = (pvr >> 4) & 0xf; 627 minor = (pvr >> 0) & 0xf; 628 } 629 630 for (cp = models; cp->name[0] != '\0'; cp++) { 631 if (cp->version == vers) 632 break; 633 } 634 635 if (str == NULL) { 636 str = cpu_model; 637 len = sizeof(cpu_model); 638 cpu = vers; 639 } 640 641 revfmt = cp->revfmt; 642 name = cp->name; 643 if (rev == MPC750 && pvr == 15) { 644 name = "755"; 645 revfmt = REVFMT_HEX; 646 } 647 648 if (cp->name[0] != '\0') { 649 n = snprintf(str, len, "%s (Revision ", cp->name); 650 } else { 651 n = snprintf(str, len, "Version %#x (Revision ", vers); 652 } 653 if (len > n) { 654 switch (revfmt) { 655 case REVFMT_MAJMIN: 656 snprintf(str + n, len - n, "%u.%u)", major, minor); 657 break; 658 case REVFMT_HEX: 659 snprintf(str + n, len - n, "0x%04x)", rev); 660 break; 661 case REVFMT_DEC: 662 snprintf(str + n, len - n, "%u)", rev); 663 break; 664 } 665 } 666 } 667 668 #ifdef L2CR_CONFIG 669 u_int l2cr_config = L2CR_CONFIG; 670 #else 671 u_int l2cr_config = 0; 672 #endif 673 674 #ifdef L3CR_CONFIG 675 u_int l3cr_config = L3CR_CONFIG; 676 #else 677 u_int l3cr_config = 0; 678 #endif 679 680 void 681 cpu_enable_l2cr(register_t l2cr) 682 { 683 register_t msr, x; 684 685 /* Disable interrupts and set the cache config bits. */ 686 msr = mfmsr(); 687 mtmsr(msr & ~PSL_EE); 688 #ifdef ALTIVEC 689 if (cpu_altivec) 690 __asm volatile("dssall"); 691 #endif 692 __asm volatile("sync"); 693 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 694 __asm volatile("sync"); 695 696 /* Wait for L2 clock to be stable (640 L2 clocks). */ 697 delay(100); 698 699 /* Invalidate all L2 contents. */ 700 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 701 do { 702 x = mfspr(SPR_L2CR); 703 } while (x & L2CR_L2IP); 704 705 /* Enable L2 cache. */ 706 l2cr |= L2CR_L2E; 707 mtspr(SPR_L2CR, l2cr); 708 mtmsr(msr); 709 } 710 711 void 712 cpu_enable_l3cr(register_t l3cr) 713 { 714 register_t x; 715 716 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 717 718 /* 719 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 720 * L3CLKEN. (also mask off reserved bits in case they were included 721 * in L3CR_CONFIG) 722 */ 723 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 724 mtspr(SPR_L3CR, l3cr); 725 726 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 727 l3cr |= 0x04000000; 728 mtspr(SPR_L3CR, l3cr); 729 730 /* 3: Set L3CLKEN to 1*/ 731 l3cr |= L3CR_L3CLKEN; 732 mtspr(SPR_L3CR, l3cr); 733 734 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 735 __asm volatile("dssall;sync"); 736 /* L3 cache is already disabled, no need to clear L3E */ 737 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 738 do { 739 x = mfspr(SPR_L3CR); 740 } while (x & L3CR_L3I); 741 742 /* 6: Clear L3CLKEN to 0 */ 743 l3cr &= ~L3CR_L3CLKEN; 744 mtspr(SPR_L3CR, l3cr); 745 746 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 747 __asm volatile("sync"); 748 delay(100); 749 750 /* 8: Set L3E and L3CLKEN */ 751 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 752 mtspr(SPR_L3CR, l3cr); 753 754 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 755 __asm volatile("sync"); 756 delay(100); 757 } 758 759 void 760 cpu_config_l2cr(int pvr) 761 { 762 register_t l2cr; 763 764 l2cr = mfspr(SPR_L2CR); 765 766 /* 767 * For MP systems, the firmware may only configure the L2 cache 768 * on the first CPU. In this case, assume that the other CPUs 769 * should use the same value for L2CR. 770 */ 771 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 772 l2cr_config = l2cr; 773 } 774 775 /* 776 * Configure L2 cache if not enabled. 777 */ 778 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 779 cpu_enable_l2cr(l2cr_config); 780 l2cr = mfspr(SPR_L2CR); 781 } 782 783 if ((l2cr & L2CR_L2E) == 0) { 784 aprint_normal(" L2 cache present but not enabled "); 785 return; 786 } 787 788 aprint_normal(","); 789 if ((pvr >> 16) == IBM750FX || 790 (pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 791 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) { 792 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 793 } else { 794 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 795 } 796 } 797 798 void 799 cpu_config_l3cr(int vers) 800 { 801 register_t l2cr; 802 register_t l3cr; 803 804 l2cr = mfspr(SPR_L2CR); 805 806 /* 807 * For MP systems, the firmware may only configure the L2 cache 808 * on the first CPU. In this case, assume that the other CPUs 809 * should use the same value for L2CR. 810 */ 811 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 812 l2cr_config = l2cr; 813 } 814 815 /* 816 * Configure L2 cache if not enabled. 817 */ 818 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 819 cpu_enable_l2cr(l2cr_config); 820 l2cr = mfspr(SPR_L2CR); 821 } 822 823 aprint_normal(","); 824 switch (vers) { 825 case MPC7447A: 826 case MPC7457: 827 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 828 return; 829 case MPC7448: 830 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 831 return; 832 default: 833 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 834 break; 835 } 836 837 l3cr = mfspr(SPR_L3CR); 838 839 /* 840 * For MP systems, the firmware may only configure the L3 cache 841 * on the first CPU. In this case, assume that the other CPUs 842 * should use the same value for L3CR. 843 */ 844 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 845 l3cr_config = l3cr; 846 } 847 848 /* 849 * Configure L3 cache if not enabled. 850 */ 851 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 852 cpu_enable_l3cr(l3cr_config); 853 l3cr = mfspr(SPR_L3CR); 854 } 855 856 if (l3cr & L3CR_L3E) { 857 aprint_normal(","); 858 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 859 } 860 } 861 862 void 863 cpu_probe_speed(struct cpu_info *ci) 864 { 865 uint64_t cps; 866 867 mtspr(SPR_MMCR0, MMCR0_FC); 868 mtspr(SPR_PMC1, 0); 869 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 870 delay(100000); 871 cps = (mfspr(SPR_PMC1) * 10) + 4999; 872 873 mtspr(SPR_MMCR0, MMCR0_FC); 874 875 ci->ci_khz = cps / 1000; 876 } 877 878 #if NSYSMON_ENVSYS > 0 879 const struct envsys_range cpu_tau_ranges[] = { 880 { 0, 0, ENVSYS_STEMP} 881 }; 882 883 struct envsys_basic_info cpu_tau_info[] = { 884 { 0, ENVSYS_STEMP, "CPU temp", 0, 0, ENVSYS_FVALID} 885 }; 886 887 void 888 cpu_tau_setup(struct cpu_info *ci) 889 { 890 struct { 891 struct sysmon_envsys sme; 892 struct envsys_tre_data tau_info; 893 } *datap; 894 int error; 895 896 datap = malloc(sizeof(*datap), M_DEVBUF, M_WAITOK | M_ZERO); 897 898 ci->ci_sysmon_cookie = &datap->sme; 899 datap->sme.sme_nsensors = 1; 900 datap->sme.sme_envsys_version = 1000; 901 datap->sme.sme_ranges = cpu_tau_ranges; 902 datap->sme.sme_sensor_info = cpu_tau_info; 903 datap->sme.sme_sensor_data = &datap->tau_info; 904 905 datap->sme.sme_sensor_data->sensor = 0; 906 datap->sme.sme_sensor_data->warnflags = ENVSYS_WARN_OK; 907 datap->sme.sme_sensor_data->validflags = ENVSYS_FVALID|ENVSYS_FCURVALID; 908 datap->sme.sme_cookie = ci; 909 datap->sme.sme_gtredata = cpu_tau_gtredata; 910 datap->sme.sme_streinfo = cpu_tau_streinfo; 911 datap->sme.sme_flags = 0; 912 913 if ((error = sysmon_envsys_register(&datap->sme)) != 0) 914 aprint_error("%s: unable to register with sysmon (%d)\n", 915 ci->ci_dev->dv_xname, error); 916 } 917 918 919 /* Find the temperature of the CPU. */ 920 int 921 cpu_tau_gtredata(struct sysmon_envsys *sme, struct envsys_tre_data *tred) 922 { 923 int i, threshold, count; 924 925 if (tred->sensor != 0) { 926 tred->validflags = 0; 927 return 0; 928 } 929 930 threshold = 64; /* Half of the 7-bit sensor range */ 931 mtspr(SPR_THRM1, 0); 932 mtspr(SPR_THRM2, 0); 933 /* XXX This counter is supposed to be "at least 20 microseonds, in 934 * XXX units of clock cycles". Since we don't have convenient 935 * XXX access to the CPU speed, set it to a conservative value, 936 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 937 * XXX the fastest G3 processor is 700MHz) . The cost is that 938 * XXX measuring the temperature takes a bit longer. 939 */ 940 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 941 942 /* Successive-approximation code adapted from Motorola 943 * application note AN1800/D, "Programming the Thermal Assist 944 * Unit in the MPC750 Microprocessor". 945 */ 946 for (i = 4; i >= 0 ; i--) { 947 mtspr(SPR_THRM1, 948 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 949 count = 0; 950 while ((count < 100) && 951 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 952 count++; 953 delay(1); 954 } 955 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 956 /* The interrupt bit was set, meaning the 957 * temperature was above the threshold 958 */ 959 threshold += 2 << i; 960 } else { 961 /* Temperature was below the threshold */ 962 threshold -= 2 << i; 963 } 964 } 965 threshold += 2; 966 967 /* Convert the temperature in degrees C to microkelvin */ 968 sme->sme_sensor_data->cur.data_us = (threshold * 1000000) + 273150000; 969 970 *tred = *sme->sme_sensor_data; 971 972 return 0; 973 } 974 975 int 976 cpu_tau_streinfo(struct sysmon_envsys *sme, struct envsys_basic_info *binfo) 977 { 978 979 /* There is nothing to set here. */ 980 return (EINVAL); 981 } 982 #endif /* NSYSMON_ENVSYS > 0 */ 983
Indexes created Sun Sep 28 16:09:52 GMT 2025