cpu_subr.c revision 1.44
1 /* $NetBSD: cpu_subr.c,v 1.44 2008/02/14 19:41:54 garbled Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.44 2008/02/14 19:41:54 garbled Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/types.h> 48 #include <sys/lwp.h> 49 #include <sys/user.h> 50 #include <sys/malloc.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <powerpc/oea/hid.h> 55 #include <powerpc/oea/hid_601.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/cpufeat.h> 58 59 #include <dev/sysmon/sysmonvar.h> 60 61 static void cpu_enable_l2cr(register_t); 62 static void cpu_enable_l3cr(register_t); 63 static void cpu_config_l2cr(int); 64 static void cpu_config_l3cr(int); 65 static void cpu_probe_speed(struct cpu_info *); 66 static void cpu_idlespin(void); 67 #if NSYSMON_ENVSYS > 0 68 static void cpu_tau_setup(struct cpu_info *); 69 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 70 #endif 71 72 int cpu; 73 int ncpus; 74 75 struct fmttab { 76 register_t fmt_mask; 77 register_t fmt_value; 78 const char *fmt_string; 79 }; 80 81 static const struct fmttab cpu_7450_l2cr_formats[] = { 82 { L2CR_L2E, 0, " disabled" }, 83 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 84 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 85 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 86 { L2CR_L2E, ~0, " 256KB L2 cache" }, 87 { L2CR_L2PE, 0, " no parity" }, 88 { L2CR_L2PE, ~0, " parity enabled" }, 89 { 0, 0, NULL } 90 }; 91 92 static const struct fmttab cpu_7448_l2cr_formats[] = { 93 { L2CR_L2E, 0, " disabled" }, 94 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 95 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 96 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 97 { L2CR_L2E, ~0, " 1MB L2 cache" }, 98 { L2CR_L2PE, 0, " no parity" }, 99 { L2CR_L2PE, ~0, " parity enabled" }, 100 { 0, 0, NULL } 101 }; 102 103 static const struct fmttab cpu_7457_l2cr_formats[] = { 104 { L2CR_L2E, 0, " disabled" }, 105 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 106 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 107 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 108 { L2CR_L2E, ~0, " 512KB L2 cache" }, 109 { L2CR_L2PE, 0, " no parity" }, 110 { L2CR_L2PE, ~0, " parity enabled" }, 111 { 0, 0, NULL } 112 }; 113 114 static const struct fmttab cpu_7450_l3cr_formats[] = { 115 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 116 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 117 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 118 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 119 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 120 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 121 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 122 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 123 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 124 { L3CR_L3SIZ, ~0, " L3 cache" }, 125 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 126 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 127 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 128 { L3CR_L3CLK, ~0, " at" }, 129 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 130 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 131 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 132 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 133 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 134 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 135 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 136 { L3CR_L3CLK, ~0, " ratio" }, 137 { 0, 0, NULL }, 138 }; 139 140 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 141 { L2CR_L2E, 0, " disabled" }, 142 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 143 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 144 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 145 { 0, ~0, " 512KB" }, 146 { L2CR_L2WT, L2CR_L2WT, " WT" }, 147 { L2CR_L2WT, 0, " WB" }, 148 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 149 { 0, ~0, " L2 cache" }, 150 { 0, 0, NULL } 151 }; 152 153 static const struct fmttab cpu_l2cr_formats[] = { 154 { L2CR_L2E, 0, " disabled" }, 155 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 156 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 157 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 158 { L2CR_L2PE, L2CR_L2PE, " parity" }, 159 { L2CR_L2PE, 0, " no-parity" }, 160 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 161 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 162 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 163 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 164 { L2CR_L2WT, L2CR_L2WT, " WT" }, 165 { L2CR_L2WT, 0, " WB" }, 166 { L2CR_L2E, ~0, " L2 cache" }, 167 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 168 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 169 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 170 { L2CR_L2CLK, ~0, " at" }, 171 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 172 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 173 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 174 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 175 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 176 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 177 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 178 { L2CR_L2CLK, ~0, " ratio" }, 179 { 0, 0, NULL } 180 }; 181 182 static void cpu_fmttab_print(const struct fmttab *, register_t); 183 184 struct cputab { 185 const char name[8]; 186 uint16_t version; 187 uint16_t revfmt; 188 }; 189 #define REVFMT_MAJMIN 1 /* %u.%u */ 190 #define REVFMT_HEX 2 /* 0x%04x */ 191 #define REVFMT_DEC 3 /* %u */ 192 static const struct cputab models[] = { 193 { "601", MPC601, REVFMT_DEC }, 194 { "602", MPC602, REVFMT_DEC }, 195 { "603", MPC603, REVFMT_MAJMIN }, 196 { "603e", MPC603e, REVFMT_MAJMIN }, 197 { "603ev", MPC603ev, REVFMT_MAJMIN }, 198 { "G2", MPCG2, REVFMT_MAJMIN }, 199 { "604", MPC604, REVFMT_MAJMIN }, 200 { "604e", MPC604e, REVFMT_MAJMIN }, 201 { "604ev", MPC604ev, REVFMT_MAJMIN }, 202 { "620", MPC620, REVFMT_HEX }, 203 { "750", MPC750, REVFMT_MAJMIN }, 204 { "750FX", IBM750FX, REVFMT_MAJMIN }, 205 { "7400", MPC7400, REVFMT_MAJMIN }, 206 { "7410", MPC7410, REVFMT_MAJMIN }, 207 { "7450", MPC7450, REVFMT_MAJMIN }, 208 { "7455", MPC7455, REVFMT_MAJMIN }, 209 { "7457", MPC7457, REVFMT_MAJMIN }, 210 { "7447A", MPC7447A, REVFMT_MAJMIN }, 211 { "7448", MPC7448, REVFMT_MAJMIN }, 212 { "8240", MPC8240, REVFMT_MAJMIN }, 213 { "8245", MPC8245, REVFMT_MAJMIN }, 214 { "970", IBM970, REVFMT_MAJMIN }, 215 { "970FX", IBM970FX, REVFMT_MAJMIN }, 216 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 217 { "", 0, REVFMT_HEX } 218 }; 219 220 #ifdef MULTIPROCESSOR 221 struct cpu_info cpu_info[CPU_MAXNUM] = { { .ci_curlwp = &lwp0, }, }; 222 volatile struct cpu_hatch_data *cpu_hatch_data; 223 volatile int cpu_hatch_stack; 224 extern int ticks_per_intr; 225 #include <powerpc/oea/bat.h> 226 #include <arch/powerpc/pic/picvar.h> 227 #include <arch/powerpc/pic/ipivar.h> 228 extern struct bat battable[]; 229 #else 230 struct cpu_info cpu_info[1] = { { .ci_curlwp = &lwp0, }, }; 231 #endif /*MULTIPROCESSOR*/ 232 233 int cpu_altivec; 234 int cpu_psluserset, cpu_pslusermod; 235 char cpu_model[80]; 236 237 /* This is to be called from locore.S, and nowhere else. */ 238 239 void 240 cpu_model_init(void) 241 { 242 u_int pvr, vers; 243 244 pvr = mfpvr(); 245 vers = pvr >> 16; 246 247 oeacpufeat = 0; 248 249 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 250 vers == IBMCELL || vers == IBMPOWER6P5) 251 oeacpufeat |= OEACPU_64 | OEACPU_64_BRIDGE | OEACPU_NOBAT; 252 253 if (vers == MPC601) 254 oeacpufeat |= OEACPU_601; 255 } 256 257 void 258 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 259 { 260 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 261 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 262 (data & fmt->fmt_mask) == fmt->fmt_value) 263 aprint_normal("%s", fmt->fmt_string); 264 } 265 } 266 267 void 268 cpu_idlespin(void) 269 { 270 register_t msr; 271 272 if (powersave <= 0) 273 return; 274 275 __asm volatile( 276 "sync;" 277 "mfmsr %0;" 278 "oris %0,%0,%1@h;" /* enter power saving mode */ 279 "mtmsr %0;" 280 "isync;" 281 : "=r"(msr) 282 : "J"(PSL_POW)); 283 } 284 285 void 286 cpu_probe_cache(void) 287 { 288 u_int assoc, pvr, vers; 289 290 pvr = mfpvr(); 291 vers = pvr >> 16; 292 293 294 /* Presently common across almost all implementations. */ 295 curcpu()->ci_ci.dcache_line_size = 32; 296 curcpu()->ci_ci.icache_line_size = 32; 297 298 299 switch (vers) { 300 #define K *1024 301 case IBM750FX: 302 case MPC601: 303 case MPC750: 304 case MPC7447A: 305 case MPC7448: 306 case MPC7450: 307 case MPC7455: 308 case MPC7457: 309 curcpu()->ci_ci.dcache_size = 32 K; 310 curcpu()->ci_ci.icache_size = 32 K; 311 assoc = 8; 312 break; 313 case MPC603: 314 curcpu()->ci_ci.dcache_size = 8 K; 315 curcpu()->ci_ci.icache_size = 8 K; 316 assoc = 2; 317 break; 318 case MPC603e: 319 case MPC603ev: 320 case MPC604: 321 case MPC8240: 322 case MPC8245: 323 case MPCG2: 324 curcpu()->ci_ci.dcache_size = 16 K; 325 curcpu()->ci_ci.icache_size = 16 K; 326 assoc = 4; 327 break; 328 case MPC604e: 329 case MPC604ev: 330 curcpu()->ci_ci.dcache_size = 32 K; 331 curcpu()->ci_ci.icache_size = 32 K; 332 assoc = 4; 333 break; 334 case IBMPOWER3II: 335 curcpu()->ci_ci.dcache_size = 64 K; 336 curcpu()->ci_ci.icache_size = 32 K; 337 curcpu()->ci_ci.dcache_line_size = 128; 338 curcpu()->ci_ci.icache_line_size = 128; 339 assoc = 128; /* not a typo */ 340 break; 341 case IBM970: 342 case IBM970FX: 343 curcpu()->ci_ci.dcache_size = 32 K; 344 curcpu()->ci_ci.icache_size = 64 K; 345 curcpu()->ci_ci.dcache_line_size = 128; 346 curcpu()->ci_ci.icache_line_size = 128; 347 assoc = 2; 348 break; 349 350 default: 351 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 352 curcpu()->ci_ci.icache_size = PAGE_SIZE; 353 assoc = 1; 354 #undef K 355 } 356 357 /* 358 * Possibly recolor. 359 */ 360 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 361 } 362 363 struct cpu_info * 364 cpu_attach_common(struct device *self, int id) 365 { 366 struct cpu_info *ci; 367 u_int pvr, vers; 368 369 ci = &cpu_info[id]; 370 #ifndef MULTIPROCESSOR 371 /* 372 * If this isn't the primary CPU, print an error message 373 * and just bail out. 374 */ 375 if (id != 0) { 376 aprint_normal(": ID %d\n", id); 377 aprint_normal("%s: processor off-line; multiprocessor support " 378 "not present in kernel\n", self->dv_xname); 379 return (NULL); 380 } 381 #endif 382 383 ci->ci_cpuid = id; 384 ci->ci_intrdepth = -1; 385 ci->ci_dev = self; 386 ci->ci_idlespin = cpu_idlespin; 387 388 pvr = mfpvr(); 389 vers = (pvr >> 16) & 0xffff; 390 391 switch (id) { 392 case 0: 393 /* load my cpu_number to PIR */ 394 switch (vers) { 395 case MPC601: 396 case MPC604: 397 case MPC604e: 398 case MPC604ev: 399 case MPC7400: 400 case MPC7410: 401 case MPC7447A: 402 case MPC7448: 403 case MPC7450: 404 case MPC7455: 405 case MPC7457: 406 mtspr(SPR_PIR, id); 407 } 408 cpu_setup(self, ci); 409 break; 410 default: 411 if (id >= CPU_MAXNUM) { 412 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 413 panic("cpuattach"); 414 } 415 #ifndef MULTIPROCESSOR 416 aprint_normal(" not configured\n"); 417 return NULL; 418 #else 419 mi_cpu_attach(ci); 420 break; 421 #endif 422 } 423 return (ci); 424 } 425 426 void 427 cpu_setup(self, ci) 428 struct device *self; 429 struct cpu_info *ci; 430 { 431 u_int hid0, hid0_save, pvr, vers; 432 const char *bitmask; 433 char hidbuf[128]; 434 char model[80]; 435 436 pvr = mfpvr(); 437 vers = (pvr >> 16) & 0xffff; 438 439 cpu_identify(model, sizeof(model)); 440 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 441 cpu_number() == 0 ? " (primary)" : ""); 442 443 hid0_save = hid0 = mfspr(SPR_HID0); 444 445 cpu_probe_cache(); 446 447 /* 448 * Configure power-saving mode. 449 */ 450 switch (vers) { 451 case MPC604: 452 case MPC604e: 453 case MPC604ev: 454 /* 455 * Do not have HID0 support settings, but can support 456 * MSR[POW] off 457 */ 458 powersave = 1; 459 break; 460 461 case MPC603: 462 case MPC603e: 463 case MPC603ev: 464 case MPC750: 465 case IBM750FX: 466 case MPC7400: 467 case MPC7410: 468 case MPC8240: 469 case MPC8245: 470 case MPCG2: 471 /* Select DOZE mode. */ 472 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 473 hid0 |= HID0_DOZE | HID0_DPM; 474 powersave = 1; 475 break; 476 477 case MPC7447A: 478 case MPC7448: 479 case MPC7457: 480 case MPC7455: 481 case MPC7450: 482 /* Enable the 7450 branch caches */ 483 hid0 |= HID0_SGE | HID0_BTIC; 484 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 485 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 486 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 487 hid0 &= ~HID0_BTIC; 488 /* Select NAP mode. */ 489 hid0 &= ~(HID0_HIGH_BAT_EN | HID0_SLEEP); 490 hid0 |= HID0_NAP | HID0_DPM /* | HID0_XBSEN */; 491 powersave = 1; 492 break; 493 494 case IBM970: 495 case IBM970FX: 496 case IBMPOWER3II: 497 default: 498 /* No power-saving mode is available. */ ; 499 } 500 501 #ifdef NAPMODE 502 switch (vers) { 503 case IBM750FX: 504 case MPC750: 505 case MPC7400: 506 /* Select NAP mode. */ 507 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 508 hid0 |= HID0_NAP; 509 break; 510 } 511 #endif 512 513 switch (vers) { 514 case IBM750FX: 515 case MPC750: 516 hid0 &= ~HID0_DBP; /* XXX correct? */ 517 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 518 break; 519 520 case MPC7400: 521 case MPC7410: 522 hid0 &= ~HID0_SPD; 523 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 524 hid0 |= HID0_EIEC; 525 break; 526 } 527 528 if (hid0 != hid0_save) { 529 mtspr(SPR_HID0, hid0); 530 __asm volatile("sync;isync"); 531 } 532 533 534 switch (vers) { 535 case MPC601: 536 bitmask = HID0_601_BITMASK; 537 break; 538 case MPC7450: 539 case MPC7455: 540 case MPC7457: 541 bitmask = HID0_7450_BITMASK; 542 break; 543 case IBM970: 544 case IBM970FX: 545 bitmask = 0; 546 break; 547 default: 548 bitmask = HID0_BITMASK; 549 break; 550 } 551 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 552 aprint_normal("%s: HID0 %s, powersave: %d\n", self->dv_xname, hidbuf, 553 powersave); 554 555 ci->ci_khz = 0; 556 557 /* 558 * Display speed and cache configuration. 559 */ 560 switch (vers) { 561 case MPC604: 562 case MPC604e: 563 case MPC604ev: 564 case MPC750: 565 case IBM750FX: 566 case MPC7400: 567 case MPC7410: 568 case MPC7447A: 569 case MPC7448: 570 case MPC7450: 571 case MPC7455: 572 case MPC7457: 573 aprint_normal("%s: ", self->dv_xname); 574 cpu_probe_speed(ci); 575 aprint_normal("%u.%02u MHz", 576 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 577 switch (vers) { 578 case MPC7450: /* 7441 does not have L3! */ 579 case MPC7455: /* 7445 does not have L3! */ 580 case MPC7457: /* 7447 does not have L3! */ 581 cpu_config_l3cr(vers); 582 break; 583 case IBM750FX: 584 case MPC750: 585 case MPC7400: 586 case MPC7410: 587 case MPC7447A: 588 case MPC7448: 589 cpu_config_l2cr(pvr); 590 break; 591 default: 592 break; 593 } 594 aprint_normal("\n"); 595 break; 596 } 597 598 #if NSYSMON_ENVSYS > 0 599 /* 600 * Attach MPC750 temperature sensor to the envsys subsystem. 601 * XXX the 74xx series also has this sensor, but it is not 602 * XXX supported by Motorola and may return values that are off by 603 * XXX 35-55 degrees C. 604 */ 605 if (vers == MPC750 || vers == IBM750FX) 606 cpu_tau_setup(ci); 607 #endif 608 609 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 610 NULL, self->dv_xname, "clock"); 611 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 612 NULL, self->dv_xname, "soft clock"); 613 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 614 NULL, self->dv_xname, "soft net"); 615 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 616 NULL, self->dv_xname, "soft serial"); 617 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 618 NULL, self->dv_xname, "traps"); 619 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 620 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 621 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 622 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 623 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 624 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 625 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 626 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 627 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 628 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 629 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 630 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 631 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 632 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 633 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 634 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 635 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 636 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 637 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 638 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 639 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 640 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 641 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 642 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 643 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 644 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 645 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 646 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 647 #ifdef ALTIVEC 648 if (cpu_altivec) { 649 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 650 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 651 } 652 #endif 653 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 654 NULL, self->dv_xname, "IPIs"); 655 } 656 657 /* 658 * According to a document labeled "PVR Register Settings": 659 ** For integrated microprocessors the PVR register inside the device 660 ** will identify the version of the microprocessor core. You must also 661 ** read the Device ID, PCI register 02, to identify the part and the 662 ** Revision ID, PCI register 08, to identify the revision of the 663 ** integrated microprocessor. 664 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 665 */ 666 667 void 668 cpu_identify(char *str, size_t len) 669 { 670 u_int pvr, major, minor; 671 uint16_t vers, rev, revfmt; 672 const struct cputab *cp; 673 const char *name; 674 size_t n; 675 676 pvr = mfpvr(); 677 vers = pvr >> 16; 678 rev = pvr; 679 680 switch (vers) { 681 case MPC7410: 682 minor = (pvr >> 0) & 0xff; 683 major = minor <= 4 ? 1 : 2; 684 break; 685 case MPCG2: /*XXX see note above */ 686 major = (pvr >> 4) & 0xf; 687 minor = (pvr >> 0) & 0xf; 688 break; 689 default: 690 major = (pvr >> 8) & 0xf; 691 minor = (pvr >> 0) & 0xf; 692 } 693 694 for (cp = models; cp->name[0] != '\0'; cp++) { 695 if (cp->version == vers) 696 break; 697 } 698 699 if (str == NULL) { 700 str = cpu_model; 701 len = sizeof(cpu_model); 702 cpu = vers; 703 } 704 705 revfmt = cp->revfmt; 706 name = cp->name; 707 if (rev == MPC750 && pvr == 15) { 708 name = "755"; 709 revfmt = REVFMT_HEX; 710 } 711 712 if (cp->name[0] != '\0') { 713 n = snprintf(str, len, "%s (Revision ", cp->name); 714 } else { 715 n = snprintf(str, len, "Version %#x (Revision ", vers); 716 } 717 if (len > n) { 718 switch (revfmt) { 719 case REVFMT_MAJMIN: 720 snprintf(str + n, len - n, "%u.%u)", major, minor); 721 break; 722 case REVFMT_HEX: 723 snprintf(str + n, len - n, "0x%04x)", rev); 724 break; 725 case REVFMT_DEC: 726 snprintf(str + n, len - n, "%u)", rev); 727 break; 728 } 729 } 730 } 731 732 #ifdef L2CR_CONFIG 733 u_int l2cr_config = L2CR_CONFIG; 734 #else 735 u_int l2cr_config = 0; 736 #endif 737 738 #ifdef L3CR_CONFIG 739 u_int l3cr_config = L3CR_CONFIG; 740 #else 741 u_int l3cr_config = 0; 742 #endif 743 744 void 745 cpu_enable_l2cr(register_t l2cr) 746 { 747 register_t msr, x; 748 uint16_t vers; 749 750 vers = mfpvr() >> 16; 751 752 /* Disable interrupts and set the cache config bits. */ 753 msr = mfmsr(); 754 mtmsr(msr & ~PSL_EE); 755 #ifdef ALTIVEC 756 if (cpu_altivec) 757 __asm volatile("dssall"); 758 #endif 759 __asm volatile("sync"); 760 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 761 __asm volatile("sync"); 762 763 /* Wait for L2 clock to be stable (640 L2 clocks). */ 764 delay(100); 765 766 /* Invalidate all L2 contents. */ 767 if (MPC745X_P(vers)) { 768 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 769 do { 770 x = mfspr(SPR_L2CR); 771 } while (x & L2CR_L2I); 772 } else { 773 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 774 do { 775 x = mfspr(SPR_L2CR); 776 } while (x & L2CR_L2IP); 777 } 778 /* Enable L2 cache. */ 779 l2cr |= L2CR_L2E; 780 mtspr(SPR_L2CR, l2cr); 781 mtmsr(msr); 782 } 783 784 void 785 cpu_enable_l3cr(register_t l3cr) 786 { 787 register_t x; 788 789 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 790 791 /* 792 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 793 * L3CLKEN. (also mask off reserved bits in case they were included 794 * in L3CR_CONFIG) 795 */ 796 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 797 mtspr(SPR_L3CR, l3cr); 798 799 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 800 l3cr |= 0x04000000; 801 mtspr(SPR_L3CR, l3cr); 802 803 /* 3: Set L3CLKEN to 1*/ 804 l3cr |= L3CR_L3CLKEN; 805 mtspr(SPR_L3CR, l3cr); 806 807 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 808 __asm volatile("dssall;sync"); 809 /* L3 cache is already disabled, no need to clear L3E */ 810 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 811 do { 812 x = mfspr(SPR_L3CR); 813 } while (x & L3CR_L3I); 814 815 /* 6: Clear L3CLKEN to 0 */ 816 l3cr &= ~L3CR_L3CLKEN; 817 mtspr(SPR_L3CR, l3cr); 818 819 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 820 __asm volatile("sync"); 821 delay(100); 822 823 /* 8: Set L3E and L3CLKEN */ 824 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 825 mtspr(SPR_L3CR, l3cr); 826 827 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 828 __asm volatile("sync"); 829 delay(100); 830 } 831 832 void 833 cpu_config_l2cr(int pvr) 834 { 835 register_t l2cr; 836 u_int vers = (pvr >> 16) & 0xffff; 837 838 l2cr = mfspr(SPR_L2CR); 839 840 /* 841 * For MP systems, the firmware may only configure the L2 cache 842 * on the first CPU. In this case, assume that the other CPUs 843 * should use the same value for L2CR. 844 */ 845 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 846 l2cr_config = l2cr; 847 } 848 849 /* 850 * Configure L2 cache if not enabled. 851 */ 852 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 853 cpu_enable_l2cr(l2cr_config); 854 l2cr = mfspr(SPR_L2CR); 855 } 856 857 if ((l2cr & L2CR_L2E) == 0) { 858 aprint_normal(" L2 cache present but not enabled "); 859 return; 860 } 861 aprint_normal(","); 862 863 switch (vers) { 864 case IBM750FX: 865 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 866 break; 867 case MPC750: 868 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 869 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 870 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 871 else 872 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 873 break; 874 case MPC7447A: 875 case MPC7457: 876 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 877 return; 878 case MPC7448: 879 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 880 return; 881 case MPC7450: 882 case MPC7455: 883 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 884 break; 885 default: 886 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 887 break; 888 } 889 } 890 891 void 892 cpu_config_l3cr(int vers) 893 { 894 register_t l2cr; 895 register_t l3cr; 896 897 l2cr = mfspr(SPR_L2CR); 898 899 /* 900 * For MP systems, the firmware may only configure the L2 cache 901 * on the first CPU. In this case, assume that the other CPUs 902 * should use the same value for L2CR. 903 */ 904 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 905 l2cr_config = l2cr; 906 } 907 908 /* 909 * Configure L2 cache if not enabled. 910 */ 911 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 912 cpu_enable_l2cr(l2cr_config); 913 l2cr = mfspr(SPR_L2CR); 914 } 915 916 aprint_normal(","); 917 switch (vers) { 918 case MPC7447A: 919 case MPC7457: 920 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 921 return; 922 case MPC7448: 923 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 924 return; 925 default: 926 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 927 break; 928 } 929 930 l3cr = mfspr(SPR_L3CR); 931 932 /* 933 * For MP systems, the firmware may only configure the L3 cache 934 * on the first CPU. In this case, assume that the other CPUs 935 * should use the same value for L3CR. 936 */ 937 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 938 l3cr_config = l3cr; 939 } 940 941 /* 942 * Configure L3 cache if not enabled. 943 */ 944 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 945 cpu_enable_l3cr(l3cr_config); 946 l3cr = mfspr(SPR_L3CR); 947 } 948 949 if (l3cr & L3CR_L3E) { 950 aprint_normal(","); 951 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 952 } 953 } 954 955 void 956 cpu_probe_speed(struct cpu_info *ci) 957 { 958 uint64_t cps; 959 960 mtspr(SPR_MMCR0, MMCR0_FC); 961 mtspr(SPR_PMC1, 0); 962 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 963 delay(100000); 964 cps = (mfspr(SPR_PMC1) * 10) + 4999; 965 966 mtspr(SPR_MMCR0, MMCR0_FC); 967 968 ci->ci_khz = cps / 1000; 969 } 970 971 #if NSYSMON_ENVSYS > 0 972 void 973 cpu_tau_setup(struct cpu_info *ci) 974 { 975 struct sysmon_envsys *sme; 976 envsys_data_t sensor; 977 int error; 978 979 sme = sysmon_envsys_create(); 980 981 sensor.state = ENVSYS_SVALID; 982 sensor.units = ENVSYS_STEMP; 983 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 984 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 985 sysmon_envsys_destroy(sme); 986 return; 987 } 988 989 sme->sme_name = ci->ci_dev->dv_xname; 990 sme->sme_cookie = ci; 991 sme->sme_refresh = cpu_tau_refresh; 992 993 if ((error = sysmon_envsys_register(sme)) != 0) { 994 aprint_error("%s: unable to register with sysmon (%d)\n", 995 ci->ci_dev->dv_xname, error); 996 sysmon_envsys_destroy(sme); 997 } 998 } 999 1000 1001 /* Find the temperature of the CPU. */ 1002 void 1003 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1004 { 1005 int i, threshold, count; 1006 1007 threshold = 64; /* Half of the 7-bit sensor range */ 1008 mtspr(SPR_THRM1, 0); 1009 mtspr(SPR_THRM2, 0); 1010 /* XXX This counter is supposed to be "at least 20 microseonds, in 1011 * XXX units of clock cycles". Since we don't have convenient 1012 * XXX access to the CPU speed, set it to a conservative value, 1013 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 1014 * XXX the fastest G3 processor is 700MHz) . The cost is that 1015 * XXX measuring the temperature takes a bit longer. 1016 */ 1017 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 1018 1019 /* Successive-approximation code adapted from Motorola 1020 * application note AN1800/D, "Programming the Thermal Assist 1021 * Unit in the MPC750 Microprocessor". 1022 */ 1023 for (i = 4; i >= 0 ; i--) { 1024 mtspr(SPR_THRM1, 1025 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1026 count = 0; 1027 while ((count < 100) && 1028 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1029 count++; 1030 delay(1); 1031 } 1032 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1033 /* The interrupt bit was set, meaning the 1034 * temperature was above the threshold 1035 */ 1036 threshold += 2 << i; 1037 } else { 1038 /* Temperature was below the threshold */ 1039 threshold -= 2 << i; 1040 } 1041 } 1042 threshold += 2; 1043 1044 /* Convert the temperature in degrees C to microkelvin */ 1045 edata->value_cur = (threshold * 1000000) + 273150000; 1046 } 1047 #endif /* NSYSMON_ENVSYS > 0 */ 1048 1049 #ifdef MULTIPROCESSOR 1050 int 1051 cpu_spinup(struct device *self, struct cpu_info *ci) 1052 { 1053 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1054 struct pglist mlist; 1055 int i, error, pvr, vers; 1056 char *cp; 1057 1058 pvr = mfpvr(); 1059 vers = pvr >> 16; 1060 KASSERT(ci != curcpu()); 1061 1062 /* 1063 * Allocate some contiguous pages for the intteup PCB and stack 1064 * from the lowest 256MB (because bat0 always maps it va == pa). 1065 */ 1066 error = uvm_pglistalloc(INTSTK, 0x0, 0x10000000, 0, 0, &mlist, 1, 1); 1067 if (error) { 1068 aprint_error(": unable to allocate idle stack\n"); 1069 return -1; 1070 } 1071 1072 KASSERT(ci != &cpu_info[0]); 1073 1074 cp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1075 memset(cp, 0, INTSTK); 1076 1077 ci->ci_intstk = cp; 1078 1079 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1080 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1081 ci->ci_curpcb = &ci->ci_curlwp->l_addr->u_pcb; 1082 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1083 1084 cpu_hatch_data = h; 1085 h->running = 0; 1086 h->self = self; 1087 h->ci = ci; 1088 h->pir = ci->ci_cpuid; 1089 cpu_hatch_stack = (uint32_t)cp + INTSTK - sizeof(struct trapframe); 1090 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1091 1092 /* copy special registers */ 1093 h->hid0 = mfspr(SPR_HID0); 1094 __asm volatile ("mfsdr1 %0" : "=r"(h->sdr1)); 1095 for (i = 0; i < 16; i++) 1096 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1097 "r"(i << ADDR_SR_SHFT)); 1098 /* copy the bat regs */ 1099 __asm volatile ("mfibatu %0,0" : "=r"(h->batu[0])); 1100 __asm volatile ("mfibatl %0,0" : "=r"(h->batl[0])); 1101 __asm volatile ("mfibatu %0,1" : "=r"(h->batu[1])); 1102 __asm volatile ("mfibatl %0,1" : "=r"(h->batl[1])); 1103 __asm volatile ("mfibatu %0,2" : "=r"(h->batu[2])); 1104 __asm volatile ("mfibatl %0,2" : "=r"(h->batl[2])); 1105 __asm volatile ("mfibatu %0,3" : "=r"(h->batu[3])); 1106 __asm volatile ("mfibatl %0,3" : "=r"(h->batl[3])); 1107 __asm volatile ("sync; isync"); 1108 1109 if (md_setup_trampoline(h, ci) == -1) 1110 return -1; 1111 md_presync_timebase(h); 1112 md_start_timebase(h); 1113 1114 /* wait for secondary printf */ 1115 delay(200000); 1116 1117 if (h->running == 0) { 1118 aprint_error(":CPU %d didn't start\n", ci->ci_cpuid); 1119 return -1; 1120 } 1121 1122 /* Register IPI Interrupt */ 1123 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1124 1125 return 0; 1126 } 1127 1128 static volatile int start_secondary_cpu; 1129 1130 void 1131 cpu_hatch() 1132 { 1133 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1134 struct cpu_info * const ci = h->ci; 1135 u_int msr; 1136 int i; 1137 1138 /* Initialize timebase. */ 1139 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1140 1141 /* Set PIR (Processor Identification Register). i.e. whoami */ 1142 mtspr(SPR_PIR, h->pir); 1143 __asm volatile ("mtsprg 0,%0" :: "r"(ci)); 1144 1145 /* Initialize MMU. */ 1146 __asm ("mtibatu 0,%0" :: "r"(h->batu[0])); 1147 __asm ("mtibatl 0,%0" :: "r"(h->batl[0])); 1148 __asm ("mtibatu 1,%0" :: "r"(h->batu[1])); 1149 __asm ("mtibatl 1,%0" :: "r"(h->batl[1])); 1150 __asm ("mtibatu 2,%0" :: "r"(h->batu[2])); 1151 __asm ("mtibatl 2,%0" :: "r"(h->batl[2])); 1152 __asm ("mtibatu 3,%0" :: "r"(h->batu[3])); 1153 __asm ("mtibatl 3,%0" :: "r"(h->batl[3])); 1154 1155 mtspr(SPR_HID0, h->hid0); 1156 1157 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1158 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1159 1160 for (i = 0; i < 16; i++) 1161 __asm ("mtsrin %0,%1" :: "r"(h->sr[i]), "r"(i << ADDR_SR_SHFT)); 1162 1163 __asm ("mtsdr1 %0" :: "r"(h->sdr1)); 1164 __asm volatile ("isync"); 1165 1166 /* Enable I/D address translations. */ 1167 __asm volatile ("mfmsr %0" : "=r"(msr)); 1168 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1169 __asm volatile ("mtmsr %0" :: "r"(msr)); 1170 __asm volatile ("sync; isync"); 1171 1172 md_sync_timebase(h); 1173 1174 cpu_setup(h->self, ci); 1175 1176 h->running = 1; 1177 __asm volatile ("sync; isync"); 1178 1179 while (start_secondary_cpu == 0) 1180 ; 1181 1182 __asm volatile ("sync; isync"); 1183 1184 aprint_normal("cpu%d: started\n", cpu_number()); 1185 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1186 1187 md_setup_interrupts(); 1188 1189 ci->ci_ipending = 0; 1190 ci->ci_cpl = 0; 1191 1192 mtmsr(mfmsr() | PSL_EE); 1193 } 1194 1195 void 1196 cpu_boot_secondary_processors() 1197 { 1198 start_secondary_cpu = 1; 1199 __asm volatile ("sync"); 1200 } 1201 1202 #endif /*MULTIPROCESSOR*/ 1203
Indexes created Thu Oct 02 07:10:07 GMT 2025