cpu_subr.c revision 1.50.14.1
1 /* $NetBSD: cpu_subr.c,v 1.50.14.1 2011/01/07 02:12:19 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.50.14.1 2011/01/07 02:12:19 matt Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/types.h> 48 #include <sys/lwp.h> 49 #include <sys/user.h> 50 #include <sys/malloc.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <powerpc/oea/hid.h> 55 #include <powerpc/oea/hid_601.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/spr.h> 58 #include <powerpc/oea/cpufeat.h> 59 60 #include <dev/sysmon/sysmonvar.h> 61 62 static void cpu_enable_l2cr(register_t); 63 static void cpu_enable_l3cr(register_t); 64 static void cpu_config_l2cr(int); 65 static void cpu_config_l3cr(int); 66 static void cpu_probe_speed(struct cpu_info *); 67 static void cpu_idlespin(void); 68 #if NSYSMON_ENVSYS > 0 69 static void cpu_tau_setup(struct cpu_info *); 70 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 71 #endif 72 73 int cpu; 74 int ncpus; 75 76 struct fmttab { 77 register_t fmt_mask; 78 register_t fmt_value; 79 const char *fmt_string; 80 }; 81 82 /* 83 * This should be one per CPU but since we only support it on 750 variants it 84 * doesn't realy matter since none of them supports SMP 85 */ 86 envsys_data_t sensor; 87 88 static const struct fmttab cpu_7450_l2cr_formats[] = { 89 { L2CR_L2E, 0, " disabled" }, 90 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 93 { L2CR_L2E, ~0, " 256KB L2 cache" }, 94 { L2CR_L2PE, 0, " no parity" }, 95 { L2CR_L2PE, ~0, " parity enabled" }, 96 { 0, 0, NULL } 97 }; 98 99 static const struct fmttab cpu_7448_l2cr_formats[] = { 100 { L2CR_L2E, 0, " disabled" }, 101 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 102 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 103 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 104 { L2CR_L2E, ~0, " 1MB L2 cache" }, 105 { L2CR_L2PE, 0, " no parity" }, 106 { L2CR_L2PE, ~0, " parity enabled" }, 107 { 0, 0, NULL } 108 }; 109 110 static const struct fmttab cpu_7457_l2cr_formats[] = { 111 { L2CR_L2E, 0, " disabled" }, 112 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 113 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 114 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 115 { L2CR_L2E, ~0, " 512KB L2 cache" }, 116 { L2CR_L2PE, 0, " no parity" }, 117 { L2CR_L2PE, ~0, " parity enabled" }, 118 { 0, 0, NULL } 119 }; 120 121 static const struct fmttab cpu_7450_l3cr_formats[] = { 122 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 123 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 124 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 125 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 126 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 127 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 128 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 129 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 130 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 131 { L3CR_L3SIZ, ~0, " L3 cache" }, 132 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 133 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 134 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 135 { L3CR_L3CLK, ~0, " at" }, 136 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 137 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 138 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 139 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 140 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 141 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 142 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 143 { L3CR_L3CLK, ~0, " ratio" }, 144 { 0, 0, NULL }, 145 }; 146 147 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 148 { L2CR_L2E, 0, " disabled" }, 149 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 150 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 151 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 152 { 0, ~0, " 512KB" }, 153 { L2CR_L2WT, L2CR_L2WT, " WT" }, 154 { L2CR_L2WT, 0, " WB" }, 155 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 156 { 0, ~0, " L2 cache" }, 157 { 0, 0, NULL } 158 }; 159 160 static const struct fmttab cpu_l2cr_formats[] = { 161 { L2CR_L2E, 0, " disabled" }, 162 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 163 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 164 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 165 { L2CR_L2PE, L2CR_L2PE, " parity" }, 166 { L2CR_L2PE, 0, " no-parity" }, 167 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 168 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 169 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 170 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 171 { L2CR_L2WT, L2CR_L2WT, " WT" }, 172 { L2CR_L2WT, 0, " WB" }, 173 { L2CR_L2E, ~0, " L2 cache" }, 174 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 175 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 176 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 177 { L2CR_L2CLK, ~0, " at" }, 178 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 179 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 180 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 181 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 182 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 183 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 184 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 185 { L2CR_L2CLK, ~0, " ratio" }, 186 { 0, 0, NULL } 187 }; 188 189 static void cpu_fmttab_print(const struct fmttab *, register_t); 190 191 struct cputab { 192 const char name[8]; 193 uint16_t version; 194 uint16_t revfmt; 195 }; 196 #define REVFMT_MAJMIN 1 /* %u.%u */ 197 #define REVFMT_HEX 2 /* 0x%04x */ 198 #define REVFMT_DEC 3 /* %u */ 199 static const struct cputab models[] = { 200 { "601", MPC601, REVFMT_DEC }, 201 { "602", MPC602, REVFMT_DEC }, 202 { "603", MPC603, REVFMT_MAJMIN }, 203 { "603e", MPC603e, REVFMT_MAJMIN }, 204 { "603ev", MPC603ev, REVFMT_MAJMIN }, 205 { "G2", MPCG2, REVFMT_MAJMIN }, 206 { "604", MPC604, REVFMT_MAJMIN }, 207 { "604e", MPC604e, REVFMT_MAJMIN }, 208 { "604ev", MPC604ev, REVFMT_MAJMIN }, 209 { "620", MPC620, REVFMT_HEX }, 210 { "750", MPC750, REVFMT_MAJMIN }, 211 { "750FX", IBM750FX, REVFMT_MAJMIN }, 212 { "7400", MPC7400, REVFMT_MAJMIN }, 213 { "7410", MPC7410, REVFMT_MAJMIN }, 214 { "7450", MPC7450, REVFMT_MAJMIN }, 215 { "7455", MPC7455, REVFMT_MAJMIN }, 216 { "7457", MPC7457, REVFMT_MAJMIN }, 217 { "7447A", MPC7447A, REVFMT_MAJMIN }, 218 { "7448", MPC7448, REVFMT_MAJMIN }, 219 { "8240", MPC8240, REVFMT_MAJMIN }, 220 { "8245", MPC8245, REVFMT_MAJMIN }, 221 { "970", IBM970, REVFMT_MAJMIN }, 222 { "970FX", IBM970FX, REVFMT_MAJMIN }, 223 { "970MP", IBM970MP, REVFMT_MAJMIN }, 224 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 225 { "", 0, REVFMT_HEX } 226 }; 227 228 #ifdef MULTIPROCESSOR 229 struct cpu_info cpu_info[CPU_MAXNUM] = { { .ci_curlwp = &lwp0, }, }; 230 volatile struct cpu_hatch_data *cpu_hatch_data; 231 volatile int cpu_hatch_stack; 232 extern int ticks_per_intr; 233 #include <powerpc/oea/bat.h> 234 #include <arch/powerpc/pic/picvar.h> 235 #include <arch/powerpc/pic/ipivar.h> 236 extern struct bat battable[]; 237 #else 238 struct cpu_info cpu_info[1] = { { .ci_curlwp = &lwp0, }, }; 239 #endif /*MULTIPROCESSOR*/ 240 241 int cpu_altivec; 242 int cpu_psluserset, cpu_pslusermod; 243 char cpu_model[80]; 244 245 /* This is to be called from locore.S, and nowhere else. */ 246 247 void 248 cpu_model_init(void) 249 { 250 u_int pvr, vers; 251 252 pvr = mfpvr(); 253 vers = pvr >> 16; 254 255 oeacpufeat = 0; 256 257 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 258 vers == IBMCELL || vers == IBMPOWER6P5) 259 oeacpufeat |= OEACPU_64 | OEACPU_64_BRIDGE | OEACPU_NOBAT; 260 261 else if (vers == MPC601) 262 oeacpufeat |= OEACPU_601; 263 264 else if (MPC745X_P(vers) && vers != MPC7450) 265 oeacpufeat |= OEACPU_XBSEN | OEACPU_HIGHBAT | OEACPU_HIGHSPRG; 266 } 267 268 void 269 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 270 { 271 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 272 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 273 (data & fmt->fmt_mask) == fmt->fmt_value) 274 aprint_normal("%s", fmt->fmt_string); 275 } 276 } 277 278 void 279 cpu_idlespin(void) 280 { 281 register_t msr; 282 283 if (powersave <= 0) 284 return; 285 286 __asm volatile( 287 "sync;" 288 "mfmsr %0;" 289 "oris %0,%0,%1@h;" /* enter power saving mode */ 290 "mtmsr %0;" 291 "isync;" 292 : "=r"(msr) 293 : "J"(PSL_POW)); 294 } 295 296 void 297 cpu_probe_cache(void) 298 { 299 u_int assoc, pvr, vers; 300 301 pvr = mfpvr(); 302 vers = pvr >> 16; 303 304 305 /* Presently common across almost all implementations. */ 306 curcpu()->ci_ci.dcache_line_size = 32; 307 curcpu()->ci_ci.icache_line_size = 32; 308 309 310 switch (vers) { 311 #define K *1024 312 case IBM750FX: 313 case MPC601: 314 case MPC750: 315 case MPC7400: 316 case MPC7447A: 317 case MPC7448: 318 case MPC7450: 319 case MPC7455: 320 case MPC7457: 321 curcpu()->ci_ci.dcache_size = 32 K; 322 curcpu()->ci_ci.icache_size = 32 K; 323 assoc = 8; 324 break; 325 case MPC603: 326 curcpu()->ci_ci.dcache_size = 8 K; 327 curcpu()->ci_ci.icache_size = 8 K; 328 assoc = 2; 329 break; 330 case MPC603e: 331 case MPC603ev: 332 case MPC604: 333 case MPC8240: 334 case MPC8245: 335 case MPCG2: 336 curcpu()->ci_ci.dcache_size = 16 K; 337 curcpu()->ci_ci.icache_size = 16 K; 338 assoc = 4; 339 break; 340 case MPC604e: 341 case MPC604ev: 342 curcpu()->ci_ci.dcache_size = 32 K; 343 curcpu()->ci_ci.icache_size = 32 K; 344 assoc = 4; 345 break; 346 case IBMPOWER3II: 347 curcpu()->ci_ci.dcache_size = 64 K; 348 curcpu()->ci_ci.icache_size = 32 K; 349 curcpu()->ci_ci.dcache_line_size = 128; 350 curcpu()->ci_ci.icache_line_size = 128; 351 assoc = 128; /* not a typo */ 352 break; 353 case IBM970: 354 case IBM970FX: 355 case IBM970MP: 356 curcpu()->ci_ci.dcache_size = 32 K; 357 curcpu()->ci_ci.icache_size = 64 K; 358 curcpu()->ci_ci.dcache_line_size = 128; 359 curcpu()->ci_ci.icache_line_size = 128; 360 assoc = 2; 361 break; 362 363 default: 364 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 365 curcpu()->ci_ci.icache_size = PAGE_SIZE; 366 assoc = 1; 367 #undef K 368 } 369 370 /* 371 * Possibly recolor. 372 */ 373 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 374 } 375 376 struct cpu_info * 377 cpu_attach_common(struct device *self, int id) 378 { 379 struct cpu_info *ci; 380 u_int pvr, vers; 381 382 ci = &cpu_info[id]; 383 #ifndef MULTIPROCESSOR 384 /* 385 * If this isn't the primary CPU, print an error message 386 * and just bail out. 387 */ 388 if (id != 0) { 389 aprint_normal(": ID %d\n", id); 390 aprint_normal("%s: processor off-line; multiprocessor support " 391 "not present in kernel\n", self->dv_xname); 392 return (NULL); 393 } 394 #endif 395 396 ci->ci_cpuid = id; 397 ci->ci_idepth = -1; 398 ci->ci_dev = self; 399 ci->ci_idlespin = cpu_idlespin; 400 401 pvr = mfpvr(); 402 vers = (pvr >> 16) & 0xffff; 403 404 switch (id) { 405 case 0: 406 /* load my cpu_number to PIR */ 407 switch (vers) { 408 case MPC601: 409 case MPC604: 410 case MPC604e: 411 case MPC604ev: 412 case MPC7400: 413 case MPC7410: 414 case MPC7447A: 415 case MPC7448: 416 case MPC7450: 417 case MPC7455: 418 case MPC7457: 419 mtspr(SPR_PIR, id); 420 } 421 cpu_setup(self, ci); 422 break; 423 default: 424 if (id >= CPU_MAXNUM) { 425 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 426 panic("cpuattach"); 427 } 428 #ifndef MULTIPROCESSOR 429 aprint_normal(" not configured\n"); 430 return NULL; 431 #else 432 mi_cpu_attach(ci); 433 break; 434 #endif 435 } 436 return (ci); 437 } 438 439 void 440 cpu_setup(self, ci) 441 struct device *self; 442 struct cpu_info *ci; 443 { 444 u_int hid0, hid0_save, pvr, vers; 445 const char *bitmask; 446 char hidbuf[128]; 447 char model[80]; 448 449 pvr = mfpvr(); 450 vers = (pvr >> 16) & 0xffff; 451 452 cpu_identify(model, sizeof(model)); 453 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 454 cpu_number() == 0 ? " (primary)" : ""); 455 456 /* set the cpu number */ 457 ci->ci_cpuid = cpu_number(); 458 hid0_save = hid0 = mfspr(SPR_HID0); 459 460 cpu_probe_cache(); 461 462 /* 463 * Configure power-saving mode. 464 */ 465 switch (vers) { 466 case MPC604: 467 case MPC604e: 468 case MPC604ev: 469 /* 470 * Do not have HID0 support settings, but can support 471 * MSR[POW] off 472 */ 473 powersave = 1; 474 break; 475 476 case MPC603: 477 case MPC603e: 478 case MPC603ev: 479 case MPC750: 480 case IBM750FX: 481 case MPC7400: 482 case MPC7410: 483 case MPC8240: 484 case MPC8245: 485 case MPCG2: 486 /* Select DOZE mode. */ 487 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 488 hid0 |= HID0_DOZE | HID0_DPM; 489 powersave = 1; 490 break; 491 492 case MPC7447A: 493 case MPC7448: 494 case MPC7457: 495 case MPC7455: 496 case MPC7450: 497 /* Enable the 7450 branch caches */ 498 hid0 |= HID0_SGE | HID0_BTIC; 499 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 500 /* Enable more and larger BAT registers */ 501 if (oeacpufeat & OEACPU_XBSEN) 502 hid0 |= HID0_XBSEN; 503 if (oeacpufeat & OEACPU_HIGHBAT) 504 hid0 |= HID0_HIGH_BAT_EN; 505 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 506 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 507 hid0 &= ~HID0_BTIC; 508 /* Select NAP mode. */ 509 hid0 &= ~HID0_SLEEP; 510 hid0 |= HID0_NAP | HID0_DPM; 511 // powersave = 1; 512 break; 513 514 case IBM970: 515 case IBM970FX: 516 case IBM970MP: 517 case IBMPOWER3II: 518 default: 519 /* No power-saving mode is available. */ ; 520 } 521 522 #ifdef NAPMODE 523 switch (vers) { 524 case IBM750FX: 525 case MPC750: 526 case MPC7400: 527 /* Select NAP mode. */ 528 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 529 hid0 |= HID0_NAP; 530 break; 531 } 532 #endif 533 534 switch (vers) { 535 case IBM750FX: 536 case MPC750: 537 hid0 &= ~HID0_DBP; /* XXX correct? */ 538 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 539 break; 540 541 case MPC7400: 542 case MPC7410: 543 hid0 &= ~HID0_SPD; 544 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 545 hid0 |= HID0_EIEC; 546 break; 547 } 548 549 if (hid0 != hid0_save) { 550 mtspr(SPR_HID0, hid0); 551 __asm volatile("sync;isync"); 552 } 553 554 555 switch (vers) { 556 case MPC601: 557 bitmask = HID0_601_BITMASK; 558 break; 559 case MPC7450: 560 case MPC7455: 561 case MPC7457: 562 bitmask = HID0_7450_BITMASK; 563 break; 564 case IBM970: 565 case IBM970FX: 566 case IBM970MP: 567 bitmask = 0; 568 break; 569 default: 570 bitmask = HID0_BITMASK; 571 break; 572 } 573 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 574 aprint_normal("%s: HID0 %s, powersave: %d\n", self->dv_xname, hidbuf, 575 powersave); 576 577 ci->ci_khz = 0; 578 579 /* 580 * Display speed and cache configuration. 581 */ 582 switch (vers) { 583 case MPC604: 584 case MPC604e: 585 case MPC604ev: 586 case MPC750: 587 case IBM750FX: 588 case MPC7400: 589 case MPC7410: 590 case MPC7447A: 591 case MPC7448: 592 case MPC7450: 593 case MPC7455: 594 case MPC7457: 595 aprint_normal("%s: ", self->dv_xname); 596 cpu_probe_speed(ci); 597 aprint_normal("%u.%02u MHz", 598 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 599 switch (vers) { 600 case MPC7450: /* 7441 does not have L3! */ 601 case MPC7455: /* 7445 does not have L3! */ 602 case MPC7457: /* 7447 does not have L3! */ 603 cpu_config_l3cr(vers); 604 break; 605 case IBM750FX: 606 case MPC750: 607 case MPC7400: 608 case MPC7410: 609 case MPC7447A: 610 case MPC7448: 611 cpu_config_l2cr(pvr); 612 break; 613 default: 614 break; 615 } 616 aprint_normal("\n"); 617 break; 618 } 619 620 #if NSYSMON_ENVSYS > 0 621 /* 622 * Attach MPC750 temperature sensor to the envsys subsystem. 623 * XXX the 74xx series also has this sensor, but it is not 624 * XXX supported by Motorola and may return values that are off by 625 * XXX 35-55 degrees C. 626 */ 627 if (vers == MPC750 || vers == IBM750FX) 628 cpu_tau_setup(ci); 629 #endif 630 631 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 632 NULL, self->dv_xname, "clock"); 633 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 634 NULL, self->dv_xname, "soft clock"); 635 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 636 NULL, self->dv_xname, "soft net"); 637 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 638 NULL, self->dv_xname, "soft serial"); 639 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 640 NULL, self->dv_xname, "traps"); 641 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 642 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 643 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 644 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 645 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 646 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 647 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 648 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 649 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 650 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 651 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 652 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 653 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 654 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 655 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 656 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 657 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 658 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 659 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 660 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 661 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 662 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 663 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 664 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 665 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 666 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 667 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 668 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 669 #ifdef ALTIVEC 670 if (cpu_altivec) { 671 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 672 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 673 } 674 #endif 675 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 676 NULL, self->dv_xname, "IPIs"); 677 } 678 679 /* 680 * According to a document labeled "PVR Register Settings": 681 ** For integrated microprocessors the PVR register inside the device 682 ** will identify the version of the microprocessor core. You must also 683 ** read the Device ID, PCI register 02, to identify the part and the 684 ** Revision ID, PCI register 08, to identify the revision of the 685 ** integrated microprocessor. 686 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 687 */ 688 689 void 690 cpu_identify(char *str, size_t len) 691 { 692 u_int pvr, major, minor; 693 uint16_t vers, rev, revfmt; 694 const struct cputab *cp; 695 const char *name; 696 size_t n; 697 698 pvr = mfpvr(); 699 vers = pvr >> 16; 700 rev = pvr; 701 702 switch (vers) { 703 case MPC7410: 704 minor = (pvr >> 0) & 0xff; 705 major = minor <= 4 ? 1 : 2; 706 break; 707 case MPCG2: /*XXX see note above */ 708 major = (pvr >> 4) & 0xf; 709 minor = (pvr >> 0) & 0xf; 710 break; 711 default: 712 major = (pvr >> 8) & 0xf; 713 minor = (pvr >> 0) & 0xf; 714 } 715 716 for (cp = models; cp->name[0] != '\0'; cp++) { 717 if (cp->version == vers) 718 break; 719 } 720 721 if (str == NULL) { 722 str = cpu_model; 723 len = sizeof(cpu_model); 724 cpu = vers; 725 } 726 727 revfmt = cp->revfmt; 728 name = cp->name; 729 if (rev == MPC750 && pvr == 15) { 730 name = "755"; 731 revfmt = REVFMT_HEX; 732 } 733 734 if (cp->name[0] != '\0') { 735 n = snprintf(str, len, "%s (Revision ", cp->name); 736 } else { 737 n = snprintf(str, len, "Version %#x (Revision ", vers); 738 } 739 if (len > n) { 740 switch (revfmt) { 741 case REVFMT_MAJMIN: 742 snprintf(str + n, len - n, "%u.%u)", major, minor); 743 break; 744 case REVFMT_HEX: 745 snprintf(str + n, len - n, "0x%04x)", rev); 746 break; 747 case REVFMT_DEC: 748 snprintf(str + n, len - n, "%u)", rev); 749 break; 750 } 751 } 752 } 753 754 #ifdef L2CR_CONFIG 755 u_int l2cr_config = L2CR_CONFIG; 756 #else 757 u_int l2cr_config = 0; 758 #endif 759 760 #ifdef L3CR_CONFIG 761 u_int l3cr_config = L3CR_CONFIG; 762 #else 763 u_int l3cr_config = 0; 764 #endif 765 766 void 767 cpu_enable_l2cr(register_t l2cr) 768 { 769 register_t msr, x; 770 uint16_t vers; 771 772 vers = mfpvr() >> 16; 773 774 /* Disable interrupts and set the cache config bits. */ 775 msr = mfmsr(); 776 mtmsr(msr & ~PSL_EE); 777 #ifdef ALTIVEC 778 if (cpu_altivec) 779 __asm volatile("dssall"); 780 #endif 781 __asm volatile("sync"); 782 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 783 __asm volatile("sync"); 784 785 /* Wait for L2 clock to be stable (640 L2 clocks). */ 786 delay(100); 787 788 /* Invalidate all L2 contents. */ 789 if (MPC745X_P(vers)) { 790 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 791 do { 792 x = mfspr(SPR_L2CR); 793 } while (x & L2CR_L2I); 794 } else { 795 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 796 do { 797 x = mfspr(SPR_L2CR); 798 } while (x & L2CR_L2IP); 799 } 800 /* Enable L2 cache. */ 801 l2cr |= L2CR_L2E; 802 mtspr(SPR_L2CR, l2cr); 803 mtmsr(msr); 804 } 805 806 void 807 cpu_enable_l3cr(register_t l3cr) 808 { 809 register_t x; 810 811 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 812 813 /* 814 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 815 * L3CLKEN. (also mask off reserved bits in case they were included 816 * in L3CR_CONFIG) 817 */ 818 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 819 mtspr(SPR_L3CR, l3cr); 820 821 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 822 l3cr |= 0x04000000; 823 mtspr(SPR_L3CR, l3cr); 824 825 /* 3: Set L3CLKEN to 1*/ 826 l3cr |= L3CR_L3CLKEN; 827 mtspr(SPR_L3CR, l3cr); 828 829 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 830 __asm volatile("dssall;sync"); 831 /* L3 cache is already disabled, no need to clear L3E */ 832 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 833 do { 834 x = mfspr(SPR_L3CR); 835 } while (x & L3CR_L3I); 836 837 /* 6: Clear L3CLKEN to 0 */ 838 l3cr &= ~L3CR_L3CLKEN; 839 mtspr(SPR_L3CR, l3cr); 840 841 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 842 __asm volatile("sync"); 843 delay(100); 844 845 /* 8: Set L3E and L3CLKEN */ 846 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 847 mtspr(SPR_L3CR, l3cr); 848 849 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 850 __asm volatile("sync"); 851 delay(100); 852 } 853 854 void 855 cpu_config_l2cr(int pvr) 856 { 857 register_t l2cr; 858 u_int vers = (pvr >> 16) & 0xffff; 859 860 l2cr = mfspr(SPR_L2CR); 861 862 /* 863 * For MP systems, the firmware may only configure the L2 cache 864 * on the first CPU. In this case, assume that the other CPUs 865 * should use the same value for L2CR. 866 */ 867 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 868 l2cr_config = l2cr; 869 } 870 871 /* 872 * Configure L2 cache if not enabled. 873 */ 874 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 875 cpu_enable_l2cr(l2cr_config); 876 l2cr = mfspr(SPR_L2CR); 877 } 878 879 if ((l2cr & L2CR_L2E) == 0) { 880 aprint_normal(" L2 cache present but not enabled "); 881 return; 882 } 883 aprint_normal(","); 884 885 switch (vers) { 886 case IBM750FX: 887 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 888 break; 889 case MPC750: 890 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 891 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 892 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 893 else 894 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 895 break; 896 case MPC7447A: 897 case MPC7457: 898 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 899 return; 900 case MPC7448: 901 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 902 return; 903 case MPC7450: 904 case MPC7455: 905 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 906 break; 907 default: 908 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 909 break; 910 } 911 } 912 913 void 914 cpu_config_l3cr(int vers) 915 { 916 register_t l2cr; 917 register_t l3cr; 918 919 l2cr = mfspr(SPR_L2CR); 920 921 /* 922 * For MP systems, the firmware may only configure the L2 cache 923 * on the first CPU. In this case, assume that the other CPUs 924 * should use the same value for L2CR. 925 */ 926 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 927 l2cr_config = l2cr; 928 } 929 930 /* 931 * Configure L2 cache if not enabled. 932 */ 933 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 934 cpu_enable_l2cr(l2cr_config); 935 l2cr = mfspr(SPR_L2CR); 936 } 937 938 aprint_normal(","); 939 switch (vers) { 940 case MPC7447A: 941 case MPC7457: 942 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 943 return; 944 case MPC7448: 945 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 946 return; 947 default: 948 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 949 break; 950 } 951 952 l3cr = mfspr(SPR_L3CR); 953 954 /* 955 * For MP systems, the firmware may only configure the L3 cache 956 * on the first CPU. In this case, assume that the other CPUs 957 * should use the same value for L3CR. 958 */ 959 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 960 l3cr_config = l3cr; 961 } 962 963 /* 964 * Configure L3 cache if not enabled. 965 */ 966 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 967 cpu_enable_l3cr(l3cr_config); 968 l3cr = mfspr(SPR_L3CR); 969 } 970 971 if (l3cr & L3CR_L3E) { 972 aprint_normal(","); 973 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 974 } 975 } 976 977 void 978 cpu_probe_speed(struct cpu_info *ci) 979 { 980 uint64_t cps; 981 982 mtspr(SPR_MMCR0, MMCR0_FC); 983 mtspr(SPR_PMC1, 0); 984 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 985 delay(100000); 986 cps = (mfspr(SPR_PMC1) * 10) + 4999; 987 988 mtspr(SPR_MMCR0, MMCR0_FC); 989 990 ci->ci_khz = cps / 1000; 991 } 992 993 #if NSYSMON_ENVSYS > 0 994 void 995 cpu_tau_setup(struct cpu_info *ci) 996 { 997 struct sysmon_envsys *sme; 998 int error, therm_delay; 999 1000 mtspr(SPR_THRM1, SPR_THRM_VALID); 1001 mtspr(SPR_THRM2, 0); 1002 1003 /* 1004 * we need to figure out how much 20+us in units of CPU clock cycles 1005 * are 1006 */ 1007 1008 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1009 1010 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1011 1012 sme = sysmon_envsys_create(); 1013 1014 sensor.units = ENVSYS_STEMP; 1015 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1016 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1017 sysmon_envsys_destroy(sme); 1018 return; 1019 } 1020 1021 sme->sme_name = ci->ci_dev->dv_xname; 1022 sme->sme_cookie = ci; 1023 sme->sme_refresh = cpu_tau_refresh; 1024 1025 if ((error = sysmon_envsys_register(sme)) != 0) { 1026 aprint_error("%s: unable to register with sysmon (%d)\n", 1027 ci->ci_dev->dv_xname, error); 1028 sysmon_envsys_destroy(sme); 1029 } 1030 } 1031 1032 1033 /* Find the temperature of the CPU. */ 1034 void 1035 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1036 { 1037 int i, threshold, count; 1038 1039 threshold = 64; /* Half of the 7-bit sensor range */ 1040 1041 /* Successive-approximation code adapted from Motorola 1042 * application note AN1800/D, "Programming the Thermal Assist 1043 * Unit in the MPC750 Microprocessor". 1044 */ 1045 for (i = 5; i >= 0 ; i--) { 1046 mtspr(SPR_THRM1, 1047 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1048 count = 0; 1049 while ((count < 100000) && 1050 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1051 count++; 1052 delay(1); 1053 } 1054 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1055 /* The interrupt bit was set, meaning the 1056 * temperature was above the threshold 1057 */ 1058 threshold += 1 << i; 1059 } else { 1060 /* Temperature was below the threshold */ 1061 threshold -= 1 << i; 1062 } 1063 1064 } 1065 threshold += 2; 1066 1067 /* Convert the temperature in degrees C to microkelvin */ 1068 edata->value_cur = (threshold * 1000000) + 273150000; 1069 edata->state = ENVSYS_SVALID; 1070 } 1071 #endif /* NSYSMON_ENVSYS > 0 */ 1072 1073 #ifdef MULTIPROCESSOR 1074 extern volatile u_int cpu_spinstart_ack; 1075 1076 int 1077 cpu_spinup(struct device *self, struct cpu_info *ci) 1078 { 1079 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1080 struct pglist mlist; 1081 int i, error, pvr, vers; 1082 char *cp, *hp; 1083 1084 pvr = mfpvr(); 1085 vers = pvr >> 16; 1086 KASSERT(ci != curcpu()); 1087 1088 /* 1089 * Allocate some contiguous pages for the intteup PCB and stack 1090 * from the lowest 256MB (because bat0 always maps it va == pa). 1091 * Must be 16 byte aligned. 1092 */ 1093 error = uvm_pglistalloc(INTSTK, 0x10000, 0x10000000, 16, 0, 1094 &mlist, 1, 1); 1095 if (error) { 1096 aprint_error(": unable to allocate idle stack\n"); 1097 return -1; 1098 } 1099 1100 KASSERT(ci != &cpu_info[0]); 1101 1102 cp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1103 memset(cp, 0, INTSTK); 1104 1105 ci->ci_intstk = cp; 1106 1107 /* Now allocate a hatch stack */ 1108 error = uvm_pglistalloc(0x1000, 0x10000, 0x10000000, 16, 0, 1109 &mlist, 1, 1); 1110 if (error) { 1111 aprint_error(": unable to allocate hatch stack\n"); 1112 return -1; 1113 } 1114 1115 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1116 memset(hp, 0, 0x1000); 1117 1118 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1119 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1120 ci->ci_curpcb = &ci->ci_curlwp->l_addr->u_pcb; 1121 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1122 1123 cpu_hatch_data = h; 1124 h->running = 0; 1125 h->self = self; 1126 h->ci = ci; 1127 h->pir = ci->ci_cpuid; 1128 1129 cpu_hatch_stack = (uint32_t)hp; 1130 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1131 1132 /* copy special registers */ 1133 1134 h->hid0 = mfspr(SPR_HID0); 1135 1136 __asm volatile ("mfsdr1 %0" : "=r"(h->sdr1)); 1137 for (i = 0; i < 16; i++) { 1138 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1139 "r"(i << ADDR_SR_SHFT)); 1140 } 1141 if (oeacpufeat & OEACPU_64) 1142 h->asr = mfspr(SPR_ASR); 1143 else 1144 h->asr = 0; 1145 1146 /* copy the bat regs */ 1147 __asm volatile ("mfibatu %0,0" : "=r"(h->batu[0])); 1148 __asm volatile ("mfibatl %0,0" : "=r"(h->batl[0])); 1149 __asm volatile ("mfibatu %0,1" : "=r"(h->batu[1])); 1150 __asm volatile ("mfibatl %0,1" : "=r"(h->batl[1])); 1151 __asm volatile ("mfibatu %0,2" : "=r"(h->batu[2])); 1152 __asm volatile ("mfibatl %0,2" : "=r"(h->batl[2])); 1153 __asm volatile ("mfibatu %0,3" : "=r"(h->batu[3])); 1154 __asm volatile ("mfibatl %0,3" : "=r"(h->batl[3])); 1155 __asm volatile ("sync; isync"); 1156 1157 if (md_setup_trampoline(h, ci) == -1) 1158 return -1; 1159 md_presync_timebase(h); 1160 md_start_timebase(h); 1161 1162 /* wait for secondary printf */ 1163 1164 delay(200000); 1165 1166 if (h->running < 1) { 1167 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1168 ci->ci_cpuid, cpu_spinstart_ack); 1169 Debugger(); 1170 return -1; 1171 } 1172 1173 /* Register IPI Interrupt */ 1174 if (ipiops.ppc_establish_ipi) 1175 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1176 1177 return 0; 1178 } 1179 1180 static volatile int start_secondary_cpu; 1181 extern void tlbia(void); 1182 1183 register_t 1184 cpu_hatch(void) 1185 { 1186 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1187 struct cpu_info * const ci = h->ci; 1188 u_int msr; 1189 int i; 1190 1191 /* Initialize timebase. */ 1192 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1193 1194 /* 1195 * Set PIR (Processor Identification Register). i.e. whoami 1196 * Note that PIR is read-only on some CPU versions, so we write to it 1197 * only if it has a different value than we need. 1198 */ 1199 1200 msr = mfspr(SPR_PIR); 1201 if (msr != h->pir) 1202 mtspr(SPR_PIR, h->pir); 1203 1204 __asm volatile ("mtsprg 0,%0" :: "r"(ci)); 1205 cpu_spinstart_ack = 0; 1206 1207 /* Initialize MMU. */ 1208 __asm ("mtibatu 0,%0" :: "r"(h->batu[0])); 1209 __asm ("mtibatl 0,%0" :: "r"(h->batl[0])); 1210 __asm ("mtibatu 1,%0" :: "r"(h->batu[1])); 1211 __asm ("mtibatl 1,%0" :: "r"(h->batl[1])); 1212 __asm ("mtibatu 2,%0" :: "r"(h->batu[2])); 1213 __asm ("mtibatl 2,%0" :: "r"(h->batl[2])); 1214 __asm ("mtibatu 3,%0" :: "r"(h->batu[3])); 1215 __asm ("mtibatl 3,%0" :: "r"(h->batl[3])); 1216 1217 mtspr(SPR_HID0, h->hid0); 1218 1219 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1220 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1221 1222 __asm volatile ("sync"); 1223 for (i = 0; i < 16; i++) 1224 __asm ("mtsrin %0,%1" :: "r"(h->sr[i]), "r"(i << ADDR_SR_SHFT)); 1225 __asm volatile ("sync; isync"); 1226 1227 if (oeacpufeat & OEACPU_64) 1228 mtspr(SPR_ASR, h->asr); 1229 1230 cpu_spinstart_ack = 1; 1231 __asm ("ptesync"); 1232 __asm ("mtsdr1 %0" :: "r"(h->sdr1)); 1233 __asm volatile ("sync; isync"); 1234 1235 cpu_spinstart_ack = 5; 1236 for (i = 0; i < 16; i++) 1237 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1238 "r"(i << ADDR_SR_SHFT)); 1239 1240 /* Enable I/D address translations. */ 1241 msr = mfmsr(); 1242 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1243 mtmsr(msr); 1244 __asm volatile ("sync; isync"); 1245 cpu_spinstart_ack = 2; 1246 1247 md_sync_timebase(h); 1248 1249 cpu_setup(h->self, ci); 1250 1251 h->running = 1; 1252 __asm volatile ("sync; isync"); 1253 1254 while (start_secondary_cpu == 0) 1255 ; 1256 1257 __asm volatile ("sync; isync"); 1258 1259 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1260 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1261 1262 md_setup_interrupts(); 1263 1264 ci->ci_ipending = 0; 1265 ci->ci_cpl = 0; 1266 1267 mtmsr(mfmsr() | PSL_EE); 1268 return ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp; 1269 } 1270 1271 void 1272 cpu_boot_secondary_processors() 1273 { 1274 start_secondary_cpu = 1; 1275 __asm volatile ("sync"); 1276 } 1277 1278 #endif /*MULTIPROCESSOR*/ 1279
Indexes created Thu Oct 02 07:10:07 GMT 2025