cpu_subr.c revision 1.50.14.2
1 /* $NetBSD: cpu_subr.c,v 1.50.14.2 2011/01/17 07:45:59 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.50.14.2 2011/01/17 07:45:59 matt Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/types.h> 48 #include <sys/lwp.h> 49 #include <sys/user.h> 50 #include <sys/malloc.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <powerpc/oea/hid.h> 55 #include <powerpc/oea/hid_601.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/spr.h> 58 #include <powerpc/oea/cpufeat.h> 59 60 #include <dev/sysmon/sysmonvar.h> 61 62 static void cpu_enable_l2cr(register_t); 63 static void cpu_enable_l3cr(register_t); 64 static void cpu_config_l2cr(int); 65 static void cpu_config_l3cr(int); 66 static void cpu_probe_speed(struct cpu_info *); 67 static void cpu_idlespin(void); 68 #if NSYSMON_ENVSYS > 0 69 static void cpu_tau_setup(struct cpu_info *); 70 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 71 #endif 72 73 int cpu; 74 int ncpus; 75 76 struct fmttab { 77 register_t fmt_mask; 78 register_t fmt_value; 79 const char *fmt_string; 80 }; 81 82 /* 83 * This should be one per CPU but since we only support it on 750 variants it 84 * doesn't realy matter since none of them supports SMP 85 */ 86 envsys_data_t sensor; 87 88 static const struct fmttab cpu_7450_l2cr_formats[] = { 89 { L2CR_L2E, 0, " disabled" }, 90 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 93 { L2CR_L2E, ~0, " 256KB L2 cache" }, 94 { L2CR_L2PE, 0, " no parity" }, 95 { L2CR_L2PE, ~0, " parity enabled" }, 96 { 0, 0, NULL } 97 }; 98 99 static const struct fmttab cpu_7448_l2cr_formats[] = { 100 { L2CR_L2E, 0, " disabled" }, 101 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 102 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 103 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 104 { L2CR_L2E, ~0, " 1MB L2 cache" }, 105 { L2CR_L2PE, 0, " no parity" }, 106 { L2CR_L2PE, ~0, " parity enabled" }, 107 { 0, 0, NULL } 108 }; 109 110 static const struct fmttab cpu_7457_l2cr_formats[] = { 111 { L2CR_L2E, 0, " disabled" }, 112 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 113 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 114 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 115 { L2CR_L2E, ~0, " 512KB L2 cache" }, 116 { L2CR_L2PE, 0, " no parity" }, 117 { L2CR_L2PE, ~0, " parity enabled" }, 118 { 0, 0, NULL } 119 }; 120 121 static const struct fmttab cpu_7450_l3cr_formats[] = { 122 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 123 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 124 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 125 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 126 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 127 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 128 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 129 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 130 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 131 { L3CR_L3SIZ, ~0, " L3 cache" }, 132 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 133 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 134 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 135 { L3CR_L3CLK, ~0, " at" }, 136 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 137 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 138 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 139 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 140 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 141 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 142 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 143 { L3CR_L3CLK, ~0, " ratio" }, 144 { 0, 0, NULL }, 145 }; 146 147 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 148 { L2CR_L2E, 0, " disabled" }, 149 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 150 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 151 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 152 { 0, ~0, " 512KB" }, 153 { L2CR_L2WT, L2CR_L2WT, " WT" }, 154 { L2CR_L2WT, 0, " WB" }, 155 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 156 { 0, ~0, " L2 cache" }, 157 { 0, 0, NULL } 158 }; 159 160 static const struct fmttab cpu_l2cr_formats[] = { 161 { L2CR_L2E, 0, " disabled" }, 162 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 163 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 164 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 165 { L2CR_L2PE, L2CR_L2PE, " parity" }, 166 { L2CR_L2PE, 0, " no-parity" }, 167 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 168 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 169 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 170 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 171 { L2CR_L2WT, L2CR_L2WT, " WT" }, 172 { L2CR_L2WT, 0, " WB" }, 173 { L2CR_L2E, ~0, " L2 cache" }, 174 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 175 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 176 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 177 { L2CR_L2CLK, ~0, " at" }, 178 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 179 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 180 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 181 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 182 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 183 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 184 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 185 { L2CR_L2CLK, ~0, " ratio" }, 186 { 0, 0, NULL } 187 }; 188 189 static void cpu_fmttab_print(const struct fmttab *, register_t); 190 191 struct cputab { 192 const char name[8]; 193 uint16_t version; 194 uint16_t revfmt; 195 }; 196 #define REVFMT_MAJMIN 1 /* %u.%u */ 197 #define REVFMT_HEX 2 /* 0x%04x */ 198 #define REVFMT_DEC 3 /* %u */ 199 static const struct cputab models[] = { 200 { "601", MPC601, REVFMT_DEC }, 201 { "602", MPC602, REVFMT_DEC }, 202 { "603", MPC603, REVFMT_MAJMIN }, 203 { "603e", MPC603e, REVFMT_MAJMIN }, 204 { "603ev", MPC603ev, REVFMT_MAJMIN }, 205 { "G2", MPCG2, REVFMT_MAJMIN }, 206 { "604", MPC604, REVFMT_MAJMIN }, 207 { "604e", MPC604e, REVFMT_MAJMIN }, 208 { "604ev", MPC604ev, REVFMT_MAJMIN }, 209 { "620", MPC620, REVFMT_HEX }, 210 { "750", MPC750, REVFMT_MAJMIN }, 211 { "750FX", IBM750FX, REVFMT_MAJMIN }, 212 { "7400", MPC7400, REVFMT_MAJMIN }, 213 { "7410", MPC7410, REVFMT_MAJMIN }, 214 { "7450", MPC7450, REVFMT_MAJMIN }, 215 { "7455", MPC7455, REVFMT_MAJMIN }, 216 { "7457", MPC7457, REVFMT_MAJMIN }, 217 { "7447A", MPC7447A, REVFMT_MAJMIN }, 218 { "7448", MPC7448, REVFMT_MAJMIN }, 219 { "8240", MPC8240, REVFMT_MAJMIN }, 220 { "8245", MPC8245, REVFMT_MAJMIN }, 221 { "970", IBM970, REVFMT_MAJMIN }, 222 { "970FX", IBM970FX, REVFMT_MAJMIN }, 223 { "970MP", IBM970MP, REVFMT_MAJMIN }, 224 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 225 { "", 0, REVFMT_HEX } 226 }; 227 228 #ifdef MULTIPROCESSOR 229 struct cpu_info cpu_info[CPU_MAXNUM] = { 230 [0] = { 231 .ci_curlwp = &lwp0, 232 .ci_fpulwp = &lwp0, 233 .ci_veclwp = &lwp0, 234 }, 235 }; 236 volatile struct cpu_hatch_data *cpu_hatch_data; 237 volatile int cpu_hatch_stack; 238 extern int ticks_per_intr; 239 #include <powerpc/oea/bat.h> 240 #include <arch/powerpc/pic/picvar.h> 241 #include <arch/powerpc/pic/ipivar.h> 242 extern struct bat battable[]; 243 #else 244 struct cpu_info cpu_info[1] = { 245 [0] = { 246 .ci_curlwp = &lwp0, 247 .ci_fpulwp = &lwp0, 248 .ci_veclwp = &lwp0, 249 }, 250 }; 251 #endif /*MULTIPROCESSOR*/ 252 253 int cpu_altivec; 254 int cpu_psluserset, cpu_pslusermod; 255 char cpu_model[80]; 256 257 /* This is to be called from locore.S, and nowhere else. */ 258 259 void 260 cpu_model_init(void) 261 { 262 u_int pvr, vers; 263 264 pvr = mfpvr(); 265 vers = pvr >> 16; 266 267 oeacpufeat = 0; 268 269 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 270 vers == IBMCELL || vers == IBMPOWER6P5) 271 oeacpufeat |= OEACPU_64 | OEACPU_64_BRIDGE | OEACPU_NOBAT; 272 273 else if (vers == MPC601) 274 oeacpufeat |= OEACPU_601; 275 276 else if (MPC745X_P(vers) && vers != MPC7450) 277 oeacpufeat |= OEACPU_XBSEN | OEACPU_HIGHBAT | OEACPU_HIGHSPRG; 278 } 279 280 void 281 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 282 { 283 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 284 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 285 (data & fmt->fmt_mask) == fmt->fmt_value) 286 aprint_normal("%s", fmt->fmt_string); 287 } 288 } 289 290 void 291 cpu_idlespin(void) 292 { 293 register_t msr; 294 295 if (powersave <= 0) 296 return; 297 298 __asm volatile( 299 "sync;" 300 "mfmsr %0;" 301 "oris %0,%0,%1@h;" /* enter power saving mode */ 302 "mtmsr %0;" 303 "isync;" 304 : "=r"(msr) 305 : "J"(PSL_POW)); 306 } 307 308 void 309 cpu_probe_cache(void) 310 { 311 u_int assoc, pvr, vers; 312 313 pvr = mfpvr(); 314 vers = pvr >> 16; 315 316 317 /* Presently common across almost all implementations. */ 318 curcpu()->ci_ci.dcache_line_size = 32; 319 curcpu()->ci_ci.icache_line_size = 32; 320 321 322 switch (vers) { 323 #define K *1024 324 case IBM750FX: 325 case MPC601: 326 case MPC750: 327 case MPC7400: 328 case MPC7447A: 329 case MPC7448: 330 case MPC7450: 331 case MPC7455: 332 case MPC7457: 333 curcpu()->ci_ci.dcache_size = 32 K; 334 curcpu()->ci_ci.icache_size = 32 K; 335 assoc = 8; 336 break; 337 case MPC603: 338 curcpu()->ci_ci.dcache_size = 8 K; 339 curcpu()->ci_ci.icache_size = 8 K; 340 assoc = 2; 341 break; 342 case MPC603e: 343 case MPC603ev: 344 case MPC604: 345 case MPC8240: 346 case MPC8245: 347 case MPCG2: 348 curcpu()->ci_ci.dcache_size = 16 K; 349 curcpu()->ci_ci.icache_size = 16 K; 350 assoc = 4; 351 break; 352 case MPC604e: 353 case MPC604ev: 354 curcpu()->ci_ci.dcache_size = 32 K; 355 curcpu()->ci_ci.icache_size = 32 K; 356 assoc = 4; 357 break; 358 case IBMPOWER3II: 359 curcpu()->ci_ci.dcache_size = 64 K; 360 curcpu()->ci_ci.icache_size = 32 K; 361 curcpu()->ci_ci.dcache_line_size = 128; 362 curcpu()->ci_ci.icache_line_size = 128; 363 assoc = 128; /* not a typo */ 364 break; 365 case IBM970: 366 case IBM970FX: 367 case IBM970MP: 368 curcpu()->ci_ci.dcache_size = 32 K; 369 curcpu()->ci_ci.icache_size = 64 K; 370 curcpu()->ci_ci.dcache_line_size = 128; 371 curcpu()->ci_ci.icache_line_size = 128; 372 assoc = 2; 373 break; 374 375 default: 376 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 377 curcpu()->ci_ci.icache_size = PAGE_SIZE; 378 assoc = 1; 379 #undef K 380 } 381 382 /* 383 * Possibly recolor. 384 */ 385 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 386 } 387 388 struct cpu_info * 389 cpu_attach_common(struct device *self, int id) 390 { 391 struct cpu_info *ci; 392 u_int pvr, vers; 393 394 ci = &cpu_info[id]; 395 #ifndef MULTIPROCESSOR 396 /* 397 * If this isn't the primary CPU, print an error message 398 * and just bail out. 399 */ 400 if (id != 0) { 401 aprint_normal(": ID %d\n", id); 402 aprint_normal("%s: processor off-line; multiprocessor support " 403 "not present in kernel\n", self->dv_xname); 404 return (NULL); 405 } 406 #endif 407 408 ci->ci_cpuid = id; 409 ci->ci_idepth = -1; 410 ci->ci_dev = self; 411 ci->ci_idlespin = cpu_idlespin; 412 413 pvr = mfpvr(); 414 vers = (pvr >> 16) & 0xffff; 415 416 switch (id) { 417 case 0: 418 /* load my cpu_number to PIR */ 419 switch (vers) { 420 case MPC601: 421 case MPC604: 422 case MPC604e: 423 case MPC604ev: 424 case MPC7400: 425 case MPC7410: 426 case MPC7447A: 427 case MPC7448: 428 case MPC7450: 429 case MPC7455: 430 case MPC7457: 431 mtspr(SPR_PIR, id); 432 } 433 cpu_setup(self, ci); 434 break; 435 default: 436 if (id >= CPU_MAXNUM) { 437 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 438 panic("cpuattach"); 439 } 440 #ifndef MULTIPROCESSOR 441 aprint_normal(" not configured\n"); 442 return NULL; 443 #else 444 mi_cpu_attach(ci); 445 break; 446 #endif 447 } 448 return (ci); 449 } 450 451 void 452 cpu_setup(self, ci) 453 struct device *self; 454 struct cpu_info *ci; 455 { 456 u_int hid0, hid0_save, pvr, vers; 457 const char *bitmask; 458 char hidbuf[128]; 459 char model[80]; 460 461 pvr = mfpvr(); 462 vers = (pvr >> 16) & 0xffff; 463 464 cpu_identify(model, sizeof(model)); 465 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 466 cpu_number() == 0 ? " (primary)" : ""); 467 468 /* set the cpu number */ 469 ci->ci_cpuid = cpu_number(); 470 hid0_save = hid0 = mfspr(SPR_HID0); 471 472 cpu_probe_cache(); 473 474 /* 475 * Configure power-saving mode. 476 */ 477 switch (vers) { 478 case MPC604: 479 case MPC604e: 480 case MPC604ev: 481 /* 482 * Do not have HID0 support settings, but can support 483 * MSR[POW] off 484 */ 485 powersave = 1; 486 break; 487 488 case MPC603: 489 case MPC603e: 490 case MPC603ev: 491 case MPC750: 492 case IBM750FX: 493 case MPC7400: 494 case MPC7410: 495 case MPC8240: 496 case MPC8245: 497 case MPCG2: 498 /* Select DOZE mode. */ 499 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 500 hid0 |= HID0_DOZE | HID0_DPM; 501 powersave = 1; 502 break; 503 504 case MPC7447A: 505 case MPC7448: 506 case MPC7457: 507 case MPC7455: 508 case MPC7450: 509 /* Enable the 7450 branch caches */ 510 hid0 |= HID0_SGE | HID0_BTIC; 511 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 512 /* Enable more and larger BAT registers */ 513 if (oeacpufeat & OEACPU_XBSEN) 514 hid0 |= HID0_XBSEN; 515 if (oeacpufeat & OEACPU_HIGHBAT) 516 hid0 |= HID0_HIGH_BAT_EN; 517 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 518 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 519 hid0 &= ~HID0_BTIC; 520 /* Select NAP mode. */ 521 hid0 &= ~HID0_SLEEP; 522 hid0 |= HID0_NAP | HID0_DPM; 523 // powersave = 1; 524 break; 525 526 case IBM970: 527 case IBM970FX: 528 case IBM970MP: 529 case IBMPOWER3II: 530 default: 531 /* No power-saving mode is available. */ ; 532 } 533 534 #ifdef NAPMODE 535 switch (vers) { 536 case IBM750FX: 537 case MPC750: 538 case MPC7400: 539 /* Select NAP mode. */ 540 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 541 hid0 |= HID0_NAP; 542 break; 543 } 544 #endif 545 546 switch (vers) { 547 case IBM750FX: 548 case MPC750: 549 hid0 &= ~HID0_DBP; /* XXX correct? */ 550 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 551 break; 552 553 case MPC7400: 554 case MPC7410: 555 hid0 &= ~HID0_SPD; 556 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 557 hid0 |= HID0_EIEC; 558 break; 559 } 560 561 if (hid0 != hid0_save) { 562 mtspr(SPR_HID0, hid0); 563 __asm volatile("sync;isync"); 564 } 565 566 567 switch (vers) { 568 case MPC601: 569 bitmask = HID0_601_BITMASK; 570 break; 571 case MPC7450: 572 case MPC7455: 573 case MPC7457: 574 bitmask = HID0_7450_BITMASK; 575 break; 576 case IBM970: 577 case IBM970FX: 578 case IBM970MP: 579 bitmask = 0; 580 break; 581 default: 582 bitmask = HID0_BITMASK; 583 break; 584 } 585 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 586 aprint_normal("%s: HID0 %s, powersave: %d\n", self->dv_xname, hidbuf, 587 powersave); 588 589 ci->ci_khz = 0; 590 591 /* 592 * Display speed and cache configuration. 593 */ 594 switch (vers) { 595 case MPC604: 596 case MPC604e: 597 case MPC604ev: 598 case MPC750: 599 case IBM750FX: 600 case MPC7400: 601 case MPC7410: 602 case MPC7447A: 603 case MPC7448: 604 case MPC7450: 605 case MPC7455: 606 case MPC7457: 607 aprint_normal("%s: ", self->dv_xname); 608 cpu_probe_speed(ci); 609 aprint_normal("%u.%02u MHz", 610 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 611 switch (vers) { 612 case MPC7450: /* 7441 does not have L3! */ 613 case MPC7455: /* 7445 does not have L3! */ 614 case MPC7457: /* 7447 does not have L3! */ 615 cpu_config_l3cr(vers); 616 break; 617 case IBM750FX: 618 case MPC750: 619 case MPC7400: 620 case MPC7410: 621 case MPC7447A: 622 case MPC7448: 623 cpu_config_l2cr(pvr); 624 break; 625 default: 626 break; 627 } 628 aprint_normal("\n"); 629 break; 630 } 631 632 #if NSYSMON_ENVSYS > 0 633 /* 634 * Attach MPC750 temperature sensor to the envsys subsystem. 635 * XXX the 74xx series also has this sensor, but it is not 636 * XXX supported by Motorola and may return values that are off by 637 * XXX 35-55 degrees C. 638 */ 639 if (vers == MPC750 || vers == IBM750FX) 640 cpu_tau_setup(ci); 641 #endif 642 643 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 644 NULL, self->dv_xname, "clock"); 645 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 646 NULL, self->dv_xname, "soft clock"); 647 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 648 NULL, self->dv_xname, "soft net"); 649 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 650 NULL, self->dv_xname, "soft serial"); 651 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 652 NULL, self->dv_xname, "traps"); 653 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 654 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 655 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 656 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 657 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 658 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 659 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 660 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 661 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 662 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 663 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 664 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 665 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 666 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 667 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 668 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 669 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 670 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 671 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 672 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 673 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 674 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 675 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 676 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 677 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 678 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 679 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 680 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 681 #ifdef ALTIVEC 682 if (cpu_altivec) { 683 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 684 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 685 } 686 #endif 687 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 688 NULL, self->dv_xname, "IPIs"); 689 } 690 691 /* 692 * According to a document labeled "PVR Register Settings": 693 ** For integrated microprocessors the PVR register inside the device 694 ** will identify the version of the microprocessor core. You must also 695 ** read the Device ID, PCI register 02, to identify the part and the 696 ** Revision ID, PCI register 08, to identify the revision of the 697 ** integrated microprocessor. 698 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 699 */ 700 701 void 702 cpu_identify(char *str, size_t len) 703 { 704 u_int pvr, major, minor; 705 uint16_t vers, rev, revfmt; 706 const struct cputab *cp; 707 const char *name; 708 size_t n; 709 710 pvr = mfpvr(); 711 vers = pvr >> 16; 712 rev = pvr; 713 714 switch (vers) { 715 case MPC7410: 716 minor = (pvr >> 0) & 0xff; 717 major = minor <= 4 ? 1 : 2; 718 break; 719 case MPCG2: /*XXX see note above */ 720 major = (pvr >> 4) & 0xf; 721 minor = (pvr >> 0) & 0xf; 722 break; 723 default: 724 major = (pvr >> 8) & 0xf; 725 minor = (pvr >> 0) & 0xf; 726 } 727 728 for (cp = models; cp->name[0] != '\0'; cp++) { 729 if (cp->version == vers) 730 break; 731 } 732 733 if (str == NULL) { 734 str = cpu_model; 735 len = sizeof(cpu_model); 736 cpu = vers; 737 } 738 739 revfmt = cp->revfmt; 740 name = cp->name; 741 if (rev == MPC750 && pvr == 15) { 742 name = "755"; 743 revfmt = REVFMT_HEX; 744 } 745 746 if (cp->name[0] != '\0') { 747 n = snprintf(str, len, "%s (Revision ", cp->name); 748 } else { 749 n = snprintf(str, len, "Version %#x (Revision ", vers); 750 } 751 if (len > n) { 752 switch (revfmt) { 753 case REVFMT_MAJMIN: 754 snprintf(str + n, len - n, "%u.%u)", major, minor); 755 break; 756 case REVFMT_HEX: 757 snprintf(str + n, len - n, "0x%04x)", rev); 758 break; 759 case REVFMT_DEC: 760 snprintf(str + n, len - n, "%u)", rev); 761 break; 762 } 763 } 764 } 765 766 #ifdef L2CR_CONFIG 767 u_int l2cr_config = L2CR_CONFIG; 768 #else 769 u_int l2cr_config = 0; 770 #endif 771 772 #ifdef L3CR_CONFIG 773 u_int l3cr_config = L3CR_CONFIG; 774 #else 775 u_int l3cr_config = 0; 776 #endif 777 778 void 779 cpu_enable_l2cr(register_t l2cr) 780 { 781 register_t msr, x; 782 uint16_t vers; 783 784 vers = mfpvr() >> 16; 785 786 /* Disable interrupts and set the cache config bits. */ 787 msr = mfmsr(); 788 mtmsr(msr & ~PSL_EE); 789 #ifdef ALTIVEC 790 if (cpu_altivec) 791 __asm volatile("dssall"); 792 #endif 793 __asm volatile("sync"); 794 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 795 __asm volatile("sync"); 796 797 /* Wait for L2 clock to be stable (640 L2 clocks). */ 798 delay(100); 799 800 /* Invalidate all L2 contents. */ 801 if (MPC745X_P(vers)) { 802 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 803 do { 804 x = mfspr(SPR_L2CR); 805 } while (x & L2CR_L2I); 806 } else { 807 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 808 do { 809 x = mfspr(SPR_L2CR); 810 } while (x & L2CR_L2IP); 811 } 812 /* Enable L2 cache. */ 813 l2cr |= L2CR_L2E; 814 mtspr(SPR_L2CR, l2cr); 815 mtmsr(msr); 816 } 817 818 void 819 cpu_enable_l3cr(register_t l3cr) 820 { 821 register_t x; 822 823 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 824 825 /* 826 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 827 * L3CLKEN. (also mask off reserved bits in case they were included 828 * in L3CR_CONFIG) 829 */ 830 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 831 mtspr(SPR_L3CR, l3cr); 832 833 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 834 l3cr |= 0x04000000; 835 mtspr(SPR_L3CR, l3cr); 836 837 /* 3: Set L3CLKEN to 1*/ 838 l3cr |= L3CR_L3CLKEN; 839 mtspr(SPR_L3CR, l3cr); 840 841 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 842 __asm volatile("dssall;sync"); 843 /* L3 cache is already disabled, no need to clear L3E */ 844 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 845 do { 846 x = mfspr(SPR_L3CR); 847 } while (x & L3CR_L3I); 848 849 /* 6: Clear L3CLKEN to 0 */ 850 l3cr &= ~L3CR_L3CLKEN; 851 mtspr(SPR_L3CR, l3cr); 852 853 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 854 __asm volatile("sync"); 855 delay(100); 856 857 /* 8: Set L3E and L3CLKEN */ 858 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 859 mtspr(SPR_L3CR, l3cr); 860 861 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 862 __asm volatile("sync"); 863 delay(100); 864 } 865 866 void 867 cpu_config_l2cr(int pvr) 868 { 869 register_t l2cr; 870 u_int vers = (pvr >> 16) & 0xffff; 871 872 l2cr = mfspr(SPR_L2CR); 873 874 /* 875 * For MP systems, the firmware may only configure the L2 cache 876 * on the first CPU. In this case, assume that the other CPUs 877 * should use the same value for L2CR. 878 */ 879 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 880 l2cr_config = l2cr; 881 } 882 883 /* 884 * Configure L2 cache if not enabled. 885 */ 886 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 887 cpu_enable_l2cr(l2cr_config); 888 l2cr = mfspr(SPR_L2CR); 889 } 890 891 if ((l2cr & L2CR_L2E) == 0) { 892 aprint_normal(" L2 cache present but not enabled "); 893 return; 894 } 895 aprint_normal(","); 896 897 switch (vers) { 898 case IBM750FX: 899 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 900 break; 901 case MPC750: 902 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 903 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 904 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 905 else 906 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 907 break; 908 case MPC7447A: 909 case MPC7457: 910 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 911 return; 912 case MPC7448: 913 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 914 return; 915 case MPC7450: 916 case MPC7455: 917 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 918 break; 919 default: 920 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 921 break; 922 } 923 } 924 925 void 926 cpu_config_l3cr(int vers) 927 { 928 register_t l2cr; 929 register_t l3cr; 930 931 l2cr = mfspr(SPR_L2CR); 932 933 /* 934 * For MP systems, the firmware may only configure the L2 cache 935 * on the first CPU. In this case, assume that the other CPUs 936 * should use the same value for L2CR. 937 */ 938 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 939 l2cr_config = l2cr; 940 } 941 942 /* 943 * Configure L2 cache if not enabled. 944 */ 945 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 946 cpu_enable_l2cr(l2cr_config); 947 l2cr = mfspr(SPR_L2CR); 948 } 949 950 aprint_normal(","); 951 switch (vers) { 952 case MPC7447A: 953 case MPC7457: 954 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 955 return; 956 case MPC7448: 957 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 958 return; 959 default: 960 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 961 break; 962 } 963 964 l3cr = mfspr(SPR_L3CR); 965 966 /* 967 * For MP systems, the firmware may only configure the L3 cache 968 * on the first CPU. In this case, assume that the other CPUs 969 * should use the same value for L3CR. 970 */ 971 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 972 l3cr_config = l3cr; 973 } 974 975 /* 976 * Configure L3 cache if not enabled. 977 */ 978 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 979 cpu_enable_l3cr(l3cr_config); 980 l3cr = mfspr(SPR_L3CR); 981 } 982 983 if (l3cr & L3CR_L3E) { 984 aprint_normal(","); 985 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 986 } 987 } 988 989 void 990 cpu_probe_speed(struct cpu_info *ci) 991 { 992 uint64_t cps; 993 994 mtspr(SPR_MMCR0, MMCR0_FC); 995 mtspr(SPR_PMC1, 0); 996 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 997 delay(100000); 998 cps = (mfspr(SPR_PMC1) * 10) + 4999; 999 1000 mtspr(SPR_MMCR0, MMCR0_FC); 1001 1002 ci->ci_khz = cps / 1000; 1003 } 1004 1005 #if NSYSMON_ENVSYS > 0 1006 void 1007 cpu_tau_setup(struct cpu_info *ci) 1008 { 1009 struct sysmon_envsys *sme; 1010 int error, therm_delay; 1011 1012 mtspr(SPR_THRM1, SPR_THRM_VALID); 1013 mtspr(SPR_THRM2, 0); 1014 1015 /* 1016 * we need to figure out how much 20+us in units of CPU clock cycles 1017 * are 1018 */ 1019 1020 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1021 1022 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1023 1024 sme = sysmon_envsys_create(); 1025 1026 sensor.units = ENVSYS_STEMP; 1027 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1028 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1029 sysmon_envsys_destroy(sme); 1030 return; 1031 } 1032 1033 sme->sme_name = ci->ci_dev->dv_xname; 1034 sme->sme_cookie = ci; 1035 sme->sme_refresh = cpu_tau_refresh; 1036 1037 if ((error = sysmon_envsys_register(sme)) != 0) { 1038 aprint_error("%s: unable to register with sysmon (%d)\n", 1039 ci->ci_dev->dv_xname, error); 1040 sysmon_envsys_destroy(sme); 1041 } 1042 } 1043 1044 1045 /* Find the temperature of the CPU. */ 1046 void 1047 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1048 { 1049 int i, threshold, count; 1050 1051 threshold = 64; /* Half of the 7-bit sensor range */ 1052 1053 /* Successive-approximation code adapted from Motorola 1054 * application note AN1800/D, "Programming the Thermal Assist 1055 * Unit in the MPC750 Microprocessor". 1056 */ 1057 for (i = 5; i >= 0 ; i--) { 1058 mtspr(SPR_THRM1, 1059 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1060 count = 0; 1061 while ((count < 100000) && 1062 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1063 count++; 1064 delay(1); 1065 } 1066 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1067 /* The interrupt bit was set, meaning the 1068 * temperature was above the threshold 1069 */ 1070 threshold += 1 << i; 1071 } else { 1072 /* Temperature was below the threshold */ 1073 threshold -= 1 << i; 1074 } 1075 1076 } 1077 threshold += 2; 1078 1079 /* Convert the temperature in degrees C to microkelvin */ 1080 edata->value_cur = (threshold * 1000000) + 273150000; 1081 edata->state = ENVSYS_SVALID; 1082 } 1083 #endif /* NSYSMON_ENVSYS > 0 */ 1084 1085 #ifdef MULTIPROCESSOR 1086 extern volatile u_int cpu_spinstart_ack; 1087 1088 int 1089 cpu_spinup(struct device *self, struct cpu_info *ci) 1090 { 1091 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1092 struct pglist mlist; 1093 int i, error, pvr, vers; 1094 char *cp, *hp; 1095 1096 pvr = mfpvr(); 1097 vers = pvr >> 16; 1098 KASSERT(ci != curcpu()); 1099 1100 /* 1101 * Allocate some contiguous pages for the intteup PCB and stack 1102 * from the lowest 256MB (because bat0 always maps it va == pa). 1103 * Must be 16 byte aligned. 1104 */ 1105 error = uvm_pglistalloc(INTSTK, 0x10000, 0x10000000, 16, 0, 1106 &mlist, 1, 1); 1107 if (error) { 1108 aprint_error(": unable to allocate idle stack\n"); 1109 return -1; 1110 } 1111 1112 KASSERT(ci != &cpu_info[0]); 1113 1114 cp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1115 memset(cp, 0, INTSTK); 1116 1117 ci->ci_intstk = cp; 1118 1119 /* Now allocate a hatch stack */ 1120 error = uvm_pglistalloc(0x1000, 0x10000, 0x10000000, 16, 0, 1121 &mlist, 1, 1); 1122 if (error) { 1123 aprint_error(": unable to allocate hatch stack\n"); 1124 return -1; 1125 } 1126 1127 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1128 memset(hp, 0, 0x1000); 1129 1130 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1131 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1132 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1133 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1134 1135 cpu_hatch_data = h; 1136 h->running = 0; 1137 h->self = self; 1138 h->ci = ci; 1139 h->pir = ci->ci_cpuid; 1140 1141 cpu_hatch_stack = (uint32_t)hp; 1142 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1143 1144 /* copy special registers */ 1145 1146 h->hid0 = mfspr(SPR_HID0); 1147 1148 __asm volatile ("mfsdr1 %0" : "=r"(h->sdr1)); 1149 for (i = 0; i < 16; i++) { 1150 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1151 "r"(i << ADDR_SR_SHFT)); 1152 } 1153 if (oeacpufeat & OEACPU_64) 1154 h->asr = mfspr(SPR_ASR); 1155 else 1156 h->asr = 0; 1157 1158 /* copy the bat regs */ 1159 __asm volatile ("mfibatu %0,0" : "=r"(h->batu[0])); 1160 __asm volatile ("mfibatl %0,0" : "=r"(h->batl[0])); 1161 __asm volatile ("mfibatu %0,1" : "=r"(h->batu[1])); 1162 __asm volatile ("mfibatl %0,1" : "=r"(h->batl[1])); 1163 __asm volatile ("mfibatu %0,2" : "=r"(h->batu[2])); 1164 __asm volatile ("mfibatl %0,2" : "=r"(h->batl[2])); 1165 __asm volatile ("mfibatu %0,3" : "=r"(h->batu[3])); 1166 __asm volatile ("mfibatl %0,3" : "=r"(h->batl[3])); 1167 __asm volatile ("sync; isync"); 1168 1169 if (md_setup_trampoline(h, ci) == -1) 1170 return -1; 1171 md_presync_timebase(h); 1172 md_start_timebase(h); 1173 1174 /* wait for secondary printf */ 1175 1176 delay(200000); 1177 1178 if (h->running < 1) { 1179 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1180 ci->ci_cpuid, cpu_spinstart_ack); 1181 Debugger(); 1182 return -1; 1183 } 1184 1185 /* Register IPI Interrupt */ 1186 if (ipiops.ppc_establish_ipi) 1187 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1188 1189 return 0; 1190 } 1191 1192 static volatile int start_secondary_cpu; 1193 extern void tlbia(void); 1194 1195 register_t 1196 cpu_hatch(void) 1197 { 1198 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1199 struct cpu_info * const ci = h->ci; 1200 u_int msr; 1201 int i; 1202 1203 /* Initialize timebase. */ 1204 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1205 1206 /* 1207 * Set PIR (Processor Identification Register). i.e. whoami 1208 * Note that PIR is read-only on some CPU versions, so we write to it 1209 * only if it has a different value than we need. 1210 */ 1211 1212 msr = mfspr(SPR_PIR); 1213 if (msr != h->pir) 1214 mtspr(SPR_PIR, h->pir); 1215 1216 __asm volatile ("mtsprg 0,%0" :: "r"(ci)); 1217 cpu_spinstart_ack = 0; 1218 1219 /* Initialize MMU. */ 1220 __asm ("mtibatu 0,%0" :: "r"(h->batu[0])); 1221 __asm ("mtibatl 0,%0" :: "r"(h->batl[0])); 1222 __asm ("mtibatu 1,%0" :: "r"(h->batu[1])); 1223 __asm ("mtibatl 1,%0" :: "r"(h->batl[1])); 1224 __asm ("mtibatu 2,%0" :: "r"(h->batu[2])); 1225 __asm ("mtibatl 2,%0" :: "r"(h->batl[2])); 1226 __asm ("mtibatu 3,%0" :: "r"(h->batu[3])); 1227 __asm ("mtibatl 3,%0" :: "r"(h->batl[3])); 1228 1229 mtspr(SPR_HID0, h->hid0); 1230 1231 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1232 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1233 1234 __asm volatile ("sync"); 1235 for (i = 0; i < 16; i++) 1236 __asm ("mtsrin %0,%1" :: "r"(h->sr[i]), "r"(i << ADDR_SR_SHFT)); 1237 __asm volatile ("sync; isync"); 1238 1239 if (oeacpufeat & OEACPU_64) 1240 mtspr(SPR_ASR, h->asr); 1241 1242 cpu_spinstart_ack = 1; 1243 __asm ("ptesync"); 1244 __asm ("mtsdr1 %0" :: "r"(h->sdr1)); 1245 __asm volatile ("sync; isync"); 1246 1247 cpu_spinstart_ack = 5; 1248 for (i = 0; i < 16; i++) 1249 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1250 "r"(i << ADDR_SR_SHFT)); 1251 1252 /* Enable I/D address translations. */ 1253 msr = mfmsr(); 1254 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1255 mtmsr(msr); 1256 __asm volatile ("sync; isync"); 1257 cpu_spinstart_ack = 2; 1258 1259 md_sync_timebase(h); 1260 1261 cpu_setup(h->self, ci); 1262 1263 h->running = 1; 1264 __asm volatile ("sync; isync"); 1265 1266 while (start_secondary_cpu == 0) 1267 ; 1268 1269 __asm volatile ("sync; isync"); 1270 1271 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1272 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1273 1274 md_setup_interrupts(); 1275 1276 ci->ci_ipending = 0; 1277 ci->ci_cpl = 0; 1278 1279 mtmsr(mfmsr() | PSL_EE); 1280 struct pcb * const idlepcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1281 return idlepcb->pcb_sp; 1282 } 1283 1284 void 1285 cpu_boot_secondary_processors() 1286 { 1287 start_secondary_cpu = 1; 1288 __asm volatile ("sync"); 1289 } 1290 1291 #endif /*MULTIPROCESSOR*/ 1292
Indexes created Thu Oct 02 07:10:07 GMT 2025