cpu_subr.c revision 1.50.14.4
1 /* $NetBSD: cpu_subr.c,v 1.50.14.4 2011/02/12 00:45:22 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.50.14.4 2011/02/12 00:45:22 matt Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/types.h> 48 #include <sys/lwp.h> 49 #include <sys/user.h> 50 #include <sys/malloc.h> 51 52 #include <uvm/uvm_extern.h> 53 54 #include <powerpc/oea/hid.h> 55 #include <powerpc/oea/hid_601.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/spr.h> 58 #include <powerpc/oea/cpufeat.h> 59 60 #include <dev/sysmon/sysmonvar.h> 61 62 static void cpu_enable_l2cr(register_t); 63 static void cpu_enable_l3cr(register_t); 64 static void cpu_config_l2cr(int); 65 static void cpu_config_l3cr(int); 66 static void cpu_probe_speed(struct cpu_info *); 67 static void cpu_idlespin(void); 68 #if NSYSMON_ENVSYS > 0 69 static void cpu_tau_setup(struct cpu_info *); 70 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 71 #endif 72 73 int cpu; 74 int ncpus; 75 76 struct fmttab { 77 register_t fmt_mask; 78 register_t fmt_value; 79 const char *fmt_string; 80 }; 81 82 /* 83 * This should be one per CPU but since we only support it on 750 variants it 84 * doesn't realy matter since none of them supports SMP 85 */ 86 envsys_data_t sensor; 87 88 static const struct fmttab cpu_7450_l2cr_formats[] = { 89 { L2CR_L2E, 0, " disabled" }, 90 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 93 { L2CR_L2E, ~0, " 256KB L2 cache" }, 94 { L2CR_L2PE, 0, " no parity" }, 95 { L2CR_L2PE, ~0, " parity enabled" }, 96 { 0, 0, NULL } 97 }; 98 99 static const struct fmttab cpu_7448_l2cr_formats[] = { 100 { L2CR_L2E, 0, " disabled" }, 101 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 102 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 103 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 104 { L2CR_L2E, ~0, " 1MB L2 cache" }, 105 { L2CR_L2PE, 0, " no parity" }, 106 { L2CR_L2PE, ~0, " parity enabled" }, 107 { 0, 0, NULL } 108 }; 109 110 static const struct fmttab cpu_7457_l2cr_formats[] = { 111 { L2CR_L2E, 0, " disabled" }, 112 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 113 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 114 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 115 { L2CR_L2E, ~0, " 512KB L2 cache" }, 116 { L2CR_L2PE, 0, " no parity" }, 117 { L2CR_L2PE, ~0, " parity enabled" }, 118 { 0, 0, NULL } 119 }; 120 121 static const struct fmttab cpu_7450_l3cr_formats[] = { 122 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 123 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 124 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 125 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 126 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 127 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 128 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 129 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 130 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 131 { L3CR_L3SIZ, ~0, " L3 cache" }, 132 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 133 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 134 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 135 { L3CR_L3CLK, ~0, " at" }, 136 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 137 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 138 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 139 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 140 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 141 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 142 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 143 { L3CR_L3CLK, ~0, " ratio" }, 144 { 0, 0, NULL }, 145 }; 146 147 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 148 { L2CR_L2E, 0, " disabled" }, 149 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 150 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 151 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 152 { 0, ~0, " 512KB" }, 153 { L2CR_L2WT, L2CR_L2WT, " WT" }, 154 { L2CR_L2WT, 0, " WB" }, 155 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 156 { 0, ~0, " L2 cache" }, 157 { 0, 0, NULL } 158 }; 159 160 static const struct fmttab cpu_l2cr_formats[] = { 161 { L2CR_L2E, 0, " disabled" }, 162 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 163 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 164 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 165 { L2CR_L2PE, L2CR_L2PE, " parity" }, 166 { L2CR_L2PE, 0, " no-parity" }, 167 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 168 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 169 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 170 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 171 { L2CR_L2WT, L2CR_L2WT, " WT" }, 172 { L2CR_L2WT, 0, " WB" }, 173 { L2CR_L2E, ~0, " L2 cache" }, 174 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 175 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 176 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 177 { L2CR_L2CLK, ~0, " at" }, 178 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 179 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 180 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 181 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 182 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 183 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 184 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 185 { L2CR_L2CLK, ~0, " ratio" }, 186 { 0, 0, NULL } 187 }; 188 189 static void cpu_fmttab_print(const struct fmttab *, register_t); 190 191 struct cputab { 192 const char name[8]; 193 uint16_t version; 194 uint16_t revfmt; 195 }; 196 #define REVFMT_MAJMIN 1 /* %u.%u */ 197 #define REVFMT_HEX 2 /* 0x%04x */ 198 #define REVFMT_DEC 3 /* %u */ 199 static const struct cputab models[] = { 200 { "601", MPC601, REVFMT_DEC }, 201 { "602", MPC602, REVFMT_DEC }, 202 { "603", MPC603, REVFMT_MAJMIN }, 203 { "603e", MPC603e, REVFMT_MAJMIN }, 204 { "603ev", MPC603ev, REVFMT_MAJMIN }, 205 { "G2", MPCG2, REVFMT_MAJMIN }, 206 { "604", MPC604, REVFMT_MAJMIN }, 207 { "604e", MPC604e, REVFMT_MAJMIN }, 208 { "604ev", MPC604ev, REVFMT_MAJMIN }, 209 { "620", MPC620, REVFMT_HEX }, 210 { "750", MPC750, REVFMT_MAJMIN }, 211 { "750FX", IBM750FX, REVFMT_MAJMIN }, 212 { "750GX", IBM750GX, REVFMT_MAJMIN }, 213 { "7400", MPC7400, REVFMT_MAJMIN }, 214 { "7410", MPC7410, REVFMT_MAJMIN }, 215 { "7450", MPC7450, REVFMT_MAJMIN }, 216 { "7455", MPC7455, REVFMT_MAJMIN }, 217 { "7457", MPC7457, REVFMT_MAJMIN }, 218 { "7447A", MPC7447A, REVFMT_MAJMIN }, 219 { "7448", MPC7448, REVFMT_MAJMIN }, 220 { "8240", MPC8240, REVFMT_MAJMIN }, 221 { "8245", MPC8245, REVFMT_MAJMIN }, 222 { "970", IBM970, REVFMT_MAJMIN }, 223 { "970FX", IBM970FX, REVFMT_MAJMIN }, 224 { "970MP", IBM970MP, REVFMT_MAJMIN }, 225 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 226 { "", 0, REVFMT_HEX } 227 }; 228 229 #ifdef MULTIPROCESSOR 230 struct cpu_info cpu_info[CPU_MAXNUM] = { 231 [0] = { 232 .ci_curlwp = &lwp0, 233 .ci_fpulwp = &lwp0, 234 .ci_veclwp = &lwp0, 235 }, 236 }; 237 volatile struct cpu_hatch_data *cpu_hatch_data; 238 volatile int cpu_hatch_stack; 239 extern int ticks_per_intr; 240 #include <powerpc/oea/bat.h> 241 #include <arch/powerpc/pic/picvar.h> 242 #include <arch/powerpc/pic/ipivar.h> 243 extern struct bat battable[]; 244 #else 245 struct cpu_info cpu_info[1] = { 246 [0] = { 247 .ci_curlwp = &lwp0, 248 .ci_fpulwp = &lwp0, 249 .ci_veclwp = &lwp0, 250 }, 251 }; 252 #endif /*MULTIPROCESSOR*/ 253 254 int cpu_altivec; 255 int cpu_psluserset, cpu_pslusermod; 256 char cpu_model[80]; 257 258 /* This is to be called from locore.S, and nowhere else. */ 259 260 void 261 cpu_model_init(void) 262 { 263 u_int pvr, vers; 264 265 pvr = mfpvr(); 266 vers = pvr >> 16; 267 268 oeacpufeat = 0; 269 270 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 271 vers == IBMCELL || vers == IBMPOWER6P5) 272 oeacpufeat |= OEACPU_64 | OEACPU_64_BRIDGE | OEACPU_NOBAT; 273 274 else if (vers == MPC601) 275 oeacpufeat |= OEACPU_601; 276 277 else if (MPC745X_P(vers) && vers != MPC7450) 278 oeacpufeat |= OEACPU_XBSEN | OEACPU_HIGHBAT | OEACPU_HIGHSPRG; 279 280 else if (vers == IBM750FX || vers == IBM750GX) 281 oeacpufeat |= OEACPU_HIGHBAT; 282 } 283 284 void 285 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 286 { 287 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 288 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 289 (data & fmt->fmt_mask) == fmt->fmt_value) 290 aprint_normal("%s", fmt->fmt_string); 291 } 292 } 293 294 void 295 cpu_idlespin(void) 296 { 297 register_t msr; 298 299 if (powersave <= 0) 300 return; 301 302 __asm volatile( 303 "sync;" 304 "mfmsr %0;" 305 "oris %0,%0,%1@h;" /* enter power saving mode */ 306 "mtmsr %0;" 307 "isync;" 308 : "=r"(msr) 309 : "J"(PSL_POW)); 310 } 311 312 void 313 cpu_probe_cache(void) 314 { 315 u_int assoc, pvr, vers; 316 317 pvr = mfpvr(); 318 vers = pvr >> 16; 319 320 321 /* Presently common across almost all implementations. */ 322 curcpu()->ci_ci.dcache_line_size = 32; 323 curcpu()->ci_ci.icache_line_size = 32; 324 325 326 switch (vers) { 327 #define K *1024 328 case IBM750FX: 329 case IBM750GX: 330 case MPC601: 331 case MPC750: 332 case MPC7400: 333 case MPC7447A: 334 case MPC7448: 335 case MPC7450: 336 case MPC7455: 337 case MPC7457: 338 curcpu()->ci_ci.dcache_size = 32 K; 339 curcpu()->ci_ci.icache_size = 32 K; 340 assoc = 8; 341 break; 342 case MPC603: 343 curcpu()->ci_ci.dcache_size = 8 K; 344 curcpu()->ci_ci.icache_size = 8 K; 345 assoc = 2; 346 break; 347 case MPC603e: 348 case MPC603ev: 349 case MPC604: 350 case MPC8240: 351 case MPC8245: 352 case MPCG2: 353 curcpu()->ci_ci.dcache_size = 16 K; 354 curcpu()->ci_ci.icache_size = 16 K; 355 assoc = 4; 356 break; 357 case MPC604e: 358 case MPC604ev: 359 curcpu()->ci_ci.dcache_size = 32 K; 360 curcpu()->ci_ci.icache_size = 32 K; 361 assoc = 4; 362 break; 363 case IBMPOWER3II: 364 curcpu()->ci_ci.dcache_size = 64 K; 365 curcpu()->ci_ci.icache_size = 32 K; 366 curcpu()->ci_ci.dcache_line_size = 128; 367 curcpu()->ci_ci.icache_line_size = 128; 368 assoc = 128; /* not a typo */ 369 break; 370 case IBM970: 371 case IBM970FX: 372 case IBM970MP: 373 curcpu()->ci_ci.dcache_size = 32 K; 374 curcpu()->ci_ci.icache_size = 64 K; 375 curcpu()->ci_ci.dcache_line_size = 128; 376 curcpu()->ci_ci.icache_line_size = 128; 377 assoc = 2; 378 break; 379 380 default: 381 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 382 curcpu()->ci_ci.icache_size = PAGE_SIZE; 383 assoc = 1; 384 #undef K 385 } 386 387 /* 388 * Possibly recolor. 389 */ 390 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 391 } 392 393 struct cpu_info * 394 cpu_attach_common(struct device *self, int id) 395 { 396 struct cpu_info *ci; 397 u_int pvr, vers; 398 399 ci = &cpu_info[id]; 400 #ifndef MULTIPROCESSOR 401 /* 402 * If this isn't the primary CPU, print an error message 403 * and just bail out. 404 */ 405 if (id != 0) { 406 aprint_normal(": ID %d\n", id); 407 aprint_normal("%s: processor off-line; multiprocessor support " 408 "not present in kernel\n", self->dv_xname); 409 return (NULL); 410 } 411 #endif 412 413 ci->ci_cpuid = id; 414 ci->ci_idepth = -1; 415 ci->ci_dev = self; 416 ci->ci_idlespin = cpu_idlespin; 417 418 pvr = mfpvr(); 419 vers = (pvr >> 16) & 0xffff; 420 421 switch (id) { 422 case 0: 423 /* load my cpu_number to PIR */ 424 switch (vers) { 425 case MPC601: 426 case MPC604: 427 case MPC604e: 428 case MPC604ev: 429 case MPC7400: 430 case MPC7410: 431 case MPC7447A: 432 case MPC7448: 433 case MPC7450: 434 case MPC7455: 435 case MPC7457: 436 mtspr(SPR_PIR, id); 437 } 438 cpu_setup(self, ci); 439 break; 440 default: 441 if (id >= CPU_MAXNUM) { 442 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 443 panic("cpuattach"); 444 } 445 #ifndef MULTIPROCESSOR 446 aprint_normal(" not configured\n"); 447 return NULL; 448 #else 449 mi_cpu_attach(ci); 450 break; 451 #endif 452 } 453 return (ci); 454 } 455 456 void 457 cpu_setup(self, ci) 458 struct device *self; 459 struct cpu_info *ci; 460 { 461 u_int hid0, hid0_save, pvr, vers; 462 const char *bitmask; 463 char hidbuf[128]; 464 char model[80]; 465 466 pvr = mfpvr(); 467 vers = (pvr >> 16) & 0xffff; 468 469 cpu_identify(model, sizeof(model)); 470 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 471 cpu_number() == 0 ? " (primary)" : ""); 472 473 /* set the cpu number */ 474 ci->ci_cpuid = cpu_number(); 475 hid0_save = hid0 = mfspr(SPR_HID0); 476 477 cpu_probe_cache(); 478 479 /* 480 * Configure power-saving mode. 481 */ 482 switch (vers) { 483 case MPC604: 484 case MPC604e: 485 case MPC604ev: 486 /* 487 * Do not have HID0 support settings, but can support 488 * MSR[POW] off 489 */ 490 powersave = 1; 491 break; 492 493 case MPC603: 494 case MPC603e: 495 case MPC603ev: 496 case MPC750: 497 case IBM750FX: 498 case IBM750GX: 499 case MPC7400: 500 case MPC7410: 501 case MPC8240: 502 case MPC8245: 503 case MPCG2: 504 /* Select DOZE mode. */ 505 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 506 hid0 |= HID0_DOZE | HID0_DPM; 507 powersave = 1; 508 break; 509 510 case MPC7447A: 511 case MPC7448: 512 case MPC7457: 513 case MPC7455: 514 case MPC7450: 515 /* Enable the 7450 branch caches */ 516 hid0 |= HID0_SGE | HID0_BTIC; 517 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 518 /* Enable more and larger BAT registers */ 519 if (oeacpufeat & OEACPU_XBSEN) 520 hid0 |= HID0_XBSEN; 521 if (oeacpufeat & OEACPU_HIGHBAT) 522 hid0 |= HID0_HIGH_BAT_EN; 523 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 524 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 525 hid0 &= ~HID0_BTIC; 526 /* Select NAP mode. */ 527 hid0 &= ~HID0_SLEEP; 528 hid0 |= HID0_NAP | HID0_DPM; 529 // powersave = 1; 530 break; 531 532 case IBM970: 533 case IBM970FX: 534 case IBM970MP: 535 case IBMPOWER3II: 536 default: 537 /* No power-saving mode is available. */ ; 538 } 539 540 #ifdef NAPMODE 541 switch (vers) { 542 case IBM750FX: 543 case IBM750GX: 544 case MPC750: 545 case MPC7400: 546 /* Select NAP mode. */ 547 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 548 hid0 |= HID0_NAP; 549 break; 550 } 551 #endif 552 553 switch (vers) { 554 case IBM750FX: 555 case IBM750GX: 556 case MPC750: 557 hid0 &= ~HID0_DBP; /* XXX correct? */ 558 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 559 break; 560 561 case MPC7400: 562 case MPC7410: 563 hid0 &= ~HID0_SPD; 564 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 565 hid0 |= HID0_EIEC; 566 break; 567 } 568 569 if (hid0 != hid0_save) { 570 mtspr(SPR_HID0, hid0); 571 __asm volatile("sync;isync"); 572 } 573 574 575 switch (vers) { 576 case MPC601: 577 bitmask = HID0_601_BITMASK; 578 break; 579 case MPC7450: 580 case MPC7455: 581 case MPC7457: 582 bitmask = HID0_7450_BITMASK; 583 break; 584 case IBM970: 585 case IBM970FX: 586 case IBM970MP: 587 bitmask = 0; 588 break; 589 default: 590 bitmask = HID0_BITMASK; 591 break; 592 } 593 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 594 aprint_normal("%s: HID0 %s, powersave: %d\n", self->dv_xname, hidbuf, 595 powersave); 596 597 ci->ci_khz = 0; 598 599 /* 600 * Display speed and cache configuration. 601 */ 602 switch (vers) { 603 case MPC604: 604 case MPC604e: 605 case MPC604ev: 606 case MPC750: 607 case IBM750FX: 608 case IBM750GX: 609 case MPC7400: 610 case MPC7410: 611 case MPC7447A: 612 case MPC7448: 613 case MPC7450: 614 case MPC7455: 615 case MPC7457: 616 aprint_normal("%s: ", self->dv_xname); 617 cpu_probe_speed(ci); 618 aprint_normal("%u.%02u MHz", 619 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 620 switch (vers) { 621 case MPC7450: /* 7441 does not have L3! */ 622 case MPC7455: /* 7445 does not have L3! */ 623 case MPC7457: /* 7447 does not have L3! */ 624 cpu_config_l3cr(vers); 625 break; 626 case IBM750FX: 627 case IBM750GX: 628 case MPC750: 629 case MPC7400: 630 case MPC7410: 631 case MPC7447A: 632 case MPC7448: 633 cpu_config_l2cr(pvr); 634 break; 635 default: 636 break; 637 } 638 aprint_normal("\n"); 639 break; 640 } 641 642 #if NSYSMON_ENVSYS > 0 643 /* 644 * Attach MPC750 temperature sensor to the envsys subsystem. 645 * XXX the 74xx series also has this sensor, but it is not 646 * XXX supported by Motorola and may return values that are off by 647 * XXX 35-55 degrees C. 648 */ 649 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 650 cpu_tau_setup(ci); 651 #endif 652 653 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 654 NULL, self->dv_xname, "clock"); 655 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 656 NULL, self->dv_xname, "soft clock"); 657 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 658 NULL, self->dv_xname, "soft net"); 659 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 660 NULL, self->dv_xname, "soft serial"); 661 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 662 NULL, self->dv_xname, "traps"); 663 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 664 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 665 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 666 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 667 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 668 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 669 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 670 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 671 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 672 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 673 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 674 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 675 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 676 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 677 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 678 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 679 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 680 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 681 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 682 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 683 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 684 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 685 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 686 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 687 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 688 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 689 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 690 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 691 #ifdef ALTIVEC 692 if (cpu_altivec) { 693 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 694 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 695 } 696 #endif 697 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 698 NULL, self->dv_xname, "IPIs"); 699 } 700 701 /* 702 * According to a document labeled "PVR Register Settings": 703 ** For integrated microprocessors the PVR register inside the device 704 ** will identify the version of the microprocessor core. You must also 705 ** read the Device ID, PCI register 02, to identify the part and the 706 ** Revision ID, PCI register 08, to identify the revision of the 707 ** integrated microprocessor. 708 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 709 */ 710 711 void 712 cpu_identify(char *str, size_t len) 713 { 714 u_int pvr, major, minor; 715 uint16_t vers, rev, revfmt; 716 const struct cputab *cp; 717 const char *name; 718 size_t n; 719 720 pvr = mfpvr(); 721 vers = pvr >> 16; 722 rev = pvr; 723 724 switch (vers) { 725 case MPC7410: 726 minor = (pvr >> 0) & 0xff; 727 major = minor <= 4 ? 1 : 2; 728 break; 729 case MPCG2: /*XXX see note above */ 730 major = (pvr >> 4) & 0xf; 731 minor = (pvr >> 0) & 0xf; 732 break; 733 default: 734 major = (pvr >> 8) & 0xf; 735 minor = (pvr >> 0) & 0xf; 736 } 737 738 for (cp = models; cp->name[0] != '\0'; cp++) { 739 if (cp->version == vers) 740 break; 741 } 742 743 if (str == NULL) { 744 str = cpu_model; 745 len = sizeof(cpu_model); 746 cpu = vers; 747 } 748 749 revfmt = cp->revfmt; 750 name = cp->name; 751 if (rev == MPC750 && pvr == 15) { 752 name = "755"; 753 revfmt = REVFMT_HEX; 754 } 755 756 if (cp->name[0] != '\0') { 757 n = snprintf(str, len, "%s (Revision ", cp->name); 758 } else { 759 n = snprintf(str, len, "Version %#x (Revision ", vers); 760 } 761 if (len > n) { 762 switch (revfmt) { 763 case REVFMT_MAJMIN: 764 snprintf(str + n, len - n, "%u.%u)", major, minor); 765 break; 766 case REVFMT_HEX: 767 snprintf(str + n, len - n, "0x%04x)", rev); 768 break; 769 case REVFMT_DEC: 770 snprintf(str + n, len - n, "%u)", rev); 771 break; 772 } 773 } 774 } 775 776 #ifdef L2CR_CONFIG 777 u_int l2cr_config = L2CR_CONFIG; 778 #else 779 u_int l2cr_config = 0; 780 #endif 781 782 #ifdef L3CR_CONFIG 783 u_int l3cr_config = L3CR_CONFIG; 784 #else 785 u_int l3cr_config = 0; 786 #endif 787 788 void 789 cpu_enable_l2cr(register_t l2cr) 790 { 791 register_t msr, x; 792 uint16_t vers; 793 794 vers = mfpvr() >> 16; 795 796 /* Disable interrupts and set the cache config bits. */ 797 msr = mfmsr(); 798 mtmsr(msr & ~PSL_EE); 799 #ifdef ALTIVEC 800 if (cpu_altivec) 801 __asm volatile("dssall"); 802 #endif 803 __asm volatile("sync"); 804 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 805 __asm volatile("sync"); 806 807 /* Wait for L2 clock to be stable (640 L2 clocks). */ 808 delay(100); 809 810 /* Invalidate all L2 contents. */ 811 if (MPC745X_P(vers)) { 812 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 813 do { 814 x = mfspr(SPR_L2CR); 815 } while (x & L2CR_L2I); 816 } else { 817 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 818 do { 819 x = mfspr(SPR_L2CR); 820 } while (x & L2CR_L2IP); 821 } 822 /* Enable L2 cache. */ 823 l2cr |= L2CR_L2E; 824 mtspr(SPR_L2CR, l2cr); 825 mtmsr(msr); 826 } 827 828 void 829 cpu_enable_l3cr(register_t l3cr) 830 { 831 register_t x; 832 833 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 834 835 /* 836 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 837 * L3CLKEN. (also mask off reserved bits in case they were included 838 * in L3CR_CONFIG) 839 */ 840 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 841 mtspr(SPR_L3CR, l3cr); 842 843 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 844 l3cr |= 0x04000000; 845 mtspr(SPR_L3CR, l3cr); 846 847 /* 3: Set L3CLKEN to 1*/ 848 l3cr |= L3CR_L3CLKEN; 849 mtspr(SPR_L3CR, l3cr); 850 851 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 852 __asm volatile("dssall;sync"); 853 /* L3 cache is already disabled, no need to clear L3E */ 854 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 855 do { 856 x = mfspr(SPR_L3CR); 857 } while (x & L3CR_L3I); 858 859 /* 6: Clear L3CLKEN to 0 */ 860 l3cr &= ~L3CR_L3CLKEN; 861 mtspr(SPR_L3CR, l3cr); 862 863 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 864 __asm volatile("sync"); 865 delay(100); 866 867 /* 8: Set L3E and L3CLKEN */ 868 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 869 mtspr(SPR_L3CR, l3cr); 870 871 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 872 __asm volatile("sync"); 873 delay(100); 874 } 875 876 void 877 cpu_config_l2cr(int pvr) 878 { 879 register_t l2cr; 880 u_int vers = (pvr >> 16) & 0xffff; 881 882 l2cr = mfspr(SPR_L2CR); 883 884 /* 885 * For MP systems, the firmware may only configure the L2 cache 886 * on the first CPU. In this case, assume that the other CPUs 887 * should use the same value for L2CR. 888 */ 889 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 890 l2cr_config = l2cr; 891 } 892 893 /* 894 * Configure L2 cache if not enabled. 895 */ 896 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 897 cpu_enable_l2cr(l2cr_config); 898 l2cr = mfspr(SPR_L2CR); 899 } 900 901 if ((l2cr & L2CR_L2E) == 0) { 902 aprint_normal(" L2 cache present but not enabled "); 903 return; 904 } 905 aprint_normal(","); 906 907 switch (vers) { 908 case IBM750FX: 909 case IBM750GX: 910 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 911 break; 912 case MPC750: 913 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 914 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 915 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 916 else 917 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 918 break; 919 case MPC7447A: 920 case MPC7457: 921 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 922 return; 923 case MPC7448: 924 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 925 return; 926 case MPC7450: 927 case MPC7455: 928 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 929 break; 930 default: 931 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 932 break; 933 } 934 } 935 936 void 937 cpu_config_l3cr(int vers) 938 { 939 register_t l2cr; 940 register_t l3cr; 941 942 l2cr = mfspr(SPR_L2CR); 943 944 /* 945 * For MP systems, the firmware may only configure the L2 cache 946 * on the first CPU. In this case, assume that the other CPUs 947 * should use the same value for L2CR. 948 */ 949 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 950 l2cr_config = l2cr; 951 } 952 953 /* 954 * Configure L2 cache if not enabled. 955 */ 956 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 957 cpu_enable_l2cr(l2cr_config); 958 l2cr = mfspr(SPR_L2CR); 959 } 960 961 aprint_normal(","); 962 switch (vers) { 963 case MPC7447A: 964 case MPC7457: 965 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 966 return; 967 case MPC7448: 968 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 969 return; 970 default: 971 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 972 break; 973 } 974 975 l3cr = mfspr(SPR_L3CR); 976 977 /* 978 * For MP systems, the firmware may only configure the L3 cache 979 * on the first CPU. In this case, assume that the other CPUs 980 * should use the same value for L3CR. 981 */ 982 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 983 l3cr_config = l3cr; 984 } 985 986 /* 987 * Configure L3 cache if not enabled. 988 */ 989 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 990 cpu_enable_l3cr(l3cr_config); 991 l3cr = mfspr(SPR_L3CR); 992 } 993 994 if (l3cr & L3CR_L3E) { 995 aprint_normal(","); 996 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 997 } 998 } 999 1000 void 1001 cpu_probe_speed(struct cpu_info *ci) 1002 { 1003 uint64_t cps; 1004 1005 mtspr(SPR_MMCR0, MMCR0_FC); 1006 mtspr(SPR_PMC1, 0); 1007 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1008 delay(100000); 1009 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1010 1011 mtspr(SPR_MMCR0, MMCR0_FC); 1012 1013 ci->ci_khz = cps / 1000; 1014 } 1015 1016 #if NSYSMON_ENVSYS > 0 1017 void 1018 cpu_tau_setup(struct cpu_info *ci) 1019 { 1020 struct sysmon_envsys *sme; 1021 int error, therm_delay; 1022 1023 mtspr(SPR_THRM1, SPR_THRM_VALID); 1024 mtspr(SPR_THRM2, 0); 1025 1026 /* 1027 * we need to figure out how much 20+us in units of CPU clock cycles 1028 * are 1029 */ 1030 1031 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1032 1033 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1034 1035 sme = sysmon_envsys_create(); 1036 1037 sensor.units = ENVSYS_STEMP; 1038 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1039 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1040 sysmon_envsys_destroy(sme); 1041 return; 1042 } 1043 1044 sme->sme_name = ci->ci_dev->dv_xname; 1045 sme->sme_cookie = ci; 1046 sme->sme_refresh = cpu_tau_refresh; 1047 1048 if ((error = sysmon_envsys_register(sme)) != 0) { 1049 aprint_error("%s: unable to register with sysmon (%d)\n", 1050 ci->ci_dev->dv_xname, error); 1051 sysmon_envsys_destroy(sme); 1052 } 1053 } 1054 1055 1056 /* Find the temperature of the CPU. */ 1057 void 1058 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1059 { 1060 int i, threshold, count; 1061 1062 threshold = 64; /* Half of the 7-bit sensor range */ 1063 1064 /* Successive-approximation code adapted from Motorola 1065 * application note AN1800/D, "Programming the Thermal Assist 1066 * Unit in the MPC750 Microprocessor". 1067 */ 1068 for (i = 5; i >= 0 ; i--) { 1069 mtspr(SPR_THRM1, 1070 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1071 count = 0; 1072 while ((count < 100000) && 1073 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1074 count++; 1075 delay(1); 1076 } 1077 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1078 /* The interrupt bit was set, meaning the 1079 * temperature was above the threshold 1080 */ 1081 threshold += 1 << i; 1082 } else { 1083 /* Temperature was below the threshold */ 1084 threshold -= 1 << i; 1085 } 1086 1087 } 1088 threshold += 2; 1089 1090 /* Convert the temperature in degrees C to microkelvin */ 1091 edata->value_cur = (threshold * 1000000) + 273150000; 1092 edata->state = ENVSYS_SVALID; 1093 } 1094 #endif /* NSYSMON_ENVSYS > 0 */ 1095 1096 #ifdef MULTIPROCESSOR 1097 extern volatile u_int cpu_spinstart_ack; 1098 1099 int 1100 cpu_spinup(struct device *self, struct cpu_info *ci) 1101 { 1102 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1103 struct pglist mlist; 1104 int i, error, pvr, vers; 1105 char *cp, *hp; 1106 1107 pvr = mfpvr(); 1108 vers = pvr >> 16; 1109 KASSERT(ci != curcpu()); 1110 1111 /* 1112 * Allocate some contiguous pages for the intteup PCB and stack 1113 * from the lowest 256MB (because bat0 always maps it va == pa). 1114 * Must be 16 byte aligned. 1115 */ 1116 error = uvm_pglistalloc(INTSTK, 0x10000, 0x10000000, 16, 0, 1117 &mlist, 1, 1); 1118 if (error) { 1119 aprint_error(": unable to allocate idle stack\n"); 1120 return -1; 1121 } 1122 1123 KASSERT(ci != &cpu_info[0]); 1124 1125 cp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1126 memset(cp, 0, INTSTK); 1127 1128 ci->ci_intstk = cp; 1129 1130 /* Now allocate a hatch stack */ 1131 error = uvm_pglistalloc(0x1000, 0x10000, 0x10000000, 16, 0, 1132 &mlist, 1, 1); 1133 if (error) { 1134 aprint_error(": unable to allocate hatch stack\n"); 1135 return -1; 1136 } 1137 1138 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1139 memset(hp, 0, 0x1000); 1140 1141 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1142 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1143 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1144 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1145 1146 cpu_hatch_data = h; 1147 h->running = 0; 1148 h->self = self; 1149 h->ci = ci; 1150 h->pir = ci->ci_cpuid; 1151 1152 cpu_hatch_stack = (uint32_t)hp; 1153 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1154 1155 /* copy special registers */ 1156 1157 h->hid0 = mfspr(SPR_HID0); 1158 1159 __asm volatile ("mfsdr1 %0" : "=r"(h->sdr1)); 1160 for (i = 0; i < 16; i++) { 1161 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1162 "r"(i << ADDR_SR_SHFT)); 1163 } 1164 if (oeacpufeat & OEACPU_64) 1165 h->asr = mfspr(SPR_ASR); 1166 else 1167 h->asr = 0; 1168 1169 /* copy the bat regs */ 1170 __asm volatile ("mfibatu %0,0" : "=r"(h->batu[0])); 1171 __asm volatile ("mfibatl %0,0" : "=r"(h->batl[0])); 1172 __asm volatile ("mfibatu %0,1" : "=r"(h->batu[1])); 1173 __asm volatile ("mfibatl %0,1" : "=r"(h->batl[1])); 1174 __asm volatile ("mfibatu %0,2" : "=r"(h->batu[2])); 1175 __asm volatile ("mfibatl %0,2" : "=r"(h->batl[2])); 1176 __asm volatile ("mfibatu %0,3" : "=r"(h->batu[3])); 1177 __asm volatile ("mfibatl %0,3" : "=r"(h->batl[3])); 1178 __asm volatile ("sync; isync"); 1179 1180 if (md_setup_trampoline(h, ci) == -1) 1181 return -1; 1182 md_presync_timebase(h); 1183 md_start_timebase(h); 1184 1185 /* wait for secondary printf */ 1186 1187 delay(200000); 1188 1189 if (h->running < 1) { 1190 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1191 ci->ci_cpuid, cpu_spinstart_ack); 1192 Debugger(); 1193 return -1; 1194 } 1195 1196 /* Register IPI Interrupt */ 1197 if (ipiops.ppc_establish_ipi) 1198 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1199 1200 return 0; 1201 } 1202 1203 static volatile int start_secondary_cpu; 1204 extern void tlbia(void); 1205 1206 register_t 1207 cpu_hatch(void) 1208 { 1209 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1210 struct cpu_info * const ci = h->ci; 1211 u_int msr; 1212 int i; 1213 1214 /* Initialize timebase. */ 1215 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1216 1217 /* 1218 * Set PIR (Processor Identification Register). i.e. whoami 1219 * Note that PIR is read-only on some CPU versions, so we write to it 1220 * only if it has a different value than we need. 1221 */ 1222 1223 msr = mfspr(SPR_PIR); 1224 if (msr != h->pir) 1225 mtspr(SPR_PIR, h->pir); 1226 1227 __asm volatile ("mtsprg 0,%0" :: "r"(ci)); 1228 cpu_spinstart_ack = 0; 1229 1230 /* Initialize MMU. */ 1231 __asm ("mtibatu 0,%0" :: "r"(h->batu[0])); 1232 __asm ("mtibatl 0,%0" :: "r"(h->batl[0])); 1233 __asm ("mtibatu 1,%0" :: "r"(h->batu[1])); 1234 __asm ("mtibatl 1,%0" :: "r"(h->batl[1])); 1235 __asm ("mtibatu 2,%0" :: "r"(h->batu[2])); 1236 __asm ("mtibatl 2,%0" :: "r"(h->batl[2])); 1237 __asm ("mtibatu 3,%0" :: "r"(h->batu[3])); 1238 __asm ("mtibatl 3,%0" :: "r"(h->batl[3])); 1239 1240 mtspr(SPR_HID0, h->hid0); 1241 1242 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1243 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1244 1245 __asm volatile ("sync"); 1246 for (i = 0; i < 16; i++) 1247 __asm ("mtsrin %0,%1" :: "r"(h->sr[i]), "r"(i << ADDR_SR_SHFT)); 1248 __asm volatile ("sync; isync"); 1249 1250 if (oeacpufeat & OEACPU_64) 1251 mtspr(SPR_ASR, h->asr); 1252 1253 cpu_spinstart_ack = 1; 1254 __asm ("ptesync"); 1255 __asm ("mtsdr1 %0" :: "r"(h->sdr1)); 1256 __asm volatile ("sync; isync"); 1257 1258 cpu_spinstart_ack = 5; 1259 for (i = 0; i < 16; i++) 1260 __asm ("mfsrin %0,%1" : "=r"(h->sr[i]) : 1261 "r"(i << ADDR_SR_SHFT)); 1262 1263 /* Enable I/D address translations. */ 1264 msr = mfmsr(); 1265 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1266 mtmsr(msr); 1267 __asm volatile ("sync; isync"); 1268 cpu_spinstart_ack = 2; 1269 1270 md_sync_timebase(h); 1271 1272 cpu_setup(h->self, ci); 1273 1274 h->running = 1; 1275 __asm volatile ("sync; isync"); 1276 1277 while (start_secondary_cpu == 0) 1278 ; 1279 1280 __asm volatile ("sync; isync"); 1281 1282 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1283 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1284 1285 md_setup_interrupts(); 1286 1287 ci->ci_ipending = 0; 1288 ci->ci_cpl = 0; 1289 1290 mtmsr(mfmsr() | PSL_EE); 1291 struct pcb * const idlepcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1292 return idlepcb->pcb_sp; 1293 } 1294 1295 void 1296 cpu_boot_secondary_processors() 1297 { 1298 start_secondary_cpu = 1; 1299 __asm volatile ("sync"); 1300 } 1301 1302 #endif /*MULTIPROCESSOR*/ 1303
Indexes created Thu Oct 02 07:10:07 GMT 2025