cpu_subr.c revision 1.6
1 /* $NetBSD: cpu_subr.c,v 1.6 2003/04/02 02:47:19 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include "opt_ppcparam.h" 37 #include "opt_multiprocessor.h" 38 #include "opt_altivec.h" 39 #include "sysmon_envsys.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/device.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <powerpc/oea/hid.h> 48 #include <powerpc/oea/hid_601.h> 49 #include <powerpc/spr.h> 50 51 #include <dev/sysmon/sysmonvar.h> 52 53 static void cpu_config_l2cr(int); 54 static void cpu_print_speed(void); 55 #if NSYSMON_ENVSYS > 0 56 static void cpu_tau_setup(struct cpu_info *); 57 static int cpu_tau_gtredata __P((struct sysmon_envsys *, 58 struct envsys_tre_data *)); 59 static int cpu_tau_streinfo __P((struct sysmon_envsys *, 60 struct envsys_basic_info *)); 61 #endif 62 63 int cpu; 64 int ncpus; 65 66 #ifdef MULTIPROCESSOR 67 struct cpu_info cpu_info[CPU_MAXNUM]; 68 #else 69 struct cpu_info cpu_info[1]; 70 #endif 71 72 int cpu_altivec; 73 char cpu_model[80]; 74 75 void 76 cpu_probe_cache(void) 77 { 78 u_int assoc, pvr, vers; 79 80 pvr = mfpvr(); 81 vers = pvr >> 16; 82 83 switch (vers) { 84 #define K *1024 85 case IBM750FX: 86 case MPC601: 87 case MPC750: 88 case MPC7450: 89 case MPC7455: 90 curcpu()->ci_ci.dcache_size = 32 K; 91 curcpu()->ci_ci.icache_size = 32 K; 92 assoc = 8; 93 break; 94 case MPC603: 95 curcpu()->ci_ci.dcache_size = 8 K; 96 curcpu()->ci_ci.icache_size = 8 K; 97 assoc = 2; 98 break; 99 case MPC603e: 100 case MPC603ev: 101 case MPC604: 102 case MPC8240: 103 case MPC8245: 104 curcpu()->ci_ci.dcache_size = 16 K; 105 curcpu()->ci_ci.icache_size = 16 K; 106 assoc = 4; 107 break; 108 case MPC604ev: 109 curcpu()->ci_ci.dcache_size = 32 K; 110 curcpu()->ci_ci.icache_size = 32 K; 111 assoc = 4; 112 break; 113 default: 114 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 115 curcpu()->ci_ci.icache_size = PAGE_SIZE; 116 assoc = 1; 117 #undef K 118 } 119 120 /* Presently common across all implementations. */ 121 curcpu()->ci_ci.dcache_line_size = CACHELINESIZE; 122 curcpu()->ci_ci.icache_line_size = CACHELINESIZE; 123 124 /* 125 * Possibly recolor. 126 */ 127 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 128 } 129 130 struct cpu_info * 131 cpu_attach_common(struct device *self, int id) 132 { 133 struct cpu_info *ci; 134 u_int pvr, vers; 135 136 ncpus++; 137 ci = &cpu_info[id]; 138 #ifndef MULTIPROCESSOR 139 /* 140 * If this isn't the primary CPU, print an error message 141 * and just bail out. 142 */ 143 if (id != 0) { 144 aprint_normal(": ID %d\n", id); 145 aprint_normal("%s: processor off-line; multiprocessor support " 146 "not present in kernel\n", self->dv_xname); 147 return (NULL); 148 } 149 #endif 150 151 ci->ci_cpuid = id; 152 ci->ci_intrdepth = -1; 153 ci->ci_dev = self; 154 155 pvr = mfpvr(); 156 vers = (pvr >> 16) & 0xffff; 157 158 switch (id) { 159 case 0: 160 /* load my cpu_number to PIR */ 161 switch (vers) { 162 case MPC601: 163 case MPC604: 164 case MPC604ev: 165 case MPC7400: 166 case MPC7410: 167 case MPC7450: 168 case MPC7455: 169 mtspr(SPR_PIR, id); 170 } 171 cpu_setup(self, ci); 172 break; 173 default: 174 if (id >= CPU_MAXNUM) { 175 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 176 panic("cpuattach"); 177 } 178 #ifndef MULTIPROCESSOR 179 aprint_normal(" not configured\n"); 180 return NULL; 181 #endif 182 } 183 return (ci); 184 } 185 186 void 187 cpu_setup(self, ci) 188 struct device *self; 189 struct cpu_info *ci; 190 { 191 u_int hid0, pvr, vers; 192 char *bitmask, hidbuf[128]; 193 char model[80]; 194 195 pvr = mfpvr(); 196 vers = (pvr >> 16) & 0xffff; 197 198 cpu_identify(model, sizeof(model)); 199 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 200 cpu_number() == 0 ? " (primary)" : ""); 201 202 hid0 = mfspr(SPR_HID0); 203 cpu_probe_cache(); 204 205 /* 206 * Configure power-saving mode. 207 */ 208 switch (vers) { 209 case MPC603: 210 case MPC603e: 211 case MPC603ev: 212 case MPC604ev: 213 case MPC750: 214 case IBM750FX: 215 case MPC7400: 216 case MPC7410: 217 case MPC8240: 218 case MPC8245: 219 /* Select DOZE mode. */ 220 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 221 hid0 |= HID0_DOZE | HID0_DPM; 222 powersave = 1; 223 break; 224 225 case MPC7455: 226 case MPC7450: 227 /* Enable the 7450 branch caches */ 228 hid0 |= HID0_SGE | HID0_BTIC; 229 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 230 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 231 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 232 hid0 &= ~HID0_BTIC; 233 /* Select NAP mode. */ 234 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 235 hid0 |= HID0_NAP | HID0_DPM; 236 powersave = 0; /* but don't use it */ 237 break; 238 239 default: 240 /* No power-saving mode is available. */ ; 241 } 242 243 #ifdef NAPMODE 244 switch (vers) { 245 case IBM750FX: 246 case MPC750: 247 case MPC7400: 248 /* Select NAP mode. */ 249 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 250 hid0 |= HID0_NAP; 251 break; 252 } 253 #endif 254 255 switch (vers) { 256 case IBM750FX: 257 case MPC750: 258 hid0 &= ~HID0_DBP; /* XXX correct? */ 259 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 260 break; 261 262 case MPC7400: 263 case MPC7410: 264 hid0 &= ~HID0_SPD; 265 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 266 hid0 |= HID0_EIEC; 267 break; 268 } 269 270 mtspr(SPR_HID0, hid0); 271 272 switch (vers) { 273 case MPC601: 274 bitmask = HID0_601_BITMASK; 275 break; 276 case MPC7450: 277 case MPC7455: 278 bitmask = HID0_7450_BITMASK; 279 break; 280 default: 281 bitmask = HID0_BITMASK; 282 break; 283 } 284 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 285 aprint_normal("%s: HID0 %s\n", self->dv_xname, hidbuf); 286 287 /* 288 * Display speed and cache configuration. 289 */ 290 if (vers == MPC750 || vers == MPC7400 || vers == IBM750FX || 291 vers == MPC7410 || vers == MPC7450 || vers == MPC7455) { 292 aprint_normal("%s", self->dv_xname); 293 cpu_print_speed(); 294 aprint_normal("%s", self->dv_xname); 295 cpu_config_l2cr(vers); 296 } 297 298 #if NSYSMON_ENVSYS > 0 299 /* 300 * Attach MPC750 temperature sensor to the envsys subsystem. 301 * XXX the 74xx series also has this sensor, but it is not 302 * XXX supported by Motorola and may return values that are off by 303 * XXX 35-55 degrees C. 304 */ 305 if (vers == MPC750 || vers == IBM750FX) 306 cpu_tau_setup(ci); 307 #endif 308 309 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 310 NULL, self->dv_xname, "clock"); 311 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 312 NULL, self->dv_xname, "soft clock"); 313 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 314 NULL, self->dv_xname, "soft net"); 315 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 316 NULL, self->dv_xname, "soft serial"); 317 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 318 NULL, self->dv_xname, "traps"); 319 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 320 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 321 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 322 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 323 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 324 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 325 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 326 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 327 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 328 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 329 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 330 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 331 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 332 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 333 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 334 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 335 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 336 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 337 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 338 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 339 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 340 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 341 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 342 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 343 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 344 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 345 #ifdef ALTIVEC 346 if (cpu_altivec) { 347 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 348 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 349 } 350 #endif 351 } 352 353 struct cputab { 354 const char name[8]; 355 uint16_t version; 356 uint16_t revfmt; 357 }; 358 #define REVFMT_MAJMIN 1 /* %u.%u */ 359 #define REVFMT_HEX 2 /* 0x%04x */ 360 #define REVFMT_DEC 3 /* %u */ 361 static const struct cputab models[] = { 362 { "601", MPC601, REVFMT_DEC }, 363 { "602", MPC602, REVFMT_DEC }, 364 { "603", MPC603, REVFMT_MAJMIN }, 365 { "603e", MPC603e, REVFMT_MAJMIN }, 366 { "603ev", MPC603ev, REVFMT_MAJMIN }, 367 { "604", MPC604, REVFMT_MAJMIN }, 368 { "604ev", MPC604ev, REVFMT_MAJMIN }, 369 { "620", MPC620, REVFMT_HEX }, 370 { "750", MPC750, REVFMT_MAJMIN }, 371 { "750FX", IBM750FX, REVFMT_MAJMIN }, 372 { "7400", MPC7400, REVFMT_MAJMIN }, 373 { "7410", MPC7410, REVFMT_MAJMIN }, 374 { "7450", MPC7450, REVFMT_MAJMIN }, 375 { "7455", MPC7455, REVFMT_MAJMIN }, 376 { "8240", MPC8240, REVFMT_MAJMIN }, 377 { "", 0, REVFMT_HEX } 378 }; 379 380 void 381 cpu_identify(char *str, size_t len) 382 { 383 u_int pvr, maj, min; 384 uint16_t vers, rev, revfmt; 385 const struct cputab *cp; 386 const char *name; 387 size_t n; 388 389 pvr = mfpvr(); 390 vers = pvr >> 16; 391 rev = pvr; 392 switch (vers) { 393 case MPC7410: 394 min = (pvr >> 0) & 0xff; 395 maj = min <= 4 ? 1 : 2; 396 break; 397 default: 398 maj = (pvr >> 8) & 0xf; 399 min = (pvr >> 0) & 0xf; 400 } 401 402 for (cp = models; cp->name[0] != '\0'; cp++) { 403 if (cp->version == vers) 404 break; 405 } 406 407 if (str == NULL) { 408 str = cpu_model; 409 len = sizeof(cpu_model); 410 cpu = vers; 411 } 412 413 revfmt = cp->revfmt; 414 name = cp->name; 415 if (rev == MPC750 && pvr == 15) { 416 name = "755"; 417 revfmt = REVFMT_HEX; 418 } 419 420 if (cp->name[0] != '\0') { 421 n = snprintf(str, len, "%s (Revision ", cp->name); 422 } else { 423 n = snprintf(str, len, "Version %#x (Revision ", vers); 424 } 425 if (len > n) { 426 switch (revfmt) { 427 case REVFMT_MAJMIN: 428 snprintf(str + n, len - n, "%u.%u)", maj, min); 429 break; 430 case REVFMT_HEX: 431 snprintf(str + n, len - n, "0x%04x)", rev); 432 break; 433 case REVFMT_DEC: 434 snprintf(str + n, len - n, "%u)", rev); 435 break; 436 } 437 } 438 } 439 440 #ifdef L2CR_CONFIG 441 u_int l2cr_config = L2CR_CONFIG; 442 #else 443 u_int l2cr_config = 0; 444 #endif 445 446 #ifdef L3CR_CONFIG 447 u_int l3cr_config = L3CR_CONFIG; 448 #else 449 u_int l3cr_config = 0; 450 #endif 451 452 void 453 cpu_config_l2cr(int vers) 454 { 455 u_int l2cr, x, msr; 456 457 l2cr = mfspr(SPR_L2CR); 458 459 /* 460 * For MP systems, the firmware may only configure the L2 cache 461 * on the first CPU. In this case, assume that the other CPUs 462 * should use the same value for L2CR. 463 */ 464 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 465 l2cr_config = l2cr; 466 } 467 468 /* 469 * Configure L2 cache if not enabled. 470 */ 471 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 472 l2cr = l2cr_config; 473 474 /* Disable interrupts and set the cache config bits. */ 475 msr = mfmsr(); 476 mtmsr(msr & ~PSL_EE); 477 #ifdef ALTIVEC 478 if (cpu_altivec) 479 __asm __volatile("dssall"); 480 #endif 481 __asm __volatile("sync"); 482 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 483 __asm __volatile("sync"); 484 485 /* Wait for L2 clock to be stable (640 L2 clocks). */ 486 delay(100); 487 488 /* Invalidate all L2 contents. */ 489 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 490 do { 491 x = mfspr(SPR_L2CR); 492 } while (x & L2CR_L2IP); 493 494 /* Enable L2 cache. */ 495 l2cr |= L2CR_L2E; 496 mtspr(SPR_L2CR, l2cr); 497 mtmsr(msr); 498 } 499 500 if (l2cr & L2CR_L2E) { 501 if (vers == MPC7450 || vers == MPC7455) { 502 u_int l3cr; 503 504 aprint_normal(": 256KB L2 cache"); 505 506 l3cr = mfspr(SPR_L3CR); 507 508 /* 509 * Configure L3 cache if not enabled. 510 */ 511 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 512 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 513 514 /* 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and L3CLKEN */ 515 /* (also mask off reserved bits in case they were included in L3CR_CONFIG) */ 516 l3cr = l3cr_config & ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 517 mtspr(SPR_L3CR, l3cr); 518 519 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 520 l3cr |= 0x04000000; 521 mtspr(SPR_L3CR, l3cr); 522 523 /* 3: Set L3CLKEN to 1*/ 524 l3cr |= L3CR_L3CLKEN; 525 mtspr(SPR_L3CR, l3cr); 526 527 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 528 __asm __volatile("dssall;sync"); 529 /* L3 cache is already disabled, no need to clear L3E */ 530 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 531 do { 532 x = mfspr(SPR_L3CR); 533 } while (x & L3CR_L3I); 534 535 /* 6: Clear L3CLKEN to 0 */ 536 l3cr &= ~L3CR_L3CLKEN; 537 mtspr(SPR_L3CR, l3cr); 538 539 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 540 __asm __volatile("sync"); 541 delay(100); 542 543 /* 8: Set L3E and L3CLKEN */ 544 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 545 mtspr(SPR_L3CR, l3cr); 546 547 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 548 __asm __volatile("sync"); 549 delay(100); 550 } 551 552 if (l3cr & L3CR_L3E) { 553 aprint_normal(", %cMB L3 cache at ", 554 l3cr & L3CR_L3SIZ ? '2' : '1'); 555 switch (l3cr & L3CR_L3CLK) { 556 case L3CLK_20: 557 aprint_normal("2:1 ratio"); 558 break; 559 case L3CLK_25: 560 aprint_normal("2.5:1 ratio"); 561 break; 562 case L3CLK_30: 563 aprint_normal("3:1 ratio"); 564 break; 565 case L3CLK_35: 566 aprint_normal("3.5:1 ratio"); 567 break; 568 case L3CLK_40: 569 aprint_normal("4:1 ratio"); 570 break; 571 case L3CLK_50: 572 aprint_normal("5:1 ratio"); 573 break; 574 case L3CLK_60: 575 aprint_normal("6:1 ratio"); 576 break; 577 default: 578 aprint_normal("unknown ratio"); 579 break; 580 } 581 } 582 aprint_normal("\n"); 583 return; 584 } 585 if (vers == IBM750FX) { 586 aprint_normal(": 512KB L2 cache\n"); 587 return; 588 } 589 switch (l2cr & L2CR_L2SIZ) { 590 case L2SIZ_256K: 591 aprint_normal(": 256KB"); 592 break; 593 case L2SIZ_512K: 594 aprint_normal(": 512KB"); 595 break; 596 case L2SIZ_1M: 597 aprint_normal(": 1MB"); 598 break; 599 case 0: 600 if (vers == MPC7410) { 601 aprint_normal(": 2MB"); 602 break; 603 } 604 /* FALLTHROUGH */ 605 default: 606 aprint_normal(": unknown size"); 607 break; 608 } 609 if (l2cr & L2CR_L2WT) { 610 aprint_normal(" write-through"); 611 } else { 612 aprint_normal(" write-back"); 613 } 614 switch (l2cr & (L2CR_L2DO|L2CR_L2IO)) { 615 case L2CR_L2DO|L2CR_L2IO: 616 aprint_normal(" locked"); 617 break; 618 case L2CR_L2DO: 619 aprint_normal(" data-only"); 620 break; 621 case L2CR_L2IO: 622 aprint_normal(" instruction-only"); 623 break; 624 case 0: 625 break; 626 } 627 switch (l2cr & L2CR_L2RAM) { 628 case L2RAM_FLOWTHRU_BURST: 629 aprint_normal(" Flow-through synchronous burst SRAM"); 630 break; 631 case L2RAM_PIPELINE_BURST: 632 aprint_normal(" Pipelined synchronous burst SRAM"); 633 break; 634 case L2RAM_PIPELINE_LATE: 635 aprint_normal(" Pipelined synchronous late-write SRAM"); 636 break; 637 default: 638 aprint_normal(" unknown type"); 639 } 640 641 if (l2cr & L2CR_L2PE) 642 aprint_normal(" with parity"); 643 aprint_normal(" L2 cache"); 644 } else 645 aprint_normal(": L2 cache not enabled"); 646 647 aprint_normal("\n"); 648 } 649 650 void 651 cpu_print_speed(void) 652 { 653 uint64_t cps; 654 655 mtspr(SPR_MMCR0, SPR_MMCR0_FC); 656 mtspr(SPR_PMC1, 0); 657 mtspr(SPR_MMCR0, SPR_MMCR0_PMC1SEL(PMCN_CYCLES)); 658 delay(100000); 659 cps = (mfspr(SPR_PMC1) * 10) + 4999; 660 661 aprint_normal(": %lld.%02lld MHz\n", cps / 1000000, (cps / 10000) % 100); 662 } 663 664 #if NSYSMON_ENVSYS > 0 665 const struct envsys_range cpu_tau_ranges[] = { 666 { 0, 0, ENVSYS_STEMP} 667 }; 668 669 struct envsys_basic_info cpu_tau_info[] = { 670 { 0, ENVSYS_STEMP, "CPU temp", 0, 0, ENVSYS_FVALID} 671 }; 672 673 void 674 cpu_tau_setup(struct cpu_info *ci) 675 { 676 struct sysmon_envsys *sme; 677 int error; 678 679 sme = &ci->ci_sysmon; 680 sme->sme_nsensors = 1; 681 sme->sme_envsys_version = 1000; 682 sme->sme_ranges = cpu_tau_ranges; 683 sme->sme_sensor_info = cpu_tau_info; 684 sme->sme_sensor_data = &ci->ci_tau_info; 685 686 sme->sme_sensor_data->sensor = 0; 687 sme->sme_sensor_data->warnflags = ENVSYS_WARN_OK; 688 sme->sme_sensor_data->validflags = ENVSYS_FVALID|ENVSYS_FCURVALID; 689 sme->sme_cookie = ci; 690 sme->sme_gtredata = cpu_tau_gtredata; 691 sme->sme_streinfo = cpu_tau_streinfo; 692 693 if ((error = sysmon_envsys_register(sme)) != 0) 694 aprint_error("%s: unable to register with sysmon (%d)\n", 695 ci->ci_dev->dv_xname, error); 696 } 697 698 699 /* Find the temperature of the CPU. */ 700 int 701 cpu_tau_gtredata(sme, tred) 702 struct sysmon_envsys *sme; 703 struct envsys_tre_data *tred; 704 { 705 struct cpu_info *ci; 706 int i, threshold, count; 707 708 if (tred->sensor != 0) { 709 tred->validflags = 0; 710 return 0; 711 } 712 713 threshold = 64; /* Half of the 7-bit sensor range */ 714 mtspr(SPR_THRM1, 0); 715 mtspr(SPR_THRM2, 0); 716 /* XXX This counter is supposed to be "at least 20 microseonds, in 717 * XXX units of clock cycles". Since we don't have convenient 718 * XXX access to the CPU speed, set it to a conservative value, 719 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 720 * XXX the fastest G3 processor is 700MHz) . The cost is that 721 * XXX measuring the temperature takes a bit longer. 722 */ 723 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 724 725 /* Successive-approximation code adapted from Motorola 726 * application note AN1800/D, "Programming the Thermal Assist 727 * Unit in the MPC750 Microprocessor". 728 */ 729 for (i = 4; i >= 0 ; i--) { 730 mtspr(SPR_THRM1, 731 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 732 count = 0; 733 while ((count < 100) && 734 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 735 count++; 736 delay(1); 737 } 738 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 739 /* The interrupt bit was set, meaning the 740 * temperature was above the threshold 741 */ 742 threshold += 2 << i; 743 } else { 744 /* Temperature was below the threshold */ 745 threshold -= 2 << i; 746 } 747 } 748 threshold += 2; 749 750 ci = (struct cpu_info *)sme->sme_cookie; 751 /* Convert the temperature in degrees C to microkelvin */ 752 ci->ci_tau_info.cur.data_us = (threshold * 1000000) + 273150000; 753 754 *tred = ci->ci_tau_info; 755 756 return 0; 757 } 758 759 int 760 cpu_tau_streinfo(sme, binfo) 761 struct sysmon_envsys *sme; 762 struct envsys_basic_info *binfo; 763 { 764 765 /* There is nothing to set here. */ 766 return (EINVAL); 767 } 768 #endif /* NSYSMON_ENVSYS > 0 */ 769
Indexes created Mon Sep 22 13:09:51 GMT 2025