cpu_subr.c revision 1.73.6.3
1 /* $NetBSD: cpu_subr.c,v 1.73.6.3 2017/12/03 11:36:37 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.73.6.3 2017/12/03 11:36:37 jdolecek Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_ppccache.h" 41 #include "opt_multiprocessor.h" 42 #include "opt_altivec.h" 43 #include "sysmon_envsys.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/types.h> 49 #include <sys/lwp.h> 50 #include <sys/xcall.h> 51 52 #include <uvm/uvm.h> 53 54 #include <powerpc/pcb.h> 55 #include <powerpc/psl.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/hid.h> 58 #include <powerpc/oea/hid_601.h> 59 #include <powerpc/oea/spr.h> 60 #include <powerpc/oea/cpufeat.h> 61 62 #include <dev/sysmon/sysmonvar.h> 63 64 static void cpu_enable_l2cr(register_t); 65 static void cpu_enable_l3cr(register_t); 66 static void cpu_config_l2cr(int); 67 static void cpu_config_l3cr(int); 68 static void cpu_probe_speed(struct cpu_info *); 69 static void cpu_idlespin(void); 70 static void cpu_set_dfs_xcall(void *, void *); 71 #if NSYSMON_ENVSYS > 0 72 static void cpu_tau_setup(struct cpu_info *); 73 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 74 #endif 75 76 int cpu = -1; 77 int ncpus; 78 79 struct fmttab { 80 register_t fmt_mask; 81 register_t fmt_value; 82 const char *fmt_string; 83 }; 84 85 /* 86 * This should be one per CPU but since we only support it on 750 variants it 87 * doesn't realy matter since none of them supports SMP 88 */ 89 envsys_data_t sensor; 90 91 static const struct fmttab cpu_7450_l2cr_formats[] = { 92 { L2CR_L2E, 0, " disabled" }, 93 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 94 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 95 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 96 { L2CR_L2E, ~0, " 256KB L2 cache" }, 97 { L2CR_L2PE, 0, " no parity" }, 98 { L2CR_L2PE, ~0, " parity enabled" }, 99 { 0, 0, NULL } 100 }; 101 102 static const struct fmttab cpu_7448_l2cr_formats[] = { 103 { L2CR_L2E, 0, " disabled" }, 104 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 105 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 106 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 107 { L2CR_L2E, ~0, " 1MB L2 cache" }, 108 { L2CR_L2PE, 0, " no parity" }, 109 { L2CR_L2PE, ~0, " parity enabled" }, 110 { 0, 0, NULL } 111 }; 112 113 static const struct fmttab cpu_7457_l2cr_formats[] = { 114 { L2CR_L2E, 0, " disabled" }, 115 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 116 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 117 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 118 { L2CR_L2E, ~0, " 512KB L2 cache" }, 119 { L2CR_L2PE, 0, " no parity" }, 120 { L2CR_L2PE, ~0, " parity enabled" }, 121 { 0, 0, NULL } 122 }; 123 124 static const struct fmttab cpu_7450_l3cr_formats[] = { 125 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 126 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 127 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 128 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 129 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 130 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 131 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 132 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 133 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 134 { L3CR_L3SIZ, ~0, " L3 cache" }, 135 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 136 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 137 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 138 { L3CR_L3CLK, ~0, " at" }, 139 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 140 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 141 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 142 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 143 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 144 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 145 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 146 { L3CR_L3CLK, ~0, " ratio" }, 147 { 0, 0, NULL }, 148 }; 149 150 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 151 { L2CR_L2E, 0, " disabled" }, 152 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 153 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 154 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 155 { 0, ~0, " 512KB" }, 156 { L2CR_L2WT, L2CR_L2WT, " WT" }, 157 { L2CR_L2WT, 0, " WB" }, 158 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 159 { 0, ~0, " L2 cache" }, 160 { 0, 0, NULL } 161 }; 162 163 static const struct fmttab cpu_l2cr_formats[] = { 164 { L2CR_L2E, 0, " disabled" }, 165 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 166 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 167 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 168 { L2CR_L2PE, L2CR_L2PE, " parity" }, 169 { L2CR_L2PE, 0, " no-parity" }, 170 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 171 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 172 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 173 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 174 { L2CR_L2WT, L2CR_L2WT, " WT" }, 175 { L2CR_L2WT, 0, " WB" }, 176 { L2CR_L2E, ~0, " L2 cache" }, 177 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 178 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 179 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 180 { L2CR_L2CLK, ~0, " at" }, 181 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 182 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 183 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 184 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 185 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 186 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 187 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 188 { L2CR_L2CLK, ~0, " ratio" }, 189 { 0, 0, NULL } 190 }; 191 192 static void cpu_fmttab_print(const struct fmttab *, register_t); 193 194 struct cputab { 195 const char name[8]; 196 uint16_t version; 197 uint16_t revfmt; 198 }; 199 #define REVFMT_MAJMIN 1 /* %u.%u */ 200 #define REVFMT_HEX 2 /* 0x%04x */ 201 #define REVFMT_DEC 3 /* %u */ 202 static const struct cputab models[] = { 203 { "601", MPC601, REVFMT_DEC }, 204 { "602", MPC602, REVFMT_DEC }, 205 { "603", MPC603, REVFMT_MAJMIN }, 206 { "603e", MPC603e, REVFMT_MAJMIN }, 207 { "603ev", MPC603ev, REVFMT_MAJMIN }, 208 { "G2", MPCG2, REVFMT_MAJMIN }, 209 { "604", MPC604, REVFMT_MAJMIN }, 210 { "604e", MPC604e, REVFMT_MAJMIN }, 211 { "604ev", MPC604ev, REVFMT_MAJMIN }, 212 { "620", MPC620, REVFMT_HEX }, 213 { "750", MPC750, REVFMT_MAJMIN }, 214 { "750FX", IBM750FX, REVFMT_MAJMIN }, 215 { "750GX", IBM750GX, REVFMT_MAJMIN }, 216 { "7400", MPC7400, REVFMT_MAJMIN }, 217 { "7410", MPC7410, REVFMT_MAJMIN }, 218 { "7450", MPC7450, REVFMT_MAJMIN }, 219 { "7455", MPC7455, REVFMT_MAJMIN }, 220 { "7457", MPC7457, REVFMT_MAJMIN }, 221 { "7447A", MPC7447A, REVFMT_MAJMIN }, 222 { "7448", MPC7448, REVFMT_MAJMIN }, 223 { "8240", MPC8240, REVFMT_MAJMIN }, 224 { "8245", MPC8245, REVFMT_MAJMIN }, 225 { "970", IBM970, REVFMT_MAJMIN }, 226 { "970FX", IBM970FX, REVFMT_MAJMIN }, 227 { "970MP", IBM970MP, REVFMT_MAJMIN }, 228 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 229 { "", 0, REVFMT_HEX } 230 }; 231 232 #ifdef MULTIPROCESSOR 233 struct cpu_info cpu_info[CPU_MAXNUM] = { 234 [0] = { 235 .ci_curlwp = &lwp0, 236 }, 237 }; 238 volatile struct cpu_hatch_data *cpu_hatch_data; 239 volatile int cpu_hatch_stack; 240 #define HATCH_STACK_SIZE 0x1000 241 extern int ticks_per_intr; 242 #include <powerpc/oea/bat.h> 243 #include <powerpc/pic/picvar.h> 244 #include <powerpc/pic/ipivar.h> 245 extern struct bat battable[]; 246 #else 247 struct cpu_info cpu_info[1] = { 248 [0] = { 249 .ci_curlwp = &lwp0, 250 }, 251 }; 252 #endif /*MULTIPROCESSOR*/ 253 254 int cpu_altivec; 255 register_t cpu_psluserset; 256 register_t cpu_pslusermod; 257 register_t cpu_pslusermask = 0xffff; 258 259 /* This is to be called from locore.S, and nowhere else. */ 260 261 void 262 cpu_model_init(void) 263 { 264 u_int pvr, vers; 265 266 pvr = mfpvr(); 267 vers = pvr >> 16; 268 269 oeacpufeat = 0; 270 271 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 272 vers == IBMCELL || vers == IBMPOWER6P5) { 273 oeacpufeat |= OEACPU_64; 274 oeacpufeat |= OEACPU_64_BRIDGE; 275 oeacpufeat |= OEACPU_NOBAT; 276 277 } else if (vers == MPC601) { 278 oeacpufeat |= OEACPU_601; 279 280 } else if (MPC745X_P(vers)) { 281 register_t hid1 = mfspr(SPR_HID1); 282 283 if (vers != MPC7450) { 284 register_t hid0 = mfspr(SPR_HID0); 285 286 /* Enable more SPRG registers */ 287 oeacpufeat |= OEACPU_HIGHSPRG; 288 289 /* Enable more BAT registers */ 290 oeacpufeat |= OEACPU_HIGHBAT; 291 hid0 |= HID0_HIGH_BAT_EN; 292 293 /* Enable larger BAT registers */ 294 oeacpufeat |= OEACPU_XBSEN; 295 hid0 |= HID0_XBSEN; 296 297 mtspr(SPR_HID0, hid0); 298 __asm volatile("sync;isync"); 299 } 300 301 /* Enable address broadcasting for MP systems */ 302 hid1 |= HID1_SYNCBE | HID1_ABE; 303 304 mtspr(SPR_HID1, hid1); 305 __asm volatile("sync;isync"); 306 307 } else if (vers == IBM750FX || vers == IBM750GX) { 308 oeacpufeat |= OEACPU_HIGHBAT; 309 } 310 } 311 312 void 313 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 314 { 315 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 316 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 317 (data & fmt->fmt_mask) == fmt->fmt_value) 318 aprint_normal("%s", fmt->fmt_string); 319 } 320 } 321 322 void 323 cpu_idlespin(void) 324 { 325 register_t msr; 326 327 if (powersave <= 0) 328 return; 329 330 __asm volatile( 331 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 332 "dssall;" 333 #endif 334 "sync;" 335 "mfmsr %0;" 336 "oris %0,%0,%1@h;" /* enter power saving mode */ 337 "mtmsr %0;" 338 "isync;" 339 : "=r"(msr) 340 : "J"(PSL_POW)); 341 } 342 343 void 344 cpu_probe_cache(void) 345 { 346 u_int assoc, pvr, vers; 347 348 pvr = mfpvr(); 349 vers = pvr >> 16; 350 351 352 /* Presently common across almost all implementations. */ 353 curcpu()->ci_ci.dcache_line_size = 32; 354 curcpu()->ci_ci.icache_line_size = 32; 355 356 357 switch (vers) { 358 #define K *1024 359 case IBM750FX: 360 case IBM750GX: 361 case MPC601: 362 case MPC750: 363 case MPC7400: 364 case MPC7447A: 365 case MPC7448: 366 case MPC7450: 367 case MPC7455: 368 case MPC7457: 369 curcpu()->ci_ci.dcache_size = 32 K; 370 curcpu()->ci_ci.icache_size = 32 K; 371 assoc = 8; 372 break; 373 case MPC603: 374 curcpu()->ci_ci.dcache_size = 8 K; 375 curcpu()->ci_ci.icache_size = 8 K; 376 assoc = 2; 377 break; 378 case MPC603e: 379 case MPC603ev: 380 case MPC604: 381 case MPC8240: 382 case MPC8245: 383 case MPCG2: 384 curcpu()->ci_ci.dcache_size = 16 K; 385 curcpu()->ci_ci.icache_size = 16 K; 386 assoc = 4; 387 break; 388 case MPC604e: 389 case MPC604ev: 390 curcpu()->ci_ci.dcache_size = 32 K; 391 curcpu()->ci_ci.icache_size = 32 K; 392 assoc = 4; 393 break; 394 case IBMPOWER3II: 395 curcpu()->ci_ci.dcache_size = 64 K; 396 curcpu()->ci_ci.icache_size = 32 K; 397 curcpu()->ci_ci.dcache_line_size = 128; 398 curcpu()->ci_ci.icache_line_size = 128; 399 assoc = 128; /* not a typo */ 400 break; 401 case IBM970: 402 case IBM970FX: 403 case IBM970MP: 404 curcpu()->ci_ci.dcache_size = 32 K; 405 curcpu()->ci_ci.icache_size = 64 K; 406 curcpu()->ci_ci.dcache_line_size = 128; 407 curcpu()->ci_ci.icache_line_size = 128; 408 assoc = 2; 409 break; 410 411 default: 412 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 413 curcpu()->ci_ci.icache_size = PAGE_SIZE; 414 assoc = 1; 415 #undef K 416 } 417 418 /* 419 * Possibly recolor. 420 */ 421 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 422 } 423 424 struct cpu_info * 425 cpu_attach_common(device_t self, int id) 426 { 427 struct cpu_info *ci; 428 u_int pvr, vers; 429 430 ci = &cpu_info[id]; 431 #ifndef MULTIPROCESSOR 432 /* 433 * If this isn't the primary CPU, print an error message 434 * and just bail out. 435 */ 436 if (id != 0) { 437 aprint_naive("\n"); 438 aprint_normal(": ID %d\n", id); 439 aprint_normal_dev(self, 440 "processor off-line; " 441 "multiprocessor support not present in kernel\n"); 442 return (NULL); 443 } 444 #endif 445 446 ci->ci_cpuid = id; 447 ci->ci_idepth = -1; 448 ci->ci_dev = self; 449 ci->ci_idlespin = cpu_idlespin; 450 451 pvr = mfpvr(); 452 vers = (pvr >> 16) & 0xffff; 453 454 switch (id) { 455 case 0: 456 /* load my cpu_number to PIR */ 457 switch (vers) { 458 case MPC601: 459 case MPC604: 460 case MPC604e: 461 case MPC604ev: 462 case MPC7400: 463 case MPC7410: 464 case MPC7447A: 465 case MPC7448: 466 case MPC7450: 467 case MPC7455: 468 case MPC7457: 469 mtspr(SPR_PIR, id); 470 } 471 cpu_setup(self, ci); 472 break; 473 default: 474 aprint_naive("\n"); 475 if (id >= CPU_MAXNUM) { 476 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 477 panic("cpuattach"); 478 } 479 #ifndef MULTIPROCESSOR 480 aprint_normal(" not configured\n"); 481 return NULL; 482 #else 483 mi_cpu_attach(ci); 484 break; 485 #endif 486 } 487 return (ci); 488 } 489 490 void 491 cpu_setup(device_t self, struct cpu_info *ci) 492 { 493 u_int pvr, vers; 494 const char * const xname = device_xname(self); 495 const char *bitmask; 496 char hidbuf[128]; 497 char model[80]; 498 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 499 char hidbuf_u[128]; 500 const char *bitmasku = NULL; 501 #endif 502 #if defined(PPC_OEA64_BRIDGE) 503 volatile uint64_t hid0; 504 #else 505 register_t hid0; 506 #endif 507 508 pvr = mfpvr(); 509 vers = (pvr >> 16) & 0xffff; 510 511 cpu_identify(model, sizeof(model)); 512 aprint_naive("\n"); 513 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 514 cpu_number() == 0 ? " (primary)" : ""); 515 516 /* set the cpu number */ 517 ci->ci_cpuid = cpu_number(); 518 #if defined(_ARCH_PPC64) 519 __asm volatile("mfspr %0,%1" : "=r"(hid0) : "K"(SPR_HID0)); 520 #else 521 hid0 = mfspr(SPR_HID0); 522 #endif 523 524 cpu_probe_cache(); 525 526 /* 527 * Configure power-saving mode. 528 */ 529 switch (vers) { 530 case MPC604: 531 case MPC604e: 532 case MPC604ev: 533 /* 534 * Do not have HID0 support settings, but can support 535 * MSR[POW] off 536 */ 537 powersave = 1; 538 break; 539 540 case MPC603: 541 case MPC603e: 542 case MPC603ev: 543 case MPC7400: 544 case MPC7410: 545 case MPC8240: 546 case MPC8245: 547 case MPCG2: 548 /* Select DOZE mode. */ 549 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 550 hid0 |= HID0_DOZE | HID0_DPM; 551 powersave = 1; 552 break; 553 554 case MPC750: 555 case IBM750FX: 556 case IBM750GX: 557 /* Select NAP mode. */ 558 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 559 hid0 |= HID0_NAP | HID0_DPM; 560 powersave = 1; 561 break; 562 563 case MPC7447A: 564 case MPC7448: 565 case MPC7457: 566 case MPC7455: 567 case MPC7450: 568 /* Enable the 7450 branch caches */ 569 hid0 |= HID0_SGE | HID0_BTIC; 570 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 571 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 572 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 573 hid0 &= ~HID0_BTIC; 574 /* Select NAP mode. */ 575 hid0 &= ~HID0_SLEEP; 576 hid0 |= HID0_NAP | HID0_DPM; 577 powersave = 1; 578 break; 579 580 case IBM970: 581 case IBM970FX: 582 case IBM970MP: 583 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 584 hid0 &= ~(HID0_64_DOZE | HID0_64_NAP | HID0_64_DEEPNAP); 585 hid0 |= HID0_64_DOZE | HID0_64_DPM | HID0_64_EX_TBEN | 586 HID0_64_TB_CTRL | HID0_64_EN_MCHK; 587 powersave = 1; 588 break; 589 #endif 590 case IBMPOWER3II: 591 default: 592 /* No power-saving mode is available. */ ; 593 } 594 595 #ifdef NAPMODE 596 switch (vers) { 597 case IBM750FX: 598 case IBM750GX: 599 case MPC750: 600 case MPC7400: 601 /* Select NAP mode. */ 602 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 603 hid0 |= HID0_NAP; 604 break; 605 } 606 #endif 607 608 switch (vers) { 609 case IBM750FX: 610 case IBM750GX: 611 case MPC750: 612 hid0 &= ~HID0_DBP; /* XXX correct? */ 613 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 614 break; 615 616 case MPC7400: 617 case MPC7410: 618 hid0 &= ~HID0_SPD; 619 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 620 hid0 |= HID0_EIEC; 621 break; 622 } 623 624 /* 625 * according to the 603e manual this is necessary for an external L2 626 * cache to work properly 627 */ 628 switch (vers) { 629 case MPC603e: 630 hid0 |= HID0_ABE; 631 } 632 633 #if defined(_ARCH_PPC64) 634 /* ppc970 needs extre goop around writes to HID0 */ 635 __asm volatile( "sync;" \ 636 "mtspr %0,%1;" \ 637 "mfspr %1,%0;" \ 638 "mfspr %1,%0;" \ 639 "mfspr %1,%0;" \ 640 "mfspr %1,%0;" \ 641 "mfspr %1,%0;" \ 642 "mfspr %1,%0;" \ 643 : : "K"(SPR_HID0), "r"(hid0)); 644 #else 645 mtspr(SPR_HID0, hid0); 646 #endif 647 __asm volatile("sync;isync"); 648 649 650 651 switch (vers) { 652 case MPC601: 653 bitmask = HID0_601_BITMASK; 654 break; 655 case MPC7447A: 656 case MPC7448: 657 case MPC7450: 658 case MPC7455: 659 case MPC7457: 660 bitmask = HID0_7450_BITMASK; 661 break; 662 case IBM970: 663 case IBM970FX: 664 case IBM970MP: 665 bitmask = HID0_970_BITMASK; 666 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 667 bitmasku = HID0_970_BITMASK_U; 668 #endif 669 break; 670 default: 671 bitmask = HID0_BITMASK; 672 break; 673 } 674 675 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 676 if (bitmasku != NULL) { 677 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0 & 0xffffffff); 678 snprintb(hidbuf_u, sizeof hidbuf_u, bitmasku, hid0 >> 32); 679 aprint_normal_dev(self, "HID0 %s %s, powersave: %d\n", 680 hidbuf_u, hidbuf, powersave); 681 } else 682 #endif 683 { 684 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 685 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", 686 hidbuf, powersave); 687 } 688 689 ci->ci_khz = 0; 690 691 /* 692 * Display speed and cache configuration. 693 */ 694 switch (vers) { 695 case MPC604: 696 case MPC604e: 697 case MPC604ev: 698 case MPC750: 699 case IBM750FX: 700 case IBM750GX: 701 case MPC7400: 702 case MPC7410: 703 case MPC7447A: 704 case MPC7448: 705 case MPC7450: 706 case MPC7455: 707 case MPC7457: 708 aprint_normal_dev(self, ""); 709 cpu_probe_speed(ci); 710 aprint_normal("%u.%02u MHz", 711 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 712 switch (vers) { 713 case MPC7450: /* 7441 does not have L3! */ 714 case MPC7455: /* 7445 does not have L3! */ 715 case MPC7457: /* 7447 does not have L3! */ 716 cpu_config_l3cr(vers); 717 break; 718 case IBM750FX: 719 case IBM750GX: 720 case MPC750: 721 case MPC7400: 722 case MPC7410: 723 case MPC7447A: 724 case MPC7448: 725 cpu_config_l2cr(pvr); 726 break; 727 default: 728 break; 729 } 730 aprint_normal("\n"); 731 break; 732 } 733 734 #if NSYSMON_ENVSYS > 0 735 /* 736 * Attach MPC750 temperature sensor to the envsys subsystem. 737 * XXX the 74xx series also has this sensor, but it is not 738 * XXX supported by Motorola and may return values that are off by 739 * XXX 35-55 degrees C. 740 */ 741 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 742 cpu_tau_setup(ci); 743 #endif 744 745 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 746 NULL, xname, "clock"); 747 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 748 NULL, xname, "traps"); 749 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 750 &ci->ci_ev_traps, xname, "kernel DSI traps"); 751 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 752 &ci->ci_ev_traps, xname, "user DSI traps"); 753 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 754 &ci->ci_ev_udsi, xname, "user DSI failures"); 755 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 756 &ci->ci_ev_traps, xname, "kernel ISI traps"); 757 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 758 &ci->ci_ev_traps, xname, "user ISI traps"); 759 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 760 &ci->ci_ev_isi, xname, "user ISI failures"); 761 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 762 &ci->ci_ev_traps, xname, "system call traps"); 763 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 764 &ci->ci_ev_traps, xname, "PGM traps"); 765 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 766 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 767 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 768 &ci->ci_ev_fpu, xname, "FPU context switches"); 769 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 770 &ci->ci_ev_traps, xname, "user alignment traps"); 771 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 772 &ci->ci_ev_ali, xname, "user alignment traps"); 773 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 774 &ci->ci_ev_umchk, xname, "user MCHK failures"); 775 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 776 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 777 #ifdef ALTIVEC 778 if (cpu_altivec) { 779 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 780 &ci->ci_ev_vec, xname, "AltiVec context switches"); 781 } 782 #endif 783 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 784 NULL, xname, "IPIs"); 785 } 786 787 /* 788 * According to a document labeled "PVR Register Settings": 789 ** For integrated microprocessors the PVR register inside the device 790 ** will identify the version of the microprocessor core. You must also 791 ** read the Device ID, PCI register 02, to identify the part and the 792 ** Revision ID, PCI register 08, to identify the revision of the 793 ** integrated microprocessor. 794 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 795 */ 796 797 void 798 cpu_identify(char *str, size_t len) 799 { 800 u_int pvr, major, minor; 801 uint16_t vers, rev, revfmt; 802 const struct cputab *cp; 803 size_t n; 804 805 pvr = mfpvr(); 806 vers = pvr >> 16; 807 rev = pvr; 808 809 switch (vers) { 810 case MPC7410: 811 minor = (pvr >> 0) & 0xff; 812 major = minor <= 4 ? 1 : 2; 813 break; 814 case MPCG2: /*XXX see note above */ 815 major = (pvr >> 4) & 0xf; 816 minor = (pvr >> 0) & 0xf; 817 break; 818 default: 819 major = (pvr >> 8) & 0xf; 820 minor = (pvr >> 0) & 0xf; 821 } 822 823 for (cp = models; cp->name[0] != '\0'; cp++) { 824 if (cp->version == vers) 825 break; 826 } 827 828 if (cpu == -1) 829 cpu = vers; 830 831 revfmt = cp->revfmt; 832 if (rev == MPC750 && pvr == 15) { 833 revfmt = REVFMT_HEX; 834 } 835 836 if (cp->name[0] != '\0') { 837 n = snprintf(str, len, "%s (Revision ", cp->name); 838 } else { 839 n = snprintf(str, len, "Version %#x (Revision ", vers); 840 } 841 if (len > n) { 842 switch (revfmt) { 843 case REVFMT_MAJMIN: 844 snprintf(str + n, len - n, "%u.%u)", major, minor); 845 break; 846 case REVFMT_HEX: 847 snprintf(str + n, len - n, "0x%04x)", rev); 848 break; 849 case REVFMT_DEC: 850 snprintf(str + n, len - n, "%u)", rev); 851 break; 852 } 853 } 854 } 855 856 #ifdef L2CR_CONFIG 857 u_int l2cr_config = L2CR_CONFIG; 858 #else 859 u_int l2cr_config = 0; 860 #endif 861 862 #ifdef L3CR_CONFIG 863 u_int l3cr_config = L3CR_CONFIG; 864 #else 865 u_int l3cr_config = 0; 866 #endif 867 868 void 869 cpu_enable_l2cr(register_t l2cr) 870 { 871 register_t msr, x; 872 uint16_t vers; 873 874 vers = mfpvr() >> 16; 875 876 /* Disable interrupts and set the cache config bits. */ 877 msr = mfmsr(); 878 mtmsr(msr & ~PSL_EE); 879 #ifdef ALTIVEC 880 if (cpu_altivec) 881 __asm volatile("dssall"); 882 #endif 883 __asm volatile("sync"); 884 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 885 __asm volatile("sync"); 886 887 /* Wait for L2 clock to be stable (640 L2 clocks). */ 888 delay(100); 889 890 /* Invalidate all L2 contents. */ 891 if (MPC745X_P(vers)) { 892 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 893 do { 894 x = mfspr(SPR_L2CR); 895 } while (x & L2CR_L2I); 896 } else { 897 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 898 do { 899 x = mfspr(SPR_L2CR); 900 } while (x & L2CR_L2IP); 901 } 902 /* Enable L2 cache. */ 903 l2cr |= L2CR_L2E; 904 mtspr(SPR_L2CR, l2cr); 905 mtmsr(msr); 906 } 907 908 void 909 cpu_enable_l3cr(register_t l3cr) 910 { 911 register_t x; 912 913 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 914 915 /* 916 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 917 * L3CLKEN. (also mask off reserved bits in case they were included 918 * in L3CR_CONFIG) 919 */ 920 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 921 mtspr(SPR_L3CR, l3cr); 922 923 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 924 l3cr |= 0x04000000; 925 mtspr(SPR_L3CR, l3cr); 926 927 /* 3: Set L3CLKEN to 1*/ 928 l3cr |= L3CR_L3CLKEN; 929 mtspr(SPR_L3CR, l3cr); 930 931 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 932 __asm volatile("dssall;sync"); 933 /* L3 cache is already disabled, no need to clear L3E */ 934 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 935 do { 936 x = mfspr(SPR_L3CR); 937 } while (x & L3CR_L3I); 938 939 /* 6: Clear L3CLKEN to 0 */ 940 l3cr &= ~L3CR_L3CLKEN; 941 mtspr(SPR_L3CR, l3cr); 942 943 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 944 __asm volatile("sync"); 945 delay(100); 946 947 /* 8: Set L3E and L3CLKEN */ 948 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 949 mtspr(SPR_L3CR, l3cr); 950 951 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 952 __asm volatile("sync"); 953 delay(100); 954 } 955 956 void 957 cpu_config_l2cr(int pvr) 958 { 959 register_t l2cr; 960 u_int vers = (pvr >> 16) & 0xffff; 961 962 l2cr = mfspr(SPR_L2CR); 963 964 /* 965 * For MP systems, the firmware may only configure the L2 cache 966 * on the first CPU. In this case, assume that the other CPUs 967 * should use the same value for L2CR. 968 */ 969 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 970 l2cr_config = l2cr; 971 } 972 973 /* 974 * Configure L2 cache if not enabled. 975 */ 976 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 977 cpu_enable_l2cr(l2cr_config); 978 l2cr = mfspr(SPR_L2CR); 979 } 980 981 if ((l2cr & L2CR_L2E) == 0) { 982 aprint_normal(" L2 cache present but not enabled "); 983 return; 984 } 985 aprint_normal(","); 986 987 switch (vers) { 988 case IBM750FX: 989 case IBM750GX: 990 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 991 break; 992 case MPC750: 993 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 994 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 995 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 996 else 997 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 998 break; 999 case MPC7447A: 1000 case MPC7457: 1001 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1002 return; 1003 case MPC7448: 1004 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1005 return; 1006 case MPC7450: 1007 case MPC7455: 1008 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1009 break; 1010 default: 1011 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1012 break; 1013 } 1014 } 1015 1016 void 1017 cpu_config_l3cr(int vers) 1018 { 1019 register_t l2cr; 1020 register_t l3cr; 1021 1022 l2cr = mfspr(SPR_L2CR); 1023 1024 /* 1025 * For MP systems, the firmware may only configure the L2 cache 1026 * on the first CPU. In this case, assume that the other CPUs 1027 * should use the same value for L2CR. 1028 */ 1029 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 1030 l2cr_config = l2cr; 1031 } 1032 1033 /* 1034 * Configure L2 cache if not enabled. 1035 */ 1036 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1037 cpu_enable_l2cr(l2cr_config); 1038 l2cr = mfspr(SPR_L2CR); 1039 } 1040 1041 aprint_normal(","); 1042 switch (vers) { 1043 case MPC7447A: 1044 case MPC7457: 1045 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1046 return; 1047 case MPC7448: 1048 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1049 return; 1050 default: 1051 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1052 break; 1053 } 1054 1055 l3cr = mfspr(SPR_L3CR); 1056 1057 /* 1058 * For MP systems, the firmware may only configure the L3 cache 1059 * on the first CPU. In this case, assume that the other CPUs 1060 * should use the same value for L3CR. 1061 */ 1062 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 1063 l3cr_config = l3cr; 1064 } 1065 1066 /* 1067 * Configure L3 cache if not enabled. 1068 */ 1069 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 1070 cpu_enable_l3cr(l3cr_config); 1071 l3cr = mfspr(SPR_L3CR); 1072 } 1073 1074 if (l3cr & L3CR_L3E) { 1075 aprint_normal(","); 1076 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1077 } 1078 } 1079 1080 void 1081 cpu_probe_speed(struct cpu_info *ci) 1082 { 1083 uint64_t cps; 1084 1085 mtspr(SPR_MMCR0, MMCR0_FC); 1086 mtspr(SPR_PMC1, 0); 1087 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1088 delay(100000); 1089 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1090 1091 mtspr(SPR_MMCR0, MMCR0_FC); 1092 1093 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1094 } 1095 1096 /* 1097 * Read the Dynamic Frequency Switching state and return a divisor for 1098 * the maximum frequency. 1099 */ 1100 int 1101 cpu_get_dfs(void) 1102 { 1103 u_int pvr, vers; 1104 1105 pvr = mfpvr(); 1106 vers = pvr >> 16; 1107 1108 switch (vers) { 1109 case MPC7448: 1110 if (mfspr(SPR_HID1) & HID1_DFS4) 1111 return 4; 1112 case MPC7447A: 1113 if (mfspr(SPR_HID1) & HID1_DFS2) 1114 return 2; 1115 } 1116 return 1; 1117 } 1118 1119 /* 1120 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1121 */ 1122 void 1123 cpu_set_dfs(int div) 1124 { 1125 uint64_t where; 1126 u_int dfs_mask, pvr, vers; 1127 1128 pvr = mfpvr(); 1129 vers = pvr >> 16; 1130 dfs_mask = 0; 1131 1132 switch (vers) { 1133 case MPC7448: 1134 dfs_mask |= HID1_DFS4; 1135 case MPC7447A: 1136 dfs_mask |= HID1_DFS2; 1137 break; 1138 default: 1139 printf("cpu_set_dfs: DFS not supported\n"); 1140 return; 1141 1142 } 1143 1144 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1145 xc_wait(where); 1146 } 1147 1148 static void 1149 cpu_set_dfs_xcall(void *arg1, void *arg2) 1150 { 1151 u_int dfs_mask, hid1, old_hid1; 1152 int *divisor, s; 1153 1154 divisor = arg1; 1155 dfs_mask = *(u_int *)arg2; 1156 1157 s = splhigh(); 1158 hid1 = old_hid1 = mfspr(SPR_HID1); 1159 1160 switch (*divisor) { 1161 case 1: 1162 hid1 &= ~dfs_mask; 1163 break; 1164 case 2: 1165 hid1 &= ~(dfs_mask & HID1_DFS4); 1166 hid1 |= dfs_mask & HID1_DFS2; 1167 break; 1168 case 4: 1169 hid1 &= ~(dfs_mask & HID1_DFS2); 1170 hid1 |= dfs_mask & HID1_DFS4; 1171 break; 1172 } 1173 1174 if (hid1 != old_hid1) { 1175 __asm volatile("sync"); 1176 mtspr(SPR_HID1, hid1); 1177 __asm volatile("sync;isync"); 1178 } 1179 1180 splx(s); 1181 } 1182 1183 #if NSYSMON_ENVSYS > 0 1184 void 1185 cpu_tau_setup(struct cpu_info *ci) 1186 { 1187 struct sysmon_envsys *sme; 1188 int error, therm_delay; 1189 1190 mtspr(SPR_THRM1, SPR_THRM_VALID); 1191 mtspr(SPR_THRM2, 0); 1192 1193 /* 1194 * we need to figure out how much 20+us in units of CPU clock cycles 1195 * are 1196 */ 1197 1198 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1199 1200 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1201 1202 sme = sysmon_envsys_create(); 1203 1204 sensor.units = ENVSYS_STEMP; 1205 sensor.state = ENVSYS_SINVALID; 1206 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1207 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1208 sysmon_envsys_destroy(sme); 1209 return; 1210 } 1211 1212 sme->sme_name = device_xname(ci->ci_dev); 1213 sme->sme_cookie = ci; 1214 sme->sme_refresh = cpu_tau_refresh; 1215 1216 if ((error = sysmon_envsys_register(sme)) != 0) { 1217 aprint_error_dev(ci->ci_dev, 1218 " unable to register with sysmon (%d)\n", error); 1219 sysmon_envsys_destroy(sme); 1220 } 1221 } 1222 1223 /* Find the temperature of the CPU. */ 1224 void 1225 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1226 { 1227 int i, threshold, count; 1228 1229 threshold = 64; /* Half of the 7-bit sensor range */ 1230 1231 /* Successive-approximation code adapted from Motorola 1232 * application note AN1800/D, "Programming the Thermal Assist 1233 * Unit in the MPC750 Microprocessor". 1234 */ 1235 for (i = 5; i >= 0 ; i--) { 1236 mtspr(SPR_THRM1, 1237 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1238 count = 0; 1239 while ((count < 100000) && 1240 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1241 count++; 1242 delay(1); 1243 } 1244 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1245 /* The interrupt bit was set, meaning the 1246 * temperature was above the threshold 1247 */ 1248 threshold += 1 << i; 1249 } else { 1250 /* Temperature was below the threshold */ 1251 threshold -= 1 << i; 1252 } 1253 } 1254 threshold += 2; 1255 1256 /* Convert the temperature in degrees C to microkelvin */ 1257 edata->value_cur = (threshold * 1000000) + 273150000; 1258 edata->state = ENVSYS_SVALID; 1259 } 1260 #endif /* NSYSMON_ENVSYS > 0 */ 1261 1262 #ifdef MULTIPROCESSOR 1263 volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum; 1264 1265 int 1266 cpu_spinup(device_t self, struct cpu_info *ci) 1267 { 1268 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1269 struct pglist mlist; 1270 int i, error; 1271 char *hp; 1272 1273 KASSERT(ci != curcpu()); 1274 1275 /* Now allocate a hatch stack */ 1276 error = uvm_pglistalloc(HATCH_STACK_SIZE, 0x10000, 0x10000000, 16, 0, 1277 &mlist, 1, 1); 1278 if (error) { 1279 aprint_error(": unable to allocate hatch stack\n"); 1280 return -1; 1281 } 1282 1283 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1284 memset(hp, 0, HATCH_STACK_SIZE); 1285 1286 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1287 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1288 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1289 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1290 1291 cpu_hatch_data = h; 1292 h->hatch_running = 0; 1293 h->hatch_self = self; 1294 h->hatch_ci = ci; 1295 h->hatch_pir = ci->ci_cpuid; 1296 1297 cpu_hatch_stack = (uint32_t)hp + HATCH_STACK_SIZE - CALLFRAMELEN; 1298 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1299 1300 /* copy special registers */ 1301 1302 h->hatch_hid0 = mfspr(SPR_HID0); 1303 1304 __asm volatile ("mfsdr1 %0" : "=r"(h->hatch_sdr1)); 1305 for (i = 0; i < 16; i++) { 1306 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1307 "r"(i << ADDR_SR_SHFT)); 1308 } 1309 if (oeacpufeat & OEACPU_64) 1310 h->hatch_asr = mfspr(SPR_ASR); 1311 else 1312 h->hatch_asr = 0; 1313 1314 /* copy the bat regs */ 1315 __asm volatile ("mfibatu %0,0" : "=r"(h->hatch_ibatu[0])); 1316 __asm volatile ("mfibatl %0,0" : "=r"(h->hatch_ibatl[0])); 1317 __asm volatile ("mfibatu %0,1" : "=r"(h->hatch_ibatu[1])); 1318 __asm volatile ("mfibatl %0,1" : "=r"(h->hatch_ibatl[1])); 1319 __asm volatile ("mfibatu %0,2" : "=r"(h->hatch_ibatu[2])); 1320 __asm volatile ("mfibatl %0,2" : "=r"(h->hatch_ibatl[2])); 1321 __asm volatile ("mfibatu %0,3" : "=r"(h->hatch_ibatu[3])); 1322 __asm volatile ("mfibatl %0,3" : "=r"(h->hatch_ibatl[3])); 1323 __asm volatile ("mfdbatu %0,0" : "=r"(h->hatch_dbatu[0])); 1324 __asm volatile ("mfdbatl %0,0" : "=r"(h->hatch_dbatl[0])); 1325 __asm volatile ("mfdbatu %0,1" : "=r"(h->hatch_dbatu[1])); 1326 __asm volatile ("mfdbatl %0,1" : "=r"(h->hatch_dbatl[1])); 1327 __asm volatile ("mfdbatu %0,2" : "=r"(h->hatch_dbatu[2])); 1328 __asm volatile ("mfdbatl %0,2" : "=r"(h->hatch_dbatl[2])); 1329 __asm volatile ("mfdbatu %0,3" : "=r"(h->hatch_dbatu[3])); 1330 __asm volatile ("mfdbatl %0,3" : "=r"(h->hatch_dbatl[3])); 1331 __asm volatile ("sync; isync"); 1332 1333 if (md_setup_trampoline(h, ci) == -1) 1334 return -1; 1335 md_presync_timebase(h); 1336 md_start_timebase(h); 1337 1338 /* wait for secondary printf */ 1339 1340 delay(200000); 1341 1342 #ifdef CACHE_PROTO_MEI 1343 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1344 __asm volatile ("sync; isync"); 1345 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1346 __asm volatile ("sync; isync"); 1347 #endif 1348 if (h->hatch_running < 1) { 1349 #ifdef CACHE_PROTO_MEI 1350 __asm volatile ("dcbi 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1351 __asm volatile ("sync; isync"); 1352 __asm volatile ("dcbst 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1353 __asm volatile ("sync; isync"); 1354 #endif 1355 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1356 ci->ci_cpuid, cpu_spinstart_ack); 1357 Debugger(); 1358 return -1; 1359 } 1360 1361 /* Register IPI Interrupt */ 1362 if (ipiops.ppc_establish_ipi) 1363 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 1364 1365 return 0; 1366 } 1367 1368 static volatile int start_secondary_cpu; 1369 1370 register_t 1371 cpu_hatch(void) 1372 { 1373 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1374 struct cpu_info * const ci = h->hatch_ci; 1375 struct pcb *pcb; 1376 u_int msr; 1377 int i; 1378 1379 /* Initialize timebase. */ 1380 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1381 1382 /* 1383 * Set PIR (Processor Identification Register). i.e. whoami 1384 * Note that PIR is read-only on some CPU versions, so we write to it 1385 * only if it has a different value than we need. 1386 */ 1387 1388 msr = mfspr(SPR_PIR); 1389 if (msr != h->hatch_pir) 1390 mtspr(SPR_PIR, h->hatch_pir); 1391 1392 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1393 curlwp = ci->ci_curlwp; 1394 cpu_spinstart_ack = 0; 1395 1396 /* Initialize MMU. */ 1397 __asm ("mtibatu 0,%0" :: "r"(h->hatch_ibatu[0])); 1398 __asm ("mtibatl 0,%0" :: "r"(h->hatch_ibatl[0])); 1399 __asm ("mtibatu 1,%0" :: "r"(h->hatch_ibatu[1])); 1400 __asm ("mtibatl 1,%0" :: "r"(h->hatch_ibatl[1])); 1401 __asm ("mtibatu 2,%0" :: "r"(h->hatch_ibatu[2])); 1402 __asm ("mtibatl 2,%0" :: "r"(h->hatch_ibatl[2])); 1403 __asm ("mtibatu 3,%0" :: "r"(h->hatch_ibatu[3])); 1404 __asm ("mtibatl 3,%0" :: "r"(h->hatch_ibatl[3])); 1405 __asm ("mtdbatu 0,%0" :: "r"(h->hatch_dbatu[0])); 1406 __asm ("mtdbatl 0,%0" :: "r"(h->hatch_dbatl[0])); 1407 __asm ("mtdbatu 1,%0" :: "r"(h->hatch_dbatu[1])); 1408 __asm ("mtdbatl 1,%0" :: "r"(h->hatch_dbatl[1])); 1409 __asm ("mtdbatu 2,%0" :: "r"(h->hatch_dbatu[2])); 1410 __asm ("mtdbatl 2,%0" :: "r"(h->hatch_dbatl[2])); 1411 __asm ("mtdbatu 3,%0" :: "r"(h->hatch_dbatu[3])); 1412 __asm ("mtdbatl 3,%0" :: "r"(h->hatch_dbatl[3])); 1413 1414 mtspr(SPR_HID0, h->hatch_hid0); 1415 1416 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1417 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1418 1419 __asm volatile ("sync"); 1420 for (i = 0; i < 16; i++) 1421 __asm ("mtsrin %0,%1" :: "r"(h->hatch_sr[i]), "r"(i << ADDR_SR_SHFT)); 1422 __asm volatile ("sync; isync"); 1423 1424 if (oeacpufeat & OEACPU_64) 1425 mtspr(SPR_ASR, h->hatch_asr); 1426 1427 cpu_spinstart_ack = 1; 1428 __asm ("ptesync"); 1429 __asm ("mtsdr1 %0" :: "r"(h->hatch_sdr1)); 1430 __asm volatile ("sync; isync"); 1431 1432 cpu_spinstart_ack = 5; 1433 for (i = 0; i < 16; i++) 1434 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1435 "r"(i << ADDR_SR_SHFT)); 1436 1437 /* Enable I/D address translations. */ 1438 msr = mfmsr(); 1439 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1440 mtmsr(msr); 1441 __asm volatile ("sync; isync"); 1442 cpu_spinstart_ack = 2; 1443 1444 md_sync_timebase(h); 1445 1446 cpu_setup(h->hatch_self, ci); 1447 1448 h->hatch_running = 1; 1449 __asm volatile ("sync; isync"); 1450 1451 while (start_secondary_cpu == 0) 1452 ; 1453 1454 __asm volatile ("sync; isync"); 1455 1456 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1457 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1458 1459 md_setup_interrupts(); 1460 1461 ci->ci_ipending = 0; 1462 ci->ci_cpl = 0; 1463 1464 mtmsr(mfmsr() | PSL_EE); 1465 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1466 return pcb->pcb_sp; 1467 } 1468 1469 void 1470 cpu_boot_secondary_processors(void) 1471 { 1472 start_secondary_cpu = 1; 1473 __asm volatile ("sync"); 1474 } 1475 1476 #endif /*MULTIPROCESSOR*/ 1477
Indexes created Thu Oct 02 07:10:07 GMT 2025