cpu_subr.c revision 1.8.2.1
1 /* $NetBSD: cpu_subr.c,v 1.8.2.1 2004/08/03 10:39:37 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.8.2.1 2004/08/03 10:39:37 skrll Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_multiprocessor.h" 41 #include "opt_altivec.h" 42 #include "sysmon_envsys.h" 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/device.h> 47 #include <sys/malloc.h> 48 49 #include <uvm/uvm_extern.h> 50 51 #include <powerpc/oea/hid.h> 52 #include <powerpc/oea/hid_601.h> 53 #include <powerpc/spr.h> 54 55 #include <dev/sysmon/sysmonvar.h> 56 57 static void cpu_enable_l2cr(register_t); 58 static void cpu_enable_l3cr(register_t); 59 static void cpu_config_l2cr(int); 60 static void cpu_config_l3cr(int); 61 static void cpu_print_speed(void); 62 #if NSYSMON_ENVSYS > 0 63 static void cpu_tau_setup(struct cpu_info *); 64 static int cpu_tau_gtredata __P((struct sysmon_envsys *, 65 struct envsys_tre_data *)); 66 static int cpu_tau_streinfo __P((struct sysmon_envsys *, 67 struct envsys_basic_info *)); 68 #endif 69 70 int cpu; 71 int ncpus; 72 73 struct fmttab { 74 register_t fmt_mask; 75 register_t fmt_value; 76 const char *fmt_string; 77 }; 78 79 static const struct fmttab cpu_7450_l2cr_formats[] = { 80 { L2CR_L2E, 0, " disabled" }, 81 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 82 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 83 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 84 { L2CR_L2E, ~0, " 256KB L2 cache" }, 85 { 0 } 86 }; 87 88 static const struct fmttab cpu_7457_l2cr_formats[] = { 89 { L2CR_L2E, 0, " disabled" }, 90 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 91 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 92 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 93 { L2CR_L2E, ~0, " 512KB L2 cache" }, 94 { 0 } 95 }; 96 97 static const struct fmttab cpu_7450_l3cr_formats[] = { 98 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 99 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 100 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 101 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 102 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 103 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 104 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 105 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 106 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 107 { L3CR_L3SIZ, ~0, " L3 cache" }, 108 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 109 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 110 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 111 { L3CR_L3CLK, ~0, " at" }, 112 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 113 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 114 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 115 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 116 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 117 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 118 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 119 { L3CR_L3CLK, ~0, " ratio" }, 120 { 0, 0 }, 121 }; 122 123 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 124 { L2CR_L2E, 0, " disabled" }, 125 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 126 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 127 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 128 { 0, ~0, " 512KB" }, 129 { L2CR_L2WT, L2CR_L2WT, " WT" }, 130 { L2CR_L2WT, 0, " WB" }, 131 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 132 { 0, ~0, " L2 cache" }, 133 { 0 } 134 }; 135 136 static const struct fmttab cpu_l2cr_formats[] = { 137 { L2CR_L2E, 0, " disabled" }, 138 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 139 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 140 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 141 { L2CR_L2PE, L2CR_L2PE, " parity" }, 142 { L2CR_L2PE, 0, " no-parity" }, 143 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 144 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 145 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 146 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 147 { L2CR_L2WT, L2CR_L2WT, " WT" }, 148 { L2CR_L2WT, 0, " WB" }, 149 { L2CR_L2E, ~0, " L2 cache" }, 150 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 151 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 152 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 153 { L2CR_L2CLK, ~0, " at" }, 154 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 155 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 156 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 157 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 158 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 159 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 160 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 161 { L2CR_L2CLK, ~0, " ratio" }, 162 { 0 } 163 }; 164 165 static void cpu_fmttab_print(const struct fmttab *, register_t); 166 167 struct cputab { 168 const char name[8]; 169 uint16_t version; 170 uint16_t revfmt; 171 }; 172 #define REVFMT_MAJMIN 1 /* %u.%u */ 173 #define REVFMT_HEX 2 /* 0x%04x */ 174 #define REVFMT_DEC 3 /* %u */ 175 static const struct cputab models[] = { 176 { "601", MPC601, REVFMT_DEC }, 177 { "602", MPC602, REVFMT_DEC }, 178 { "603", MPC603, REVFMT_MAJMIN }, 179 { "603e", MPC603e, REVFMT_MAJMIN }, 180 { "603ev", MPC603ev, REVFMT_MAJMIN }, 181 { "604", MPC604, REVFMT_MAJMIN }, 182 { "604ev", MPC604ev, REVFMT_MAJMIN }, 183 { "620", MPC620, REVFMT_HEX }, 184 { "750", MPC750, REVFMT_MAJMIN }, 185 { "750FX", IBM750FX, REVFMT_MAJMIN }, 186 { "7400", MPC7400, REVFMT_MAJMIN }, 187 { "7410", MPC7410, REVFMT_MAJMIN }, 188 { "7450", MPC7450, REVFMT_MAJMIN }, 189 { "7455", MPC7455, REVFMT_MAJMIN }, 190 { "7457", MPC7457, REVFMT_MAJMIN }, 191 { "8240", MPC8240, REVFMT_MAJMIN }, 192 { "", 0, REVFMT_HEX } 193 }; 194 195 196 #ifdef MULTIPROCESSOR 197 struct cpu_info cpu_info[CPU_MAXNUM]; 198 #else 199 struct cpu_info cpu_info[1]; 200 #endif 201 202 int cpu_altivec; 203 int cpu_psluserset, cpu_pslusermod; 204 char cpu_model[80]; 205 206 void 207 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 208 { 209 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 210 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 211 (data & fmt->fmt_mask) == fmt->fmt_value) 212 aprint_normal("%s", fmt->fmt_string); 213 } 214 } 215 216 void 217 cpu_probe_cache(void) 218 { 219 u_int assoc, pvr, vers; 220 221 pvr = mfpvr(); 222 vers = pvr >> 16; 223 224 switch (vers) { 225 #define K *1024 226 case IBM750FX: 227 case MPC601: 228 case MPC750: 229 case MPC7450: 230 case MPC7455: 231 case MPC7457: 232 curcpu()->ci_ci.dcache_size = 32 K; 233 curcpu()->ci_ci.icache_size = 32 K; 234 assoc = 8; 235 break; 236 case MPC603: 237 curcpu()->ci_ci.dcache_size = 8 K; 238 curcpu()->ci_ci.icache_size = 8 K; 239 assoc = 2; 240 break; 241 case MPC603e: 242 case MPC603ev: 243 case MPC604: 244 case MPC8240: 245 case MPC8245: 246 curcpu()->ci_ci.dcache_size = 16 K; 247 curcpu()->ci_ci.icache_size = 16 K; 248 assoc = 4; 249 break; 250 case MPC604ev: 251 curcpu()->ci_ci.dcache_size = 32 K; 252 curcpu()->ci_ci.icache_size = 32 K; 253 assoc = 4; 254 break; 255 default: 256 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 257 curcpu()->ci_ci.icache_size = PAGE_SIZE; 258 assoc = 1; 259 #undef K 260 } 261 262 /* Presently common across all implementations. */ 263 curcpu()->ci_ci.dcache_line_size = CACHELINESIZE; 264 curcpu()->ci_ci.icache_line_size = CACHELINESIZE; 265 266 /* 267 * Possibly recolor. 268 */ 269 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 270 } 271 272 struct cpu_info * 273 cpu_attach_common(struct device *self, int id) 274 { 275 struct cpu_info *ci; 276 u_int pvr, vers; 277 278 ncpus++; 279 ci = &cpu_info[id]; 280 #ifndef MULTIPROCESSOR 281 /* 282 * If this isn't the primary CPU, print an error message 283 * and just bail out. 284 */ 285 if (id != 0) { 286 aprint_normal(": ID %d\n", id); 287 aprint_normal("%s: processor off-line; multiprocessor support " 288 "not present in kernel\n", self->dv_xname); 289 return (NULL); 290 } 291 #endif 292 293 ci->ci_cpuid = id; 294 ci->ci_intrdepth = -1; 295 ci->ci_dev = self; 296 297 pvr = mfpvr(); 298 vers = (pvr >> 16) & 0xffff; 299 300 switch (id) { 301 case 0: 302 /* load my cpu_number to PIR */ 303 switch (vers) { 304 case MPC601: 305 case MPC604: 306 case MPC604ev: 307 case MPC7400: 308 case MPC7410: 309 case MPC7450: 310 case MPC7455: 311 case MPC7457: 312 mtspr(SPR_PIR, id); 313 } 314 cpu_setup(self, ci); 315 break; 316 default: 317 if (id >= CPU_MAXNUM) { 318 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 319 panic("cpuattach"); 320 } 321 #ifndef MULTIPROCESSOR 322 aprint_normal(" not configured\n"); 323 return NULL; 324 #endif 325 } 326 return (ci); 327 } 328 329 void 330 cpu_setup(self, ci) 331 struct device *self; 332 struct cpu_info *ci; 333 { 334 u_int hid0, pvr, vers; 335 char *bitmask, hidbuf[128]; 336 char model[80]; 337 338 pvr = mfpvr(); 339 vers = (pvr >> 16) & 0xffff; 340 341 cpu_identify(model, sizeof(model)); 342 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 343 cpu_number() == 0 ? " (primary)" : ""); 344 345 hid0 = mfspr(SPR_HID0); 346 cpu_probe_cache(); 347 348 /* 349 * Configure power-saving mode. 350 */ 351 switch (vers) { 352 case MPC603: 353 case MPC603e: 354 case MPC603ev: 355 case MPC604ev: 356 case MPC750: 357 case IBM750FX: 358 case MPC7400: 359 case MPC7410: 360 case MPC8240: 361 case MPC8245: 362 /* Select DOZE mode. */ 363 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 364 hid0 |= HID0_DOZE | HID0_DPM; 365 powersave = 1; 366 break; 367 368 case MPC7457: 369 case MPC7455: 370 case MPC7450: 371 /* Enable the 7450 branch caches */ 372 hid0 |= HID0_SGE | HID0_BTIC; 373 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 374 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 375 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 376 hid0 &= ~HID0_BTIC; 377 /* Select NAP mode. */ 378 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 379 hid0 |= HID0_NAP | HID0_DPM; 380 powersave = 0; /* but don't use it */ 381 break; 382 383 default: 384 /* No power-saving mode is available. */ ; 385 } 386 387 #ifdef NAPMODE 388 switch (vers) { 389 case IBM750FX: 390 case MPC750: 391 case MPC7400: 392 /* Select NAP mode. */ 393 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 394 hid0 |= HID0_NAP; 395 break; 396 } 397 #endif 398 399 switch (vers) { 400 case IBM750FX: 401 case MPC750: 402 hid0 &= ~HID0_DBP; /* XXX correct? */ 403 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 404 break; 405 406 case MPC7400: 407 case MPC7410: 408 hid0 &= ~HID0_SPD; 409 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 410 hid0 |= HID0_EIEC; 411 break; 412 } 413 414 mtspr(SPR_HID0, hid0); 415 416 switch (vers) { 417 case MPC601: 418 bitmask = HID0_601_BITMASK; 419 break; 420 case MPC7450: 421 case MPC7455: 422 case MPC7457: 423 bitmask = HID0_7450_BITMASK; 424 break; 425 default: 426 bitmask = HID0_BITMASK; 427 break; 428 } 429 bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf); 430 aprint_normal("%s: HID0 %s\n", self->dv_xname, hidbuf); 431 432 /* 433 * Display speed and cache configuration. 434 */ 435 if (vers == MPC750 || vers == MPC7400 || vers == IBM750FX || 436 vers == MPC7410 || MPC745X_P(vers)) { 437 aprint_normal("%s: ", self->dv_xname); 438 cpu_print_speed(); 439 if (MPC745X_P(vers)) { 440 cpu_config_l3cr(vers); 441 } else { 442 cpu_config_l2cr(pvr); 443 } 444 aprint_normal("\n"); 445 } 446 447 #if NSYSMON_ENVSYS > 0 448 /* 449 * Attach MPC750 temperature sensor to the envsys subsystem. 450 * XXX the 74xx series also has this sensor, but it is not 451 * XXX supported by Motorola and may return values that are off by 452 * XXX 35-55 degrees C. 453 */ 454 if (vers == MPC750 || vers == IBM750FX) 455 cpu_tau_setup(ci); 456 #endif 457 458 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 459 NULL, self->dv_xname, "clock"); 460 evcnt_attach_dynamic(&ci->ci_ev_softclock, EVCNT_TYPE_INTR, 461 NULL, self->dv_xname, "soft clock"); 462 evcnt_attach_dynamic(&ci->ci_ev_softnet, EVCNT_TYPE_INTR, 463 NULL, self->dv_xname, "soft net"); 464 evcnt_attach_dynamic(&ci->ci_ev_softserial, EVCNT_TYPE_INTR, 465 NULL, self->dv_xname, "soft serial"); 466 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 467 NULL, self->dv_xname, "traps"); 468 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 469 &ci->ci_ev_traps, self->dv_xname, "kernel DSI traps"); 470 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 471 &ci->ci_ev_traps, self->dv_xname, "user DSI traps"); 472 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 473 &ci->ci_ev_udsi, self->dv_xname, "user DSI failures"); 474 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 475 &ci->ci_ev_traps, self->dv_xname, "kernel ISI traps"); 476 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 477 &ci->ci_ev_traps, self->dv_xname, "user ISI traps"); 478 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 479 &ci->ci_ev_isi, self->dv_xname, "user ISI failures"); 480 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 481 &ci->ci_ev_traps, self->dv_xname, "system call traps"); 482 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 483 &ci->ci_ev_traps, self->dv_xname, "PGM traps"); 484 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 485 &ci->ci_ev_traps, self->dv_xname, "FPU unavailable traps"); 486 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 487 &ci->ci_ev_fpu, self->dv_xname, "FPU context switches"); 488 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 489 &ci->ci_ev_traps, self->dv_xname, "user alignment traps"); 490 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 491 &ci->ci_ev_ali, self->dv_xname, "user alignment traps"); 492 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 493 &ci->ci_ev_umchk, self->dv_xname, "user MCHK failures"); 494 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 495 &ci->ci_ev_traps, self->dv_xname, "AltiVec unavailable"); 496 #ifdef ALTIVEC 497 if (cpu_altivec) { 498 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 499 &ci->ci_ev_vec, self->dv_xname, "AltiVec context switches"); 500 } 501 #endif 502 } 503 504 void 505 cpu_identify(char *str, size_t len) 506 { 507 u_int pvr, maj, min; 508 uint16_t vers, rev, revfmt; 509 const struct cputab *cp; 510 const char *name; 511 size_t n; 512 513 pvr = mfpvr(); 514 vers = pvr >> 16; 515 rev = pvr; 516 switch (vers) { 517 case MPC7410: 518 min = (pvr >> 0) & 0xff; 519 maj = min <= 4 ? 1 : 2; 520 break; 521 default: 522 maj = (pvr >> 8) & 0xf; 523 min = (pvr >> 0) & 0xf; 524 } 525 526 for (cp = models; cp->name[0] != '\0'; cp++) { 527 if (cp->version == vers) 528 break; 529 } 530 531 if (str == NULL) { 532 str = cpu_model; 533 len = sizeof(cpu_model); 534 cpu = vers; 535 } 536 537 revfmt = cp->revfmt; 538 name = cp->name; 539 if (rev == MPC750 && pvr == 15) { 540 name = "755"; 541 revfmt = REVFMT_HEX; 542 } 543 544 if (cp->name[0] != '\0') { 545 n = snprintf(str, len, "%s (Revision ", cp->name); 546 } else { 547 n = snprintf(str, len, "Version %#x (Revision ", vers); 548 } 549 if (len > n) { 550 switch (revfmt) { 551 case REVFMT_MAJMIN: 552 snprintf(str + n, len - n, "%u.%u)", maj, min); 553 break; 554 case REVFMT_HEX: 555 snprintf(str + n, len - n, "0x%04x)", rev); 556 break; 557 case REVFMT_DEC: 558 snprintf(str + n, len - n, "%u)", rev); 559 break; 560 } 561 } 562 } 563 564 #ifdef L2CR_CONFIG 565 u_int l2cr_config = L2CR_CONFIG; 566 #else 567 u_int l2cr_config = 0; 568 #endif 569 570 #ifdef L3CR_CONFIG 571 u_int l3cr_config = L3CR_CONFIG; 572 #else 573 u_int l3cr_config = 0; 574 #endif 575 576 void 577 cpu_enable_l2cr(register_t l2cr) 578 { 579 register_t msr, x; 580 581 /* Disable interrupts and set the cache config bits. */ 582 msr = mfmsr(); 583 mtmsr(msr & ~PSL_EE); 584 #ifdef ALTIVEC 585 if (cpu_altivec) 586 __asm __volatile("dssall"); 587 #endif 588 __asm __volatile("sync"); 589 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 590 __asm __volatile("sync"); 591 592 /* Wait for L2 clock to be stable (640 L2 clocks). */ 593 delay(100); 594 595 /* Invalidate all L2 contents. */ 596 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 597 do { 598 x = mfspr(SPR_L2CR); 599 } while (x & L2CR_L2IP); 600 601 /* Enable L2 cache. */ 602 l2cr |= L2CR_L2E; 603 mtspr(SPR_L2CR, l2cr); 604 mtmsr(msr); 605 } 606 607 void 608 cpu_enable_l3cr(register_t l3cr) 609 { 610 register_t x; 611 612 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 613 614 /* 615 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 616 * L3CLKEN. (also mask off reserved bits in case they were included 617 * in L3CR_CONFIG) 618 */ 619 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 620 mtspr(SPR_L3CR, l3cr); 621 622 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 623 l3cr |= 0x04000000; 624 mtspr(SPR_L3CR, l3cr); 625 626 /* 3: Set L3CLKEN to 1*/ 627 l3cr |= L3CR_L3CLKEN; 628 mtspr(SPR_L3CR, l3cr); 629 630 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 631 __asm __volatile("dssall;sync"); 632 /* L3 cache is already disabled, no need to clear L3E */ 633 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 634 do { 635 x = mfspr(SPR_L3CR); 636 } while (x & L3CR_L3I); 637 638 /* 6: Clear L3CLKEN to 0 */ 639 l3cr &= ~L3CR_L3CLKEN; 640 mtspr(SPR_L3CR, l3cr); 641 642 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 643 __asm __volatile("sync"); 644 delay(100); 645 646 /* 8: Set L3E and L3CLKEN */ 647 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 648 mtspr(SPR_L3CR, l3cr); 649 650 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 651 __asm __volatile("sync"); 652 delay(100); 653 } 654 655 void 656 cpu_config_l2cr(int pvr) 657 { 658 register_t l2cr; 659 660 l2cr = mfspr(SPR_L2CR); 661 662 /* 663 * For MP systems, the firmware may only configure the L2 cache 664 * on the first CPU. In this case, assume that the other CPUs 665 * should use the same value for L2CR. 666 */ 667 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 668 l2cr_config = l2cr; 669 } 670 671 /* 672 * Configure L2 cache if not enabled. 673 */ 674 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 675 cpu_enable_l2cr(l2cr_config); 676 l2cr = mfspr(SPR_L2CR); 677 } 678 679 if ((l2cr & L2CR_L2E) == 0) 680 return; 681 682 aprint_normal(","); 683 if ((pvr >> 16) == IBM750FX || 684 (pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 685 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) { 686 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 687 } else { 688 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 689 } 690 } 691 692 void 693 cpu_config_l3cr(int vers) 694 { 695 register_t l2cr; 696 register_t l3cr; 697 698 l2cr = mfspr(SPR_L2CR); 699 700 /* 701 * For MP systems, the firmware may only configure the L2 cache 702 * on the first CPU. In this case, assume that the other CPUs 703 * should use the same value for L2CR. 704 */ 705 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 706 l2cr_config = l2cr; 707 } 708 709 /* 710 * Configure L2 cache if not enabled. 711 */ 712 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 713 cpu_enable_l2cr(l2cr_config); 714 l2cr = mfspr(SPR_L2CR); 715 } 716 717 aprint_normal(","); 718 cpu_fmttab_print(vers == MPC7457 719 ? cpu_7457_l2cr_formats : cpu_7450_l2cr_formats, l2cr); 720 721 l3cr = mfspr(SPR_L3CR); 722 723 /* 724 * For MP systems, the firmware may only configure the L3 cache 725 * on the first CPU. In this case, assume that the other CPUs 726 * should use the same value for L3CR. 727 */ 728 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 729 l3cr_config = l3cr; 730 } 731 732 /* 733 * Configure L3 cache if not enabled. 734 */ 735 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 736 cpu_enable_l3cr(l3cr_config); 737 l3cr = mfspr(SPR_L3CR); 738 } 739 740 if (l3cr & L3CR_L3E) { 741 aprint_normal(","); 742 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 743 } 744 } 745 746 void 747 cpu_print_speed(void) 748 { 749 uint64_t cps; 750 751 mtspr(SPR_MMCR0, MMCR0_FC); 752 mtspr(SPR_PMC1, 0); 753 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 754 delay(100000); 755 cps = (mfspr(SPR_PMC1) * 10) + 4999; 756 757 aprint_normal("%lld.%02lld MHz", cps / 1000000, (cps / 10000) % 100); 758 } 759 760 #if NSYSMON_ENVSYS > 0 761 const struct envsys_range cpu_tau_ranges[] = { 762 { 0, 0, ENVSYS_STEMP} 763 }; 764 765 struct envsys_basic_info cpu_tau_info[] = { 766 { 0, ENVSYS_STEMP, "CPU temp", 0, 0, ENVSYS_FVALID} 767 }; 768 769 void 770 cpu_tau_setup(struct cpu_info *ci) 771 { 772 struct { 773 struct sysmon_envsys sme; 774 struct envsys_tre_data tau_info; 775 } *datap; 776 int error; 777 778 datap = malloc(sizeof(*datap), M_DEVBUF, M_WAITOK | M_ZERO); 779 780 ci->ci_sysmon_cookie = &datap->sme; 781 datap->sme.sme_nsensors = 1; 782 datap->sme.sme_envsys_version = 1000; 783 datap->sme.sme_ranges = cpu_tau_ranges; 784 datap->sme.sme_sensor_info = cpu_tau_info; 785 datap->sme.sme_sensor_data = &datap->tau_info; 786 787 datap->sme.sme_sensor_data->sensor = 0; 788 datap->sme.sme_sensor_data->warnflags = ENVSYS_WARN_OK; 789 datap->sme.sme_sensor_data->validflags = ENVSYS_FVALID|ENVSYS_FCURVALID; 790 datap->sme.sme_cookie = ci; 791 datap->sme.sme_gtredata = cpu_tau_gtredata; 792 datap->sme.sme_streinfo = cpu_tau_streinfo; 793 datap->sme.sme_flags = 0; 794 795 if ((error = sysmon_envsys_register(&datap->sme)) != 0) 796 aprint_error("%s: unable to register with sysmon (%d)\n", 797 ci->ci_dev->dv_xname, error); 798 } 799 800 801 /* Find the temperature of the CPU. */ 802 int 803 cpu_tau_gtredata(struct sysmon_envsys *sme, struct envsys_tre_data *tred) 804 { 805 int i, threshold, count; 806 807 if (tred->sensor != 0) { 808 tred->validflags = 0; 809 return 0; 810 } 811 812 threshold = 64; /* Half of the 7-bit sensor range */ 813 mtspr(SPR_THRM1, 0); 814 mtspr(SPR_THRM2, 0); 815 /* XXX This counter is supposed to be "at least 20 microseonds, in 816 * XXX units of clock cycles". Since we don't have convenient 817 * XXX access to the CPU speed, set it to a conservative value, 818 * XXX that is, assuming a fast (1GHz) G3 CPU (As of February 2002, 819 * XXX the fastest G3 processor is 700MHz) . The cost is that 820 * XXX measuring the temperature takes a bit longer. 821 */ 822 mtspr(SPR_THRM3, SPR_THRM_TIMER(20000) | SPR_THRM_ENABLE); 823 824 /* Successive-approximation code adapted from Motorola 825 * application note AN1800/D, "Programming the Thermal Assist 826 * Unit in the MPC750 Microprocessor". 827 */ 828 for (i = 4; i >= 0 ; i--) { 829 mtspr(SPR_THRM1, 830 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 831 count = 0; 832 while ((count < 100) && 833 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 834 count++; 835 delay(1); 836 } 837 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 838 /* The interrupt bit was set, meaning the 839 * temperature was above the threshold 840 */ 841 threshold += 2 << i; 842 } else { 843 /* Temperature was below the threshold */ 844 threshold -= 2 << i; 845 } 846 } 847 threshold += 2; 848 849 /* Convert the temperature in degrees C to microkelvin */ 850 sme->sme_sensor_data->cur.data_us = (threshold * 1000000) + 273150000; 851 852 *tred = *sme->sme_sensor_data; 853 854 return 0; 855 } 856 857 int 858 cpu_tau_streinfo(struct sysmon_envsys *sme, struct envsys_basic_info *binfo) 859 { 860 861 /* There is nothing to set here. */ 862 return (EINVAL); 863 } 864 #endif /* NSYSMON_ENVSYS > 0 */ 865
Indexes created Thu Oct 02 07:10:07 GMT 2025