cpu_subr.c revision 1.97.2.2
1 /* $NetBSD: cpu_subr.c,v 1.97.2.2 2020/04/13 08:04:04 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.97.2.2 2020/04/13 08:04:04 martin Exp $"); 38 39 #include "opt_ppcparam.h" 40 #include "opt_ppccache.h" 41 #include "opt_multiprocessor.h" 42 #include "opt_altivec.h" 43 #include "sysmon_envsys.h" 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/device.h> 48 #include <sys/types.h> 49 #include <sys/lwp.h> 50 #include <sys/xcall.h> 51 52 #include <uvm/uvm.h> 53 54 #include <powerpc/pcb.h> 55 #include <powerpc/psl.h> 56 #include <powerpc/spr.h> 57 #include <powerpc/oea/hid.h> 58 #include <powerpc/oea/hid_601.h> 59 #include <powerpc/oea/spr.h> 60 #include <powerpc/oea/cpufeat.h> 61 62 #include <dev/sysmon/sysmonvar.h> 63 64 static void cpu_enable_l2cr(register_t); 65 static void cpu_enable_l3cr(register_t); 66 static void cpu_config_l2cr(int); 67 static void cpu_config_l3cr(int); 68 static void cpu_probe_speed(struct cpu_info *); 69 static void cpu_idlespin(void); 70 static void cpu_set_dfs_xcall(void *, void *); 71 #if NSYSMON_ENVSYS > 0 72 static void cpu_tau_setup(struct cpu_info *); 73 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 74 #endif 75 76 extern void init_scom_speedctl(void); 77 78 int cpu = -1; 79 int ncpus; 80 81 struct fmttab { 82 register_t fmt_mask; 83 register_t fmt_value; 84 const char *fmt_string; 85 }; 86 87 /* 88 * This should be one per CPU but since we only support it on 750 variants it 89 * doesn't really matter since none of them support SMP 90 */ 91 envsys_data_t sensor; 92 93 static const struct fmttab cpu_7450_l2cr_formats[] = { 94 { L2CR_L2E, 0, " disabled" }, 95 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 96 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 97 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 98 { L2CR_L2E, ~0, " 256KB L2 cache" }, 99 { L2CR_L2PE, 0, " no parity" }, 100 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 101 { 0, 0, NULL } 102 }; 103 104 static const struct fmttab cpu_7448_l2cr_formats[] = { 105 { L2CR_L2E, 0, " disabled" }, 106 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 107 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 108 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 109 { L2CR_L2E, ~0, " 1MB L2 cache" }, 110 { L2CR_L2PE, 0, " no parity" }, 111 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 112 { 0, 0, NULL } 113 }; 114 115 static const struct fmttab cpu_7457_l2cr_formats[] = { 116 { L2CR_L2E, 0, " disabled" }, 117 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 118 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 119 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 120 { L2CR_L2E, ~0, " 512KB L2 cache" }, 121 { L2CR_L2PE, 0, " no parity" }, 122 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 123 { 0, 0, NULL } 124 }; 125 126 static const struct fmttab cpu_7450_l3cr_formats[] = { 127 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 128 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 129 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 130 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 131 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 132 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 133 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 134 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 135 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 136 { L3CR_L3SIZ, ~0, " L3 cache" }, 137 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 138 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 139 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 140 { L3CR_L3CLK, ~0, " at" }, 141 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 142 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 143 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 144 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 145 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 146 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 147 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 148 { L3CR_L3CLK, ~0, " ratio" }, 149 { 0, 0, NULL }, 150 }; 151 152 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 153 { L2CR_L2E, 0, " disabled" }, 154 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 155 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 156 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 157 { 0, ~0, " 512KB" }, 158 { L2CR_L2WT, L2CR_L2WT, " WT" }, 159 { L2CR_L2WT, 0, " WB" }, 160 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 161 { 0, ~0, " L2 cache" }, 162 { 0, 0, NULL } 163 }; 164 165 static const struct fmttab cpu_l2cr_formats[] = { 166 { L2CR_L2E, 0, " disabled" }, 167 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 168 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 169 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 170 { L2CR_L2PE, L2CR_L2PE, " parity" }, 171 { L2CR_L2PE, 0, " no-parity" }, 172 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 173 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 174 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 175 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 176 { L2CR_L2WT, L2CR_L2WT, " WT" }, 177 { L2CR_L2WT, 0, " WB" }, 178 { L2CR_L2E, ~0, " L2 cache" }, 179 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 180 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 181 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 182 { L2CR_L2CLK, ~0, " at" }, 183 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 184 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 185 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 186 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 187 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 188 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 189 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 190 { L2CR_L2CLK, ~0, " ratio" }, 191 { 0, 0, NULL } 192 }; 193 194 static void cpu_fmttab_print(const struct fmttab *, register_t); 195 196 struct cputab { 197 const char name[8]; 198 uint16_t version; 199 uint16_t revfmt; 200 }; 201 #define REVFMT_MAJMIN 1 /* %u.%u */ 202 #define REVFMT_HEX 2 /* 0x%04x */ 203 #define REVFMT_DEC 3 /* %u */ 204 static const struct cputab models[] = { 205 { "601", MPC601, REVFMT_DEC }, 206 { "602", MPC602, REVFMT_DEC }, 207 { "603", MPC603, REVFMT_MAJMIN }, 208 { "603e", MPC603e, REVFMT_MAJMIN }, 209 { "603ev", MPC603ev, REVFMT_MAJMIN }, 210 { "G2", MPCG2, REVFMT_MAJMIN }, 211 { "604", MPC604, REVFMT_MAJMIN }, 212 { "604e", MPC604e, REVFMT_MAJMIN }, 213 { "604ev", MPC604ev, REVFMT_MAJMIN }, 214 { "620", MPC620, REVFMT_HEX }, 215 { "750", MPC750, REVFMT_MAJMIN }, 216 { "750FX", IBM750FX, REVFMT_MAJMIN }, 217 { "750GX", IBM750GX, REVFMT_MAJMIN }, 218 { "7400", MPC7400, REVFMT_MAJMIN }, 219 { "7410", MPC7410, REVFMT_MAJMIN }, 220 { "7450", MPC7450, REVFMT_MAJMIN }, 221 { "7455", MPC7455, REVFMT_MAJMIN }, 222 { "7457", MPC7457, REVFMT_MAJMIN }, 223 { "7447A", MPC7447A, REVFMT_MAJMIN }, 224 { "7448", MPC7448, REVFMT_MAJMIN }, 225 { "8240", MPC8240, REVFMT_MAJMIN }, 226 { "8245", MPC8245, REVFMT_MAJMIN }, 227 { "970", IBM970, REVFMT_MAJMIN }, 228 { "970FX", IBM970FX, REVFMT_MAJMIN }, 229 { "970MP", IBM970MP, REVFMT_MAJMIN }, 230 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 231 { "", 0, REVFMT_HEX } 232 }; 233 234 #ifdef MULTIPROCESSOR 235 struct cpu_info cpu_info[CPU_MAXNUM] = { 236 [0] = { 237 .ci_curlwp = &lwp0, 238 }, 239 }; 240 volatile struct cpu_hatch_data *cpu_hatch_data; 241 volatile int cpu_hatch_stack; 242 #define HATCH_STACK_SIZE 0x1000 243 extern int ticks_per_intr; 244 #include <powerpc/oea/bat.h> 245 #include <powerpc/pic/picvar.h> 246 #include <powerpc/pic/ipivar.h> 247 extern struct bat battable[]; 248 #else 249 struct cpu_info cpu_info[1] = { 250 [0] = { 251 .ci_curlwp = &lwp0, 252 }, 253 }; 254 #endif /*MULTIPROCESSOR*/ 255 256 int cpu_altivec; 257 register_t cpu_psluserset; 258 register_t cpu_pslusermod; 259 register_t cpu_pslusermask = 0xffff; 260 261 /* This is to be called from locore.S, and nowhere else. */ 262 263 void 264 cpu_model_init(void) 265 { 266 u_int pvr, vers; 267 268 pvr = mfpvr(); 269 vers = pvr >> 16; 270 271 oeacpufeat = 0; 272 273 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 274 vers == IBMCELL || vers == IBMPOWER6P5) { 275 oeacpufeat |= OEACPU_64; 276 oeacpufeat |= OEACPU_64_BRIDGE; 277 oeacpufeat |= OEACPU_NOBAT; 278 279 } else if (vers == MPC601) { 280 oeacpufeat |= OEACPU_601; 281 282 } else if (MPC745X_P(vers)) { 283 register_t hid1 = mfspr(SPR_HID1); 284 285 if (vers != MPC7450) { 286 register_t hid0 = mfspr(SPR_HID0); 287 288 /* Enable more SPRG registers */ 289 oeacpufeat |= OEACPU_HIGHSPRG; 290 291 /* Enable more BAT registers */ 292 oeacpufeat |= OEACPU_HIGHBAT; 293 hid0 |= HID0_HIGH_BAT_EN; 294 295 /* Enable larger BAT registers */ 296 oeacpufeat |= OEACPU_XBSEN; 297 hid0 |= HID0_XBSEN; 298 299 mtspr(SPR_HID0, hid0); 300 __asm volatile("sync;isync"); 301 } 302 303 /* Enable address broadcasting for MP systems */ 304 hid1 |= HID1_SYNCBE | HID1_ABE; 305 306 mtspr(SPR_HID1, hid1); 307 __asm volatile("sync;isync"); 308 309 } else if (vers == IBM750FX || vers == IBM750GX) { 310 oeacpufeat |= OEACPU_HIGHBAT; 311 } 312 } 313 314 void 315 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 316 { 317 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 318 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 319 (data & fmt->fmt_mask) == fmt->fmt_value) 320 aprint_normal("%s", fmt->fmt_string); 321 } 322 } 323 324 void 325 cpu_idlespin(void) 326 { 327 register_t msr; 328 329 if (powersave <= 0) 330 return; 331 332 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 333 if (cpu_altivec) 334 __asm volatile("dssall"); 335 #endif 336 337 __asm volatile( 338 "sync;" 339 "mfmsr %0;" 340 "oris %0,%0,%1@h;" /* enter power saving mode */ 341 "mtmsr %0;" 342 "isync;" 343 : "=r"(msr) 344 : "J"(PSL_POW)); 345 } 346 347 void 348 cpu_probe_cache(void) 349 { 350 u_int assoc, pvr, vers; 351 352 pvr = mfpvr(); 353 vers = pvr >> 16; 354 355 356 /* Presently common across almost all implementations. */ 357 curcpu()->ci_ci.dcache_line_size = 32; 358 curcpu()->ci_ci.icache_line_size = 32; 359 360 361 switch (vers) { 362 #define K *1024 363 case IBM750FX: 364 case IBM750GX: 365 case MPC601: 366 case MPC750: 367 case MPC7400: 368 case MPC7447A: 369 case MPC7448: 370 case MPC7450: 371 case MPC7455: 372 case MPC7457: 373 curcpu()->ci_ci.dcache_size = 32 K; 374 curcpu()->ci_ci.icache_size = 32 K; 375 assoc = 8; 376 break; 377 case MPC603: 378 curcpu()->ci_ci.dcache_size = 8 K; 379 curcpu()->ci_ci.icache_size = 8 K; 380 assoc = 2; 381 break; 382 case MPC603e: 383 case MPC603ev: 384 case MPC604: 385 case MPC8240: 386 case MPC8245: 387 case MPCG2: 388 curcpu()->ci_ci.dcache_size = 16 K; 389 curcpu()->ci_ci.icache_size = 16 K; 390 assoc = 4; 391 break; 392 case MPC604e: 393 case MPC604ev: 394 curcpu()->ci_ci.dcache_size = 32 K; 395 curcpu()->ci_ci.icache_size = 32 K; 396 assoc = 4; 397 break; 398 case IBMPOWER3II: 399 curcpu()->ci_ci.dcache_size = 64 K; 400 curcpu()->ci_ci.icache_size = 32 K; 401 curcpu()->ci_ci.dcache_line_size = 128; 402 curcpu()->ci_ci.icache_line_size = 128; 403 assoc = 128; /* not a typo */ 404 break; 405 case IBM970: 406 case IBM970FX: 407 case IBM970MP: 408 curcpu()->ci_ci.dcache_size = 32 K; 409 curcpu()->ci_ci.icache_size = 64 K; 410 curcpu()->ci_ci.dcache_line_size = 128; 411 curcpu()->ci_ci.icache_line_size = 128; 412 assoc = 2; 413 break; 414 415 default: 416 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 417 curcpu()->ci_ci.icache_size = PAGE_SIZE; 418 assoc = 1; 419 #undef K 420 } 421 422 /* 423 * Possibly recolor. 424 */ 425 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 426 } 427 428 struct cpu_info * 429 cpu_attach_common(device_t self, int id) 430 { 431 struct cpu_info *ci; 432 u_int pvr, vers; 433 434 ci = &cpu_info[id]; 435 #ifndef MULTIPROCESSOR 436 /* 437 * If this isn't the primary CPU, print an error message 438 * and just bail out. 439 */ 440 if (id != 0) { 441 aprint_naive("\n"); 442 aprint_normal(": ID %d\n", id); 443 aprint_normal_dev(self, 444 "processor off-line; " 445 "multiprocessor support not present in kernel\n"); 446 return (NULL); 447 } 448 #endif 449 450 ci->ci_cpuid = id; 451 ci->ci_idepth = -1; 452 ci->ci_dev = self; 453 ci->ci_idlespin = cpu_idlespin; 454 455 #ifdef MULTIPROCESSOR 456 /* Register IPI Interrupt */ 457 if ((ipiops.ppc_establish_ipi) && (id == 0)) 458 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 459 #endif 460 461 pvr = mfpvr(); 462 vers = (pvr >> 16) & 0xffff; 463 464 switch (id) { 465 case 0: 466 /* load my cpu_number to PIR */ 467 switch (vers) { 468 case MPC601: 469 case MPC604: 470 case MPC604e: 471 case MPC604ev: 472 case MPC7400: 473 case MPC7410: 474 case MPC7447A: 475 case MPC7448: 476 case MPC7450: 477 case MPC7455: 478 case MPC7457: 479 mtspr(SPR_PIR, id); 480 } 481 cpu_setup(self, ci); 482 break; 483 default: 484 aprint_naive("\n"); 485 if (id >= CPU_MAXNUM) { 486 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 487 panic("cpuattach"); 488 } 489 #ifndef MULTIPROCESSOR 490 aprint_normal(" not configured\n"); 491 return NULL; 492 #else 493 mi_cpu_attach(ci); 494 break; 495 #endif 496 } 497 return (ci); 498 } 499 500 void 501 cpu_setup(device_t self, struct cpu_info *ci) 502 { 503 u_int pvr, vers; 504 const char * const xname = device_xname(self); 505 const char *bitmask; 506 char hidbuf[128]; 507 char model[80]; 508 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 509 char hidbuf_u[128]; 510 const char *bitmasku = NULL; 511 volatile uint64_t hid64_0, hid64_0_save; 512 #endif 513 #if !defined(_ARCH_PPC64) 514 register_t hid0 = 0, hid0_save = 0; 515 #endif 516 517 pvr = mfpvr(); 518 vers = (pvr >> 16) & 0xffff; 519 520 cpu_identify(model, sizeof(model)); 521 aprint_naive("\n"); 522 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 523 cpu_number() == 0 ? " (primary)" : ""); 524 525 /* set the cpu number */ 526 ci->ci_cpuid = cpu_number(); 527 #if defined(_ARCH_PPC64) 528 __asm volatile("mfspr %0,%1" : "=r"(hid64_0) : "K"(SPR_HID0)); 529 hid64_0_save = hid64_0; 530 #else 531 #if defined(PPC_OEA64_BRIDGE) 532 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) 533 hid64_0_save = hid64_0 = mfspr(SPR_HID0); 534 else 535 #endif 536 hid0_save = hid0 = mfspr(SPR_HID0); 537 #endif 538 539 540 cpu_probe_cache(); 541 542 /* 543 * Configure power-saving mode. 544 */ 545 switch (vers) { 546 #if !defined(_ARCH_PPC64) 547 case MPC604: 548 case MPC604e: 549 case MPC604ev: 550 /* 551 * Do not have HID0 support settings, but can support 552 * MSR[POW] off 553 */ 554 powersave = 1; 555 break; 556 557 case MPC603: 558 case MPC603e: 559 case MPC603ev: 560 case MPC7400: 561 case MPC7410: 562 case MPC8240: 563 case MPC8245: 564 case MPCG2: 565 /* Select DOZE mode. */ 566 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 567 hid0 |= HID0_DOZE | HID0_DPM; 568 powersave = 1; 569 break; 570 571 case MPC750: 572 case IBM750FX: 573 case IBM750GX: 574 /* Select NAP mode. */ 575 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 576 hid0 |= HID0_NAP | HID0_DPM; 577 powersave = 1; 578 break; 579 580 case MPC7447A: 581 case MPC7448: 582 case MPC7457: 583 case MPC7455: 584 case MPC7450: 585 /* Enable the 7450 branch caches */ 586 hid0 |= HID0_SGE | HID0_BTIC; 587 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 588 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 589 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 590 hid0 &= ~HID0_BTIC; 591 /* Select NAP mode. */ 592 hid0 &= ~HID0_SLEEP; 593 /* XXX my quicksilver hangs if nap is enabled */ 594 if (vers != MPC7450) { 595 hid0 |= HID0_NAP | HID0_DPM; 596 powersave = 1; 597 } 598 break; 599 #endif 600 601 case IBM970: 602 case IBM970FX: 603 case IBM970MP: 604 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 605 #if !defined(_ARCH_PPC64) 606 KASSERT((oeacpufeat & OEACPU_64_BRIDGE) != 0); 607 #endif 608 hid64_0 &= ~(HID0_64_DOZE | HID0_64_NAP | HID0_64_DEEPNAP); 609 hid64_0 |= HID0_64_NAP | HID0_64_DPM | HID0_64_EX_TBEN | 610 HID0_64_TB_CTRL | HID0_64_EN_MCHK; 611 powersave = 1; 612 break; 613 #endif 614 case IBMPOWER3II: 615 default: 616 /* No power-saving mode is available. */ ; 617 } 618 619 #ifdef NAPMODE 620 switch (vers) { 621 case IBM750FX: 622 case IBM750GX: 623 case MPC750: 624 case MPC7400: 625 /* Select NAP mode. */ 626 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 627 hid0 |= HID0_NAP; 628 break; 629 } 630 #endif 631 632 switch (vers) { 633 case IBM750FX: 634 case IBM750GX: 635 case MPC750: 636 hid0 &= ~HID0_DBP; /* XXX correct? */ 637 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 638 break; 639 640 case MPC7400: 641 case MPC7410: 642 hid0 &= ~HID0_SPD; 643 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 644 hid0 |= HID0_EIEC; 645 break; 646 } 647 648 /* 649 * according to the 603e manual this is necessary for an external L2 650 * cache to work properly 651 */ 652 switch (vers) { 653 case MPC603e: 654 hid0 |= HID0_ABE; 655 } 656 657 #if defined(_ARCH_PPC64) || defined(PPC_OEA64_BRIDGE) 658 #if defined(PPC_OEA64_BRIDGE) 659 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 660 #endif 661 if (hid64_0 != hid64_0_save) { 662 mtspr64(SPR_HID0, hid64_0); 663 } 664 #if defined(PPC_OEA64_BRIDGE) 665 } else { 666 #endif 667 #endif 668 669 #if !defined(_ARCH_PPC64) 670 if (hid0 != hid0_save) { 671 mtspr(SPR_HID0, hid0); 672 __asm volatile("sync;isync"); 673 } 674 #endif 675 #if defined(PPC_OEA64_BRIDGE) 676 } 677 #endif 678 679 switch (vers) { 680 case MPC601: 681 bitmask = HID0_601_BITMASK; 682 break; 683 case MPC7447A: 684 case MPC7448: 685 case MPC7450: 686 case MPC7455: 687 case MPC7457: 688 bitmask = HID0_7450_BITMASK; 689 break; 690 case IBM970: 691 case IBM970FX: 692 case IBM970MP: 693 bitmask = HID0_970_BITMASK; 694 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 695 bitmasku = HID0_970_BITMASK_U; 696 #endif 697 break; 698 default: 699 bitmask = HID0_BITMASK; 700 break; 701 } 702 703 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 704 if (bitmasku != NULL) { 705 snprintb(hidbuf, sizeof hidbuf, bitmask, hid64_0 & 0xffffffff); 706 snprintb(hidbuf_u, sizeof hidbuf_u, bitmasku, hid64_0 >> 32); 707 aprint_normal_dev(self, "HID0 %s %s, powersave: %d\n", 708 hidbuf_u, hidbuf, powersave); 709 } else 710 #endif 711 { 712 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 713 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", 714 hidbuf, powersave); 715 } 716 717 ci->ci_khz = 0; 718 719 /* 720 * Display speed and cache configuration. 721 */ 722 switch (vers) { 723 case MPC604: 724 case MPC604e: 725 case MPC604ev: 726 case MPC750: 727 case IBM750FX: 728 case IBM750GX: 729 case MPC7400: 730 case MPC7410: 731 case MPC7447A: 732 case MPC7448: 733 case MPC7450: 734 case MPC7455: 735 case MPC7457: 736 aprint_normal_dev(self, ""); 737 cpu_probe_speed(ci); 738 aprint_normal("%u.%02u MHz", 739 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 740 switch (vers) { 741 case MPC7450: /* 7441 does not have L3! */ 742 case MPC7455: /* 7445 does not have L3! */ 743 case MPC7457: /* 7447 does not have L3! */ 744 cpu_config_l3cr(vers); 745 break; 746 case IBM750FX: 747 case IBM750GX: 748 case MPC750: 749 case MPC7400: 750 case MPC7410: 751 case MPC7447A: 752 case MPC7448: 753 cpu_config_l2cr(pvr); 754 break; 755 default: 756 break; 757 } 758 aprint_normal("\n"); 759 break; 760 } 761 762 #if NSYSMON_ENVSYS > 0 763 /* 764 * Attach MPC750 temperature sensor to the envsys subsystem. 765 * XXX the 74xx series also has this sensor, but it is not 766 * XXX supported by Motorola and may return values that are off by 767 * XXX 35-55 degrees C. 768 */ 769 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 770 cpu_tau_setup(ci); 771 #endif 772 773 #if defined(PPC_OEA64) || defined(PPC_OEA64_BRIDGE) 774 if (vers == IBM970MP) 775 init_scom_speedctl(); 776 #endif 777 778 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 779 NULL, xname, "clock"); 780 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 781 NULL, xname, "traps"); 782 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 783 &ci->ci_ev_traps, xname, "kernel DSI traps"); 784 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 785 &ci->ci_ev_traps, xname, "user DSI traps"); 786 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 787 &ci->ci_ev_udsi, xname, "user DSI failures"); 788 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 789 &ci->ci_ev_traps, xname, "kernel ISI traps"); 790 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 791 &ci->ci_ev_traps, xname, "user ISI traps"); 792 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 793 &ci->ci_ev_isi, xname, "user ISI failures"); 794 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 795 &ci->ci_ev_traps, xname, "system call traps"); 796 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 797 &ci->ci_ev_traps, xname, "PGM traps"); 798 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 799 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 800 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 801 &ci->ci_ev_fpu, xname, "FPU context switches"); 802 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 803 &ci->ci_ev_traps, xname, "user alignment traps"); 804 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 805 &ci->ci_ev_ali, xname, "user alignment traps"); 806 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 807 &ci->ci_ev_umchk, xname, "user MCHK failures"); 808 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 809 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 810 #ifdef ALTIVEC 811 if (cpu_altivec) { 812 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 813 &ci->ci_ev_vec, xname, "AltiVec context switches"); 814 } 815 #endif 816 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 817 NULL, xname, "IPIs"); 818 } 819 820 /* 821 * According to a document labeled "PVR Register Settings": 822 ** For integrated microprocessors the PVR register inside the device 823 ** will identify the version of the microprocessor core. You must also 824 ** read the Device ID, PCI register 02, to identify the part and the 825 ** Revision ID, PCI register 08, to identify the revision of the 826 ** integrated microprocessor. 827 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 828 */ 829 830 void 831 cpu_identify(char *str, size_t len) 832 { 833 u_int pvr, major, minor; 834 uint16_t vers, rev, revfmt; 835 const struct cputab *cp; 836 size_t n; 837 838 pvr = mfpvr(); 839 vers = pvr >> 16; 840 rev = pvr; 841 842 switch (vers) { 843 case MPC7410: 844 minor = (pvr >> 0) & 0xff; 845 major = minor <= 4 ? 1 : 2; 846 break; 847 case MPCG2: /*XXX see note above */ 848 major = (pvr >> 4) & 0xf; 849 minor = (pvr >> 0) & 0xf; 850 break; 851 default: 852 major = (pvr >> 8) & 0xf; 853 minor = (pvr >> 0) & 0xf; 854 } 855 856 for (cp = models; cp->name[0] != '\0'; cp++) { 857 if (cp->version == vers) 858 break; 859 } 860 861 if (cpu == -1) 862 cpu = vers; 863 864 revfmt = cp->revfmt; 865 if (rev == MPC750 && pvr == 15) { 866 revfmt = REVFMT_HEX; 867 } 868 869 if (cp->name[0] != '\0') { 870 n = snprintf(str, len, "%s (Revision ", cp->name); 871 } else { 872 n = snprintf(str, len, "Version %#x (Revision ", vers); 873 } 874 if (len > n) { 875 switch (revfmt) { 876 case REVFMT_MAJMIN: 877 snprintf(str + n, len - n, "%u.%u)", major, minor); 878 break; 879 case REVFMT_HEX: 880 snprintf(str + n, len - n, "0x%04x)", rev); 881 break; 882 case REVFMT_DEC: 883 snprintf(str + n, len - n, "%u)", rev); 884 break; 885 } 886 } 887 } 888 889 #ifdef L2CR_CONFIG 890 u_int l2cr_config = L2CR_CONFIG; 891 #else 892 u_int l2cr_config = 0; 893 #endif 894 895 #ifdef L3CR_CONFIG 896 u_int l3cr_config = L3CR_CONFIG; 897 #else 898 u_int l3cr_config = 0; 899 #endif 900 901 void 902 cpu_enable_l2cr(register_t l2cr) 903 { 904 register_t msr, x; 905 uint16_t vers; 906 907 vers = mfpvr() >> 16; 908 909 /* Disable interrupts and set the cache config bits. */ 910 msr = mfmsr(); 911 mtmsr(msr & ~PSL_EE); 912 #ifdef ALTIVEC 913 if (cpu_altivec) 914 __asm volatile("dssall"); 915 #endif 916 __asm volatile("sync"); 917 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 918 __asm volatile("sync"); 919 920 /* Wait for L2 clock to be stable (640 L2 clocks). */ 921 delay(100); 922 923 /* Invalidate all L2 contents. */ 924 if (MPC745X_P(vers)) { 925 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 926 do { 927 x = mfspr(SPR_L2CR); 928 } while (x & L2CR_L2I); 929 } else { 930 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 931 do { 932 x = mfspr(SPR_L2CR); 933 } while (x & L2CR_L2IP); 934 } 935 /* Enable L2 cache. */ 936 l2cr |= L2CR_L2E; 937 mtspr(SPR_L2CR, l2cr); 938 mtmsr(msr); 939 } 940 941 void 942 cpu_enable_l3cr(register_t l3cr) 943 { 944 register_t x; 945 946 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 947 948 /* 949 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 950 * L3CLKEN. (also mask off reserved bits in case they were included 951 * in L3CR_CONFIG) 952 */ 953 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 954 mtspr(SPR_L3CR, l3cr); 955 956 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 957 l3cr |= 0x04000000; 958 mtspr(SPR_L3CR, l3cr); 959 960 /* 3: Set L3CLKEN to 1*/ 961 l3cr |= L3CR_L3CLKEN; 962 mtspr(SPR_L3CR, l3cr); 963 964 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 965 __asm volatile("dssall;sync"); 966 /* L3 cache is already disabled, no need to clear L3E */ 967 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 968 do { 969 x = mfspr(SPR_L3CR); 970 } while (x & L3CR_L3I); 971 972 /* 6: Clear L3CLKEN to 0 */ 973 l3cr &= ~L3CR_L3CLKEN; 974 mtspr(SPR_L3CR, l3cr); 975 976 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 977 __asm volatile("sync"); 978 delay(100); 979 980 /* 8: Set L3E and L3CLKEN */ 981 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 982 mtspr(SPR_L3CR, l3cr); 983 984 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 985 __asm volatile("sync"); 986 delay(100); 987 } 988 989 void 990 cpu_config_l2cr(int pvr) 991 { 992 register_t l2cr; 993 u_int vers = (pvr >> 16) & 0xffff; 994 995 l2cr = mfspr(SPR_L2CR); 996 997 /* 998 * For MP systems, the firmware may only configure the L2 cache 999 * on the first CPU. In this case, assume that the other CPUs 1000 * should use the same value for L2CR. 1001 */ 1002 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 1003 l2cr_config = l2cr; 1004 } 1005 1006 /* 1007 * Configure L2 cache if not enabled. 1008 */ 1009 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1010 cpu_enable_l2cr(l2cr_config); 1011 l2cr = mfspr(SPR_L2CR); 1012 } 1013 1014 if ((l2cr & L2CR_L2E) == 0) { 1015 aprint_normal(" L2 cache present but not enabled "); 1016 return; 1017 } 1018 aprint_normal(","); 1019 1020 switch (vers) { 1021 case IBM750FX: 1022 case IBM750GX: 1023 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1024 break; 1025 case MPC750: 1026 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 1027 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) 1028 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1029 else 1030 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1031 break; 1032 case MPC7447A: 1033 case MPC7457: 1034 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1035 return; 1036 case MPC7448: 1037 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1038 return; 1039 case MPC7450: 1040 case MPC7455: 1041 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1042 break; 1043 default: 1044 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1045 break; 1046 } 1047 } 1048 1049 void 1050 cpu_config_l3cr(int vers) 1051 { 1052 register_t l2cr; 1053 register_t l3cr; 1054 1055 l2cr = mfspr(SPR_L2CR); 1056 1057 /* 1058 * For MP systems, the firmware may only configure the L2 cache 1059 * on the first CPU. In this case, assume that the other CPUs 1060 * should use the same value for L2CR. 1061 */ 1062 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 1063 l2cr_config = l2cr; 1064 } 1065 1066 /* 1067 * Configure L2 cache if not enabled. 1068 */ 1069 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1070 cpu_enable_l2cr(l2cr_config); 1071 l2cr = mfspr(SPR_L2CR); 1072 } 1073 1074 aprint_normal(","); 1075 switch (vers) { 1076 case MPC7447A: 1077 case MPC7457: 1078 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1079 return; 1080 case MPC7448: 1081 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1082 return; 1083 default: 1084 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1085 break; 1086 } 1087 1088 l3cr = mfspr(SPR_L3CR); 1089 1090 /* 1091 * For MP systems, the firmware may only configure the L3 cache 1092 * on the first CPU. In this case, assume that the other CPUs 1093 * should use the same value for L3CR. 1094 */ 1095 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 1096 l3cr_config = l3cr; 1097 } 1098 1099 /* 1100 * Configure L3 cache if not enabled. 1101 */ 1102 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 1103 cpu_enable_l3cr(l3cr_config); 1104 l3cr = mfspr(SPR_L3CR); 1105 } 1106 1107 if (l3cr & L3CR_L3E) { 1108 aprint_normal(","); 1109 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1110 } 1111 } 1112 1113 void 1114 cpu_probe_speed(struct cpu_info *ci) 1115 { 1116 uint64_t cps; 1117 1118 mtspr(SPR_MMCR0, MMCR0_FC); 1119 mtspr(SPR_PMC1, 0); 1120 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1121 delay(100000); 1122 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1123 1124 mtspr(SPR_MMCR0, MMCR0_FC); 1125 1126 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1127 } 1128 1129 /* 1130 * Read the Dynamic Frequency Switching state and return a divisor for 1131 * the maximum frequency. 1132 */ 1133 int 1134 cpu_get_dfs(void) 1135 { 1136 u_int pvr, vers; 1137 1138 pvr = mfpvr(); 1139 vers = pvr >> 16; 1140 1141 switch (vers) { 1142 case MPC7448: 1143 if (mfspr(SPR_HID1) & HID1_DFS4) 1144 return 4; 1145 /* FALLTHROUGH */ 1146 case MPC7447A: 1147 if (mfspr(SPR_HID1) & HID1_DFS2) 1148 return 2; 1149 } 1150 return 1; 1151 } 1152 1153 /* 1154 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1155 */ 1156 void 1157 cpu_set_dfs(int div) 1158 { 1159 u_int dfs_mask, pvr, vers; 1160 1161 pvr = mfpvr(); 1162 vers = pvr >> 16; 1163 dfs_mask = 0; 1164 1165 switch (vers) { 1166 case MPC7448: 1167 dfs_mask |= HID1_DFS4; 1168 /* FALLTHROUGH */ 1169 case MPC7447A: 1170 dfs_mask |= HID1_DFS2; 1171 break; 1172 default: 1173 printf("cpu_set_dfs: DFS not supported\n"); 1174 return; 1175 1176 } 1177 #ifdef MULTIPROCESSOR 1178 uint64_t where; 1179 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1180 xc_wait(where); 1181 #else 1182 cpu_set_dfs_xcall(&div, &dfs_mask); 1183 #endif 1184 } 1185 1186 static void 1187 cpu_set_dfs_xcall(void *arg1, void *arg2) 1188 { 1189 u_int dfs_mask, hid1, old_hid1; 1190 int *divisor, s; 1191 1192 divisor = arg1; 1193 dfs_mask = *(u_int *)arg2; 1194 1195 s = splhigh(); 1196 hid1 = old_hid1 = mfspr(SPR_HID1); 1197 1198 switch (*divisor) { 1199 case 1: 1200 hid1 &= ~dfs_mask; 1201 break; 1202 case 2: 1203 hid1 &= ~(dfs_mask & HID1_DFS4); 1204 hid1 |= dfs_mask & HID1_DFS2; 1205 break; 1206 case 4: 1207 hid1 &= ~(dfs_mask & HID1_DFS2); 1208 hid1 |= dfs_mask & HID1_DFS4; 1209 break; 1210 } 1211 1212 if (hid1 != old_hid1) { 1213 __asm volatile("sync"); 1214 mtspr(SPR_HID1, hid1); 1215 __asm volatile("sync;isync"); 1216 } 1217 1218 splx(s); 1219 } 1220 1221 #if NSYSMON_ENVSYS > 0 1222 void 1223 cpu_tau_setup(struct cpu_info *ci) 1224 { 1225 struct sysmon_envsys *sme; 1226 int error, therm_delay; 1227 1228 mtspr(SPR_THRM1, SPR_THRM_VALID); 1229 mtspr(SPR_THRM2, 0); 1230 1231 /* 1232 * we need to figure out how much 20+us in units of CPU clock cycles 1233 * are 1234 */ 1235 1236 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1237 1238 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1239 1240 sme = sysmon_envsys_create(); 1241 1242 sensor.units = ENVSYS_STEMP; 1243 sensor.state = ENVSYS_SINVALID; 1244 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1245 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1246 sysmon_envsys_destroy(sme); 1247 return; 1248 } 1249 1250 sme->sme_name = device_xname(ci->ci_dev); 1251 sme->sme_cookie = ci; 1252 sme->sme_refresh = cpu_tau_refresh; 1253 1254 if ((error = sysmon_envsys_register(sme)) != 0) { 1255 aprint_error_dev(ci->ci_dev, 1256 " unable to register with sysmon (%d)\n", error); 1257 sysmon_envsys_destroy(sme); 1258 } 1259 } 1260 1261 /* Find the temperature of the CPU. */ 1262 void 1263 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1264 { 1265 int i, threshold, count; 1266 1267 threshold = 64; /* Half of the 7-bit sensor range */ 1268 1269 /* Successive-approximation code adapted from Motorola 1270 * application note AN1800/D, "Programming the Thermal Assist 1271 * Unit in the MPC750 Microprocessor". 1272 */ 1273 for (i = 5; i >= 0 ; i--) { 1274 mtspr(SPR_THRM1, 1275 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1276 count = 0; 1277 while ((count < 100000) && 1278 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1279 count++; 1280 delay(1); 1281 } 1282 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1283 /* The interrupt bit was set, meaning the 1284 * temperature was above the threshold 1285 */ 1286 threshold += 1 << i; 1287 } else { 1288 /* Temperature was below the threshold */ 1289 threshold -= 1 << i; 1290 } 1291 } 1292 threshold += 2; 1293 1294 /* Convert the temperature in degrees C to microkelvin */ 1295 edata->value_cur = (threshold * 1000000) + 273150000; 1296 edata->state = ENVSYS_SVALID; 1297 } 1298 #endif /* NSYSMON_ENVSYS > 0 */ 1299 1300 #ifdef MULTIPROCESSOR 1301 volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum; 1302 1303 int 1304 cpu_spinup(device_t self, struct cpu_info *ci) 1305 { 1306 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1307 struct pglist mlist; 1308 int i, error; 1309 char *hp; 1310 1311 KASSERT(ci != curcpu()); 1312 1313 /* Now allocate a hatch stack */ 1314 error = uvm_pglistalloc(HATCH_STACK_SIZE, 0x10000, 0x10000000, 16, 0, 1315 &mlist, 1, 1); 1316 if (error) { 1317 aprint_error(": unable to allocate hatch stack\n"); 1318 return -1; 1319 } 1320 1321 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1322 memset(hp, 0, HATCH_STACK_SIZE); 1323 1324 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1325 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1326 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1327 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1328 1329 cpu_hatch_data = h; 1330 h->hatch_running = 0; 1331 h->hatch_self = self; 1332 h->hatch_ci = ci; 1333 h->hatch_pir = ci->ci_cpuid; 1334 1335 cpu_hatch_stack = (uint32_t)hp + HATCH_STACK_SIZE - CALLFRAMELEN; 1336 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1337 1338 /* copy special registers */ 1339 1340 h->hatch_hid0 = mfspr(SPR_HID0); 1341 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 1342 h->hatch_hid1 = mfspr(SPR_HID1); 1343 h->hatch_hid4 = mfspr(SPR_HID4); 1344 h->hatch_hid5 = mfspr(SPR_HID5); 1345 #endif 1346 1347 __asm volatile ("mfsdr1 %0" : "=r"(h->hatch_sdr1)); 1348 for (i = 0; i < 16; i++) { 1349 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1350 "r"(i << ADDR_SR_SHFT)); 1351 } 1352 if (oeacpufeat & OEACPU_64) 1353 h->hatch_asr = mfspr(SPR_ASR); 1354 else 1355 h->hatch_asr = 0; 1356 1357 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1358 /* copy the bat regs */ 1359 __asm volatile ("mfibatu %0,0" : "=r"(h->hatch_ibatu[0])); 1360 __asm volatile ("mfibatl %0,0" : "=r"(h->hatch_ibatl[0])); 1361 __asm volatile ("mfibatu %0,1" : "=r"(h->hatch_ibatu[1])); 1362 __asm volatile ("mfibatl %0,1" : "=r"(h->hatch_ibatl[1])); 1363 __asm volatile ("mfibatu %0,2" : "=r"(h->hatch_ibatu[2])); 1364 __asm volatile ("mfibatl %0,2" : "=r"(h->hatch_ibatl[2])); 1365 __asm volatile ("mfibatu %0,3" : "=r"(h->hatch_ibatu[3])); 1366 __asm volatile ("mfibatl %0,3" : "=r"(h->hatch_ibatl[3])); 1367 __asm volatile ("mfdbatu %0,0" : "=r"(h->hatch_dbatu[0])); 1368 __asm volatile ("mfdbatl %0,0" : "=r"(h->hatch_dbatl[0])); 1369 __asm volatile ("mfdbatu %0,1" : "=r"(h->hatch_dbatu[1])); 1370 __asm volatile ("mfdbatl %0,1" : "=r"(h->hatch_dbatl[1])); 1371 __asm volatile ("mfdbatu %0,2" : "=r"(h->hatch_dbatu[2])); 1372 __asm volatile ("mfdbatl %0,2" : "=r"(h->hatch_dbatl[2])); 1373 __asm volatile ("mfdbatu %0,3" : "=r"(h->hatch_dbatu[3])); 1374 __asm volatile ("mfdbatl %0,3" : "=r"(h->hatch_dbatl[3])); 1375 __asm volatile ("sync; isync"); 1376 } 1377 1378 if (md_setup_trampoline(h, ci) == -1) 1379 return -1; 1380 md_presync_timebase(h); 1381 md_start_timebase(h); 1382 1383 /* wait for secondary printf */ 1384 1385 delay(200000); 1386 1387 #ifdef CACHE_PROTO_MEI 1388 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1389 __asm volatile ("sync; isync"); 1390 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1391 __asm volatile ("sync; isync"); 1392 #endif 1393 int hatch_bail = 0; 1394 while ((h->hatch_running < 1) && (hatch_bail < 100000)) { 1395 delay(1); 1396 hatch_bail++; 1397 #ifdef CACHE_PROTO_MEI 1398 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1399 __asm volatile ("sync; isync"); 1400 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1401 __asm volatile ("sync; isync"); 1402 #endif 1403 } 1404 if (h->hatch_running < 1) { 1405 #ifdef CACHE_PROTO_MEI 1406 __asm volatile ("dcbi 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1407 __asm volatile ("sync; isync"); 1408 __asm volatile ("dcbst 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1409 __asm volatile ("sync; isync"); 1410 #endif 1411 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1412 ci->ci_cpuid, cpu_spinstart_ack); 1413 Debugger(); 1414 return -1; 1415 } 1416 1417 return 0; 1418 } 1419 1420 static volatile int start_secondary_cpu; 1421 1422 register_t 1423 cpu_hatch(void) 1424 { 1425 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1426 struct cpu_info * const ci = h->hatch_ci; 1427 struct pcb *pcb; 1428 u_int msr; 1429 int i; 1430 1431 /* Initialize timebase. */ 1432 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1433 1434 /* 1435 * Set PIR (Processor Identification Register). i.e. whoami 1436 * Note that PIR is read-only on some CPU versions, so we write to it 1437 * only if it has a different value than we need. 1438 */ 1439 1440 msr = mfspr(SPR_PIR); 1441 if (msr != h->hatch_pir) 1442 mtspr(SPR_PIR, h->hatch_pir); 1443 1444 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1445 curlwp = ci->ci_curlwp; 1446 cpu_spinstart_ack = 0; 1447 1448 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1449 /* Initialize MMU. */ 1450 __asm ("mtibatu 0,%0" :: "r"(h->hatch_ibatu[0])); 1451 __asm ("mtibatl 0,%0" :: "r"(h->hatch_ibatl[0])); 1452 __asm ("mtibatu 1,%0" :: "r"(h->hatch_ibatu[1])); 1453 __asm ("mtibatl 1,%0" :: "r"(h->hatch_ibatl[1])); 1454 __asm ("mtibatu 2,%0" :: "r"(h->hatch_ibatu[2])); 1455 __asm ("mtibatl 2,%0" :: "r"(h->hatch_ibatl[2])); 1456 __asm ("mtibatu 3,%0" :: "r"(h->hatch_ibatu[3])); 1457 __asm ("mtibatl 3,%0" :: "r"(h->hatch_ibatl[3])); 1458 __asm ("mtdbatu 0,%0" :: "r"(h->hatch_dbatu[0])); 1459 __asm ("mtdbatl 0,%0" :: "r"(h->hatch_dbatl[0])); 1460 __asm ("mtdbatu 1,%0" :: "r"(h->hatch_dbatu[1])); 1461 __asm ("mtdbatl 1,%0" :: "r"(h->hatch_dbatl[1])); 1462 __asm ("mtdbatu 2,%0" :: "r"(h->hatch_dbatu[2])); 1463 __asm ("mtdbatl 2,%0" :: "r"(h->hatch_dbatl[2])); 1464 __asm ("mtdbatu 3,%0" :: "r"(h->hatch_dbatu[3])); 1465 __asm ("mtdbatl 3,%0" :: "r"(h->hatch_dbatl[3])); 1466 } 1467 1468 #ifdef PPC_OEA64_BRIDGE 1469 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 1470 1471 mtspr64(SPR_HID0, h->hatch_hid0); 1472 mtspr64(SPR_HID1, h->hatch_hid1); 1473 mtspr64(SPR_HID4, h->hatch_hid4); 1474 mtspr64(SPR_HID5, h->hatch_hid5); 1475 mtspr64(SPR_HIOR, 0); 1476 } else 1477 #endif 1478 mtspr(SPR_HID0, h->hatch_hid0); 1479 1480 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1481 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1482 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1483 } 1484 1485 __asm volatile ("sync"); 1486 for (i = 0; i < 16; i++) 1487 __asm ("mtsrin %0,%1" :: "r"(h->hatch_sr[i]), "r"(i << ADDR_SR_SHFT)); 1488 __asm volatile ("sync; isync"); 1489 1490 if (oeacpufeat & OEACPU_64) 1491 mtspr(SPR_ASR, h->hatch_asr); 1492 1493 cpu_spinstart_ack = 1; 1494 __asm ("ptesync"); 1495 __asm ("mtsdr1 %0" :: "r"(h->hatch_sdr1)); 1496 __asm volatile ("sync; isync"); 1497 1498 cpu_spinstart_ack = 5; 1499 for (i = 0; i < 16; i++) 1500 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1501 "r"(i << ADDR_SR_SHFT)); 1502 1503 /* Enable I/D address translations. */ 1504 msr = mfmsr(); 1505 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1506 mtmsr(msr); 1507 __asm volatile ("sync; isync"); 1508 cpu_spinstart_ack = 2; 1509 1510 md_sync_timebase(h); 1511 1512 cpu_setup(h->hatch_self, ci); 1513 1514 h->hatch_running = 1; 1515 __asm volatile ("sync; isync"); 1516 1517 while (start_secondary_cpu == 0) 1518 ; 1519 1520 __asm volatile ("sync; isync"); 1521 1522 aprint_normal("cpu%d started\n", curcpu()->ci_index); 1523 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1524 1525 md_setup_interrupts(); 1526 1527 ci->ci_ipending = 0; 1528 ci->ci_cpl = 0; 1529 1530 mtmsr(mfmsr() | PSL_EE); 1531 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1532 return pcb->pcb_sp; 1533 } 1534 1535 void 1536 cpu_boot_secondary_processors(void) 1537 { 1538 start_secondary_cpu = 1; 1539 __asm volatile ("sync"); 1540 } 1541 1542 #endif /*MULTIPROCESSOR*/ 1543
Indexes created Thu Oct 02 07:10:07 GMT 2025