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      1 /* $NetBSD: jh7100.dtsi,v 1.2 2024/10/24 12:03:16 skrll Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2024 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Nick Hudson
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include "../../../external/gpl2/dts/dist/include/dt-bindings/clock/starfive-jh7100-audio.h"
     33 
     34 / {
     35 	soc {
     36 		audclk: clock-controller@10480000 {
     37 			compatible = "starfive,jh7100-audclk";
     38 			reg = <0x0 0x10480000 0x0 0x10000>;
     39 			clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
     40 				 <&clkgen JH7100_CLK_AUDIO_12288>,
     41 				 <&clkgen JH7100_CLK_DOM7AHB_BUS>;
     42 			clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
     43 			#clock-cells = <1>;
     44 		};
     45 
     46 		audrst: reset-controller@10490000 {
     47 			compatible = "starfive,jh7100-audrst";
     48 			reg = <0x0 0x10490000 0x0 0x10000>;
     49 			#reset-cells = <1>;
     50 		};
     51 
     52 		sysaudio: syscon@104a0000 {
     53 			compatible = "starfive,jh7100-sysaudio", "syscon";
     54 			reg = <0x0 0x104a0000 0x0 0x10000>;
     55 		};
     56 
     57 		usb3: usb@104c0000 {
     58 			compatible = "starfive,jh7100-usb";
     59 			ranges = <0x0 0x0 0x104c0000 0x100000>;
     60 			#address-cells = <1>;
     61 			#size-cells = <1>;
     62 			clocks = <&audclk JH7100_AUDCLK_USB_LPM>,
     63 			         <&audclk JH7100_AUDCLK_USB_STB>,
     64 			         <&clkgen JH7100_CLK_USB_AXI>,
     65 			         <&clkgen JH7100_CLK_USBNOC_AXI>;
     66 			clock-names = "lpm", "stb", "axi", "nocaxi";
     67 			resets = <&rstgen JH7100_RSTN_USB_AXI>,
     68 			         <&rstgen JH7100_RSTN_USBNOC_AXI>;
     69 			reset-names = "axi", "nocaxi";
     70 			starfive,syscon = <&sysaudio>;
     71 			status = "disabled";
     72 
     73 			usb_cdns3: usb@0 {
     74 				compatible = "cdns,usb3";
     75 				reg = <0x00000 0x10000>,
     76 				      <0x10000 0x10000>,
     77 				      <0x20000 0x10000>;
     78 				reg-names = "otg", "xhci", "dev";
     79 				interrupts = <44>, <52>, <43>;
     80 				interrupt-names = "host", "peripheral", "otg";
     81 			};
     82 		};
     83 	};
     84 };
     85 
     86 
     87 &sdio0 {
     88 	max-frequency = <10000000>;
     89 };
     90 
     91 
     92 &sdio1 {
     93 	max-frequency = <50000000>;
     94 };
     95 
     96