clint_fdt.c revision 1.2 1 1.2 skrll /* $NetBSD: clint_fdt.c,v 1.2 2023/07/26 06:36:34 skrll Exp $ */
2 1.1 skrll
3 1.1 skrll /*-
4 1.1 skrll * Copyright (c) 2023 The NetBSD Foundation, Inc.
5 1.1 skrll * All rights reserved.
6 1.1 skrll *
7 1.1 skrll * This code is derived from software contributed to The NetBSD Foundation
8 1.1 skrll * by Nick Hudson
9 1.1 skrll *
10 1.1 skrll * Redistribution and use in source and binary forms, with or without
11 1.1 skrll * modification, are permitted provided that the following conditions
12 1.1 skrll * are met:
13 1.1 skrll * 1. Redistributions of source code must retain the above copyright
14 1.1 skrll * notice, this list of conditions and the following disclaimer.
15 1.1 skrll * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 skrll * notice, this list of conditions and the following disclaimer in the
17 1.1 skrll * documentation and/or other materials provided with the distribution.
18 1.1 skrll *
19 1.1 skrll * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 skrll * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 skrll * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 skrll * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 skrll * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 skrll * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 skrll * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 skrll * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 skrll * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 skrll * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 skrll * POSSIBILITY OF SUCH DAMAGE.
30 1.1 skrll */
31 1.1 skrll
32 1.1 skrll #include <sys/cdefs.h>
33 1.2 skrll __KERNEL_RCSID(0, "$NetBSD: clint_fdt.c,v 1.2 2023/07/26 06:36:34 skrll Exp $");
34 1.1 skrll
35 1.1 skrll #include <sys/param.h>
36 1.1 skrll
37 1.1 skrll #include <sys/bus.h>
38 1.1 skrll #include <sys/cpu.h>
39 1.1 skrll #include <sys/device.h>
40 1.1 skrll #include <sys/evcnt.h>
41 1.1 skrll #include <sys/intr.h>
42 1.1 skrll
43 1.1 skrll #include <dev/fdt/fdtvar.h>
44 1.1 skrll
45 1.1 skrll #include <riscv/fdt/riscv_fdtvar.h>
46 1.1 skrll
47 1.1 skrll #include <machine/sysreg.h>
48 1.1 skrll
49 1.1 skrll
50 1.1 skrll #define CLINT_MSIP_HARTN(n) 0x0000 + 4 * (n)
51 1.1 skrll #define CLINT_MTIMECMP_HARTN(n) 0x4000 + 8 * (n)
52 1.1 skrll #define CLINT_MTIME 0xbff8
53 1.1 skrll #define CLINT_MTIME_LO CLINT_MTIME + 0x0
54 1.1 skrll #define CLINT_MTIME_HI CLINT_MTIME + 0x4
55 1.1 skrll
56 1.1 skrll static const struct device_compatible_entry compat_data[] = {
57 1.1 skrll { .compat = "riscv,clint0" },
58 1.1 skrll DEVICE_COMPAT_EOL
59 1.1 skrll };
60 1.1 skrll
61 1.1 skrll struct clint_fdt_softc {
62 1.1 skrll device_t sc_dev;
63 1.1 skrll bus_space_tag_t sc_bst;
64 1.1 skrll bus_space_handle_t sc_bsh;
65 1.1 skrll
66 1.1 skrll uint64_t sc_timebase_frequency;
67 1.1 skrll uint64_t sc_ticks_per_hz;
68 1.1 skrll };
69 1.1 skrll
70 1.1 skrll static struct clint_fdt_softc *clint_sc;
71 1.1 skrll
72 1.1 skrll #define CLINT_READ(sc, reg) \
73 1.1 skrll bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
74 1.1 skrll #define CLINT_WRITE(sc, reg, val) \
75 1.1 skrll bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
76 1.1 skrll
77 1.1 skrll static int
78 1.1 skrll clint_ipi_handler(void *arg)
79 1.1 skrll {
80 1.1 skrll cpu_Debugger();
81 1.1 skrll return 1;
82 1.1 skrll }
83 1.1 skrll
84 1.1 skrll
85 1.1 skrll static uint64_t
86 1.1 skrll clint_time_read(struct clint_fdt_softc *sc)
87 1.1 skrll {
88 1.1 skrll #if _LP64
89 1.1 skrll return bus_space_read_8(sc->sc_bst, sc->sc_bsh, CLINT_MTIME);
90 1.1 skrll #else
91 1.1 skrll uint32_t hi, lo;
92 1.1 skrll do {
93 1.1 skrll hi = CLINT_READ(sc, CLINT_MTIME_HI);
94 1.1 skrll lo = CLINT_READ(sc, CLINT_MTIME_LO);
95 1.1 skrll
96 1.1 skrll } while (hi != CLINT_READ(sc, CLINT_MTIME_HI));
97 1.1 skrll return
98 1.1 skrll __SHIFTIN(hi, __BITS(63, 32)) |
99 1.1 skrll __SHIFTIN(lo, __BITS(31, 0));
100 1.1 skrll #endif
101 1.1 skrll }
102 1.1 skrll
103 1.1 skrll
104 1.1 skrll static void
105 1.1 skrll clint_timer_set(struct clint_fdt_softc *sc, struct cpu_info *ci)
106 1.1 skrll {
107 1.1 skrll const uint64_t now = clint_time_read(sc);
108 1.1 skrll
109 1.1 skrll ci->ci_lastintr = now;
110 1.1 skrll ci->ci_ev_timer.ev_count++;
111 1.1 skrll
112 1.1 skrll ci->ci_lastintr_scheduled += sc->sc_ticks_per_hz;
113 1.1 skrll
114 1.1 skrll CLINT_WRITE(sc, CLINT_MTIMECMP_HARTN(ci->ci_cpuid),
115 1.1 skrll ci->ci_lastintr_scheduled);
116 1.1 skrll }
117 1.1 skrll
118 1.1 skrll static int
119 1.1 skrll clint_timer_intr(void *arg)
120 1.1 skrll {
121 1.1 skrll struct cpu_info * const ci = curcpu();
122 1.1 skrll struct clockframe * const cf = arg;
123 1.1 skrll struct clint_fdt_softc * const sc = clint_sc;
124 1.1 skrll
125 1.1 skrll csr_sip_clear(SIP_STIP); /* clean pending interrupt status */
126 1.1 skrll
127 1.1 skrll clint_timer_set(sc, ci);
128 1.1 skrll
129 1.1 skrll hardclock(cf);
130 1.1 skrll
131 1.1 skrll return 1;
132 1.1 skrll }
133 1.1 skrll
134 1.1 skrll static void
135 1.1 skrll clint_cpu_initclocks(void)
136 1.1 skrll {
137 1.1 skrll struct cpu_info * const ci = curcpu();
138 1.1 skrll struct clint_fdt_softc * const sc = clint_sc;
139 1.1 skrll
140 1.1 skrll clint_timer_set(sc, ci);
141 1.1 skrll
142 1.1 skrll csr_sie_set(SIE_STIE); /* enable supervisor timer intr */
143 1.1 skrll }
144 1.1 skrll
145 1.1 skrll static int
146 1.1 skrll clint_match(device_t parent, cfdata_t cf, void *aux)
147 1.1 skrll {
148 1.1 skrll struct fdt_attach_args * const faa = aux;
149 1.1 skrll
150 1.1 skrll return of_compatible_match(faa->faa_phandle, compat_data);
151 1.1 skrll }
152 1.1 skrll
153 1.1 skrll static void
154 1.1 skrll clint_attach(device_t parent, device_t self, void *aux)
155 1.1 skrll {
156 1.1 skrll struct clint_fdt_softc * const sc = device_private(self);
157 1.1 skrll const struct fdt_attach_args * const faa = aux;
158 1.1 skrll const int phandle = faa->faa_phandle;
159 1.1 skrll bus_addr_t addr;
160 1.1 skrll bus_size_t size;
161 1.1 skrll
162 1.1 skrll if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
163 1.1 skrll aprint_error(": couldn't get registers\n");
164 1.1 skrll return;
165 1.1 skrll }
166 1.1 skrll
167 1.1 skrll const int cpus = OF_finddevice("/cpus");
168 1.1 skrll if (cpus == -1) {
169 1.1 skrll aprint_error(": couldn't get 'cpus' node\n");
170 1.1 skrll return;
171 1.1 skrll }
172 1.1 skrll
173 1.1 skrll uint32_t tbfreq;
174 1.1 skrll int ret = of_getprop_uint32(cpus, "timebase-frequency", &tbfreq);
175 1.1 skrll if (ret < 0) {
176 1.1 skrll aprint_error(": can't get timebase frequency\n");
177 1.1 skrll return;
178 1.1 skrll }
179 1.1 skrll
180 1.1 skrll sc->sc_dev = self;
181 1.1 skrll sc->sc_bst = faa->faa_bst;
182 1.1 skrll sc->sc_timebase_frequency = tbfreq;
183 1.1 skrll
184 1.1 skrll if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
185 1.1 skrll aprint_error(": couldn't map registers\n");
186 1.1 skrll return;
187 1.1 skrll }
188 1.1 skrll
189 1.1 skrll printf("%s: addr %#" PRIxBUSADDR " size %#" PRIxBUSSIZE "\n", __func__,
190 1.1 skrll addr, size);
191 1.1 skrll
192 1.1 skrll aprint_naive("\n");
193 1.1 skrll aprint_normal(": local interrupt control. %" PRId64 " KHz timer.\n",
194 1.1 skrll sc->sc_timebase_frequency / 1000);
195 1.1 skrll
196 1.1 skrll sc->sc_ticks_per_hz = sc->sc_timebase_frequency / hz;
197 1.1 skrll int len;
198 1.1 skrll const uint32_t *data =
199 1.1 skrll fdtbus_get_prop(phandle, "interrupts-extended", &len);
200 1.1 skrll if (data == NULL) {
201 1.1 skrll aprint_error_dev(self, "couldn't get context data\n");
202 1.1 skrll return;
203 1.1 skrll }
204 1.1 skrll
205 1.1 skrll clint_sc = sc;
206 1.1 skrll // riscv_fdt_timer_register(clint_cpu_initclocks);
207 1.1 skrll
208 1.1 skrll int context = 0;
209 1.1 skrll while (len > 0) {
210 1.1 skrll const int pphandle = be32toh(data[0]);
211 1.1 skrll const int xref = fdtbus_get_phandle_from_native(pphandle);
212 1.1 skrll const int intr_source = be32toh(data[1]);
213 1.1 skrll uint32_t intr_cells;
214 1.1 skrll
215 1.1 skrll int error =
216 1.1 skrll of_getprop_uint32(xref, "#interrupt-cells", &intr_cells);
217 1.1 skrll if (error) {
218 1.1 skrll aprint_error_dev(self, "couldn't get cell length "
219 1.1 skrll "for parent CPU for context %d", context);
220 1.1 skrll return;
221 1.1 skrll }
222 1.1 skrll int (*handler)(void *) = NULL;
223 1.1 skrll void *arg = NULL;
224 1.1 skrll int ipl = IPL_HIGH;
225 1.1 skrll switch (intr_source) {
226 1.1 skrll case IRQ_MACHINE_SOFTWARE:
227 1.1 skrll handler = clint_ipi_handler;
228 1.1 skrll arg = sc;
229 1.1 skrll break;
230 1.1 skrll case IRQ_MACHINE_TIMER:
231 1.1 skrll handler = clint_timer_intr;
232 1.1 skrll arg = NULL; /* clock frame */
233 1.1 skrll ipl = IPL_SCHED;
234 1.1 skrll break;
235 1.1 skrll default:
236 1.1 skrll aprint_error_dev(self, "unknown interrupt source %d",
237 1.1 skrll intr_source);
238 1.1 skrll }
239 1.1 skrll
240 1.1 skrll if (handler) {
241 1.1 skrll void *ih = fdtbus_intr_establish_xname(phandle,
242 1.1 skrll context, ipl, FDT_INTR_MPSAFE,
243 1.1 skrll handler, arg, device_xname(self));
244 1.1 skrll if (ih == NULL) {
245 1.1 skrll aprint_error_dev(self, "couldn't install "
246 1.1 skrll "interrupt handler\n");
247 1.1 skrll } else {
248 1.1 skrll char intrstr[128];
249 1.1 skrll bool ok = fdtbus_intr_str(phandle, context,
250 1.1 skrll intrstr, sizeof(intrstr));
251 1.1 skrll aprint_verbose_dev(self, "interrupt %s handler "
252 1.1 skrll "installed\n", ok ? intrstr : "(unk)");
253 1.1 skrll }
254 1.1 skrll }
255 1.1 skrll
256 1.1 skrll len -= (intr_cells + 1) * 4;
257 1.1 skrll data += (intr_cells + 1);
258 1.1 skrll context++;
259 1.1 skrll }
260 1.1 skrll }
261 1.1 skrll
262 1.1 skrll CFATTACH_DECL_NEW(clint_fdt, sizeof(struct clint_fdt_softc),
263 1.1 skrll clint_match, clint_attach, NULL, NULL);
264