clint_fdt.c revision 1.1
1 /* $NetBSD: clint_fdt.c,v 1.1 2023/05/07 12:41:48 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2023 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: clint_fdt.c,v 1.1 2023/05/07 12:41:48 skrll Exp $"); 34 35 #include <sys/param.h> 36 37 #include <sys/bus.h> 38 #include <sys/cpu.h> 39 #include <sys/device.h> 40 #include <sys/evcnt.h> 41 #include <sys/intr.h> 42 43 #include <dev/fdt/fdtvar.h> 44 45 #include <riscv/fdt/riscv_fdtvar.h> 46 47 #include <machine/sysreg.h> 48 49 50 #define CLINT_MSIP_HARTN(n) 0x0000 + 4 * (n) 51 #define CLINT_MTIMECMP_HARTN(n) 0x4000 + 8 * (n) 52 #define CLINT_MTIME 0xbff8 53 #define CLINT_MTIME_LO CLINT_MTIME + 0x0 54 #define CLINT_MTIME_HI CLINT_MTIME + 0x4 55 56 static const struct device_compatible_entry compat_data[] = { 57 { .compat = "riscv,clint0" }, 58 DEVICE_COMPAT_EOL 59 }; 60 61 struct clint_fdt_softc { 62 device_t sc_dev; 63 bus_space_tag_t sc_bst; 64 bus_space_handle_t sc_bsh; 65 66 uint64_t sc_timebase_frequency; 67 uint64_t sc_ticks_per_hz; 68 }; 69 70 static struct clint_fdt_softc *clint_sc; 71 72 #define CLINT_READ(sc, reg) \ 73 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 74 #define CLINT_WRITE(sc, reg, val) \ 75 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 76 77 static int 78 clint_ipi_handler(void *arg) 79 { 80 cpu_Debugger(); 81 return 1; 82 } 83 84 85 static uint64_t 86 clint_time_read(struct clint_fdt_softc *sc) 87 { 88 #if _LP64 89 return bus_space_read_8(sc->sc_bst, sc->sc_bsh, CLINT_MTIME); 90 #else 91 uint32_t hi, lo; 92 do { 93 hi = CLINT_READ(sc, CLINT_MTIME_HI); 94 lo = CLINT_READ(sc, CLINT_MTIME_LO); 95 96 } while (hi != CLINT_READ(sc, CLINT_MTIME_HI)); 97 return 98 __SHIFTIN(hi, __BITS(63, 32)) | 99 __SHIFTIN(lo, __BITS(31, 0)); 100 #endif 101 } 102 103 104 static void 105 clint_timer_set(struct clint_fdt_softc *sc, struct cpu_info *ci) 106 { 107 const uint64_t now = clint_time_read(sc); 108 109 ci->ci_lastintr = now; 110 ci->ci_ev_timer.ev_count++; 111 112 ci->ci_lastintr_scheduled += sc->sc_ticks_per_hz; 113 114 CLINT_WRITE(sc, CLINT_MTIMECMP_HARTN(ci->ci_cpuid), 115 ci->ci_lastintr_scheduled); 116 } 117 118 static int 119 clint_timer_intr(void *arg) 120 { 121 struct cpu_info * const ci = curcpu(); 122 struct clockframe * const cf = arg; 123 struct clint_fdt_softc * const sc = clint_sc; 124 125 printf_nolog("%s: sip %#" PRIxPTR "\n", __func__, csr_sip_read()); 126 127 csr_sip_clear(SIP_STIP); /* clean pending interrupt status */ 128 129 clint_timer_set(sc, ci); 130 131 hardclock(cf); 132 133 return 1; 134 } 135 136 static void 137 clint_cpu_initclocks(void) 138 { 139 struct cpu_info * const ci = curcpu(); 140 struct clint_fdt_softc * const sc = clint_sc; 141 142 clint_timer_set(sc, ci); 143 144 csr_sie_set(SIE_STIE); /* enable supervisor timer intr */ 145 146 printf("init clocks at time %"PRId64"\n", 147 ci->ci_lastintr); 148 } 149 150 static int 151 clint_match(device_t parent, cfdata_t cf, void *aux) 152 { 153 struct fdt_attach_args * const faa = aux; 154 155 return of_compatible_match(faa->faa_phandle, compat_data); 156 } 157 158 static void 159 clint_attach(device_t parent, device_t self, void *aux) 160 { 161 struct clint_fdt_softc * const sc = device_private(self); 162 const struct fdt_attach_args * const faa = aux; 163 const int phandle = faa->faa_phandle; 164 bus_addr_t addr; 165 bus_size_t size; 166 167 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 168 aprint_error(": couldn't get registers\n"); 169 return; 170 } 171 172 const int cpus = OF_finddevice("/cpus"); 173 if (cpus == -1) { 174 aprint_error(": couldn't get 'cpus' node\n"); 175 return; 176 } 177 178 uint32_t tbfreq; 179 int ret = of_getprop_uint32(cpus, "timebase-frequency", &tbfreq); 180 if (ret < 0) { 181 aprint_error(": can't get timebase frequency\n"); 182 return; 183 } 184 185 sc->sc_dev = self; 186 sc->sc_bst = faa->faa_bst; 187 sc->sc_timebase_frequency = tbfreq; 188 189 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 190 aprint_error(": couldn't map registers\n"); 191 return; 192 } 193 194 printf("%s: addr %#" PRIxBUSADDR " size %#" PRIxBUSSIZE "\n", __func__, 195 addr, size); 196 197 aprint_naive("\n"); 198 aprint_normal(": local interrupt control. %" PRId64 " KHz timer.\n", 199 sc->sc_timebase_frequency / 1000); 200 201 sc->sc_ticks_per_hz = sc->sc_timebase_frequency / hz; 202 int len; 203 const uint32_t *data = 204 fdtbus_get_prop(phandle, "interrupts-extended", &len); 205 if (data == NULL) { 206 aprint_error_dev(self, "couldn't get context data\n"); 207 return; 208 } 209 210 clint_sc = sc; 211 // riscv_fdt_timer_register(clint_cpu_initclocks); 212 213 int context = 0; 214 while (len > 0) { 215 const int pphandle = be32toh(data[0]); 216 const int xref = fdtbus_get_phandle_from_native(pphandle); 217 const int intr_source = be32toh(data[1]); 218 uint32_t intr_cells; 219 220 int error = 221 of_getprop_uint32(xref, "#interrupt-cells", &intr_cells); 222 if (error) { 223 aprint_error_dev(self, "couldn't get cell length " 224 "for parent CPU for context %d", context); 225 return; 226 } 227 int (*handler)(void *) = NULL; 228 void *arg = NULL; 229 int ipl = IPL_HIGH; 230 switch (intr_source) { 231 case IRQ_MACHINE_SOFTWARE: 232 handler = clint_ipi_handler; 233 arg = sc; 234 break; 235 case IRQ_MACHINE_TIMER: 236 handler = clint_timer_intr; 237 arg = NULL; /* clock frame */ 238 ipl = IPL_SCHED; 239 break; 240 default: 241 aprint_error_dev(self, "unknown interrupt source %d", 242 intr_source); 243 } 244 245 if (handler) { 246 void *ih = fdtbus_intr_establish_xname(phandle, 247 context, ipl, FDT_INTR_MPSAFE, 248 handler, arg, device_xname(self)); 249 if (ih == NULL) { 250 aprint_error_dev(self, "couldn't install " 251 "interrupt handler\n"); 252 } else { 253 char intrstr[128]; 254 bool ok = fdtbus_intr_str(phandle, context, 255 intrstr, sizeof(intrstr)); 256 aprint_verbose_dev(self, "interrupt %s handler " 257 "installed\n", ok ? intrstr : "(unk)"); 258 } 259 } 260 261 len -= (intr_cells + 1) * 4; 262 data += (intr_cells + 1); 263 context++; 264 } 265 } 266 267 CFATTACH_DECL_NEW(clint_fdt, sizeof(struct clint_fdt_softc), 268 clint_match, clint_attach, NULL, NULL); 269
Indexes created Wed Sep 24 05:09:52 GMT 2025