1 /* $NetBSD: pcihost_fdt.c,v 1.1 2025/01/01 17:53:07 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2018 Jared D. McNeill <jmcneill (at) invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: pcihost_fdt.c,v 1.1 2025/01/01 17:53:07 skrll Exp $"); 31 32 #include <sys/param.h> 33 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/kernel.h> 38 #include <sys/kmem.h> 39 #include <sys/lwp.h> 40 #include <sys/mutex.h> 41 #include <sys/queue.h> 42 #include <sys/systm.h> 43 44 #include <machine/cpu.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pciconf.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #include <riscv/fdt/pcihost_fdtvar.h> 53 54 #define PCIHOST_DEFAULT_BUS_MIN 0 55 #define PCIHOST_DEFAULT_BUS_MAX 255 56 57 #define PCIHOST_CACHELINE_SIZE 64 /* riscv_dcache_align */ 58 59 int pcihost_segment = 0; 60 61 static int pcihost_match(device_t, cfdata_t, void *); 62 static void pcihost_attach(device_t, device_t, void *); 63 64 static int pcihost_config(struct pcihost_softc *); 65 66 static void pcihost_attach_hook(device_t, device_t, 67 struct pcibus_attach_args *); 68 static int pcihost_bus_maxdevs(void *, int); 69 static pcitag_t pcihost_make_tag(void *, int, int, int); 70 static void pcihost_decompose_tag(void *, pcitag_t, int *, int *, int *); 71 static u_int pcihost_get_segment(void *); 72 static pcireg_t pcihost_conf_read(void *, pcitag_t, int); 73 static void pcihost_conf_write(void *, pcitag_t, int, pcireg_t); 74 static int pcihost_conf_hook(void *, int, int, int, pcireg_t); 75 static void pcihost_conf_interrupt(void *, int, int, int, int, int *); 76 77 static int pcihost_intr_map(const struct pci_attach_args *, 78 pci_intr_handle_t *); 79 static const char *pcihost_intr_string(void *, pci_intr_handle_t, 80 char *, size_t); 81 static const struct evcnt *pcihost_intr_evcnt(void *, pci_intr_handle_t); 82 static int pcihost_intr_setattr(void *, pci_intr_handle_t *, int, 83 uint64_t); 84 static void * pcihost_intr_establish(void *, pci_intr_handle_t, 85 int, int (*)(void *), void *, 86 const char *); 87 static void pcihost_intr_disestablish(void *, void *); 88 89 static int pcihost_bus_space_map(void *, bus_addr_t, bus_size_t, 90 int, bus_space_handle_t *); 91 92 CFATTACH_DECL_NEW(pcihost_fdt, sizeof(struct pcihost_softc), 93 pcihost_match, pcihost_attach, NULL, NULL); 94 95 static const struct device_compatible_entry compat_data[] = { 96 { .compat = "pci-host-cam-generic", .value = PCIHOST_CAM }, 97 { .compat = "pci-host-ecam-generic", .value = PCIHOST_ECAM }, 98 DEVICE_COMPAT_EOL 99 }; 100 101 static int 102 pcihost_match(device_t parent, cfdata_t cf, void *aux) 103 { 104 struct fdt_attach_args * const faa = aux; 105 106 return of_compatible_match(faa->faa_phandle, compat_data); 107 } 108 109 static void 110 pcihost_attach(device_t parent, device_t self, void *aux) 111 { 112 struct pcihost_softc * const sc = device_private(self); 113 struct fdt_attach_args * const faa = aux; 114 bus_addr_t cs_addr; 115 bus_size_t cs_size; 116 int error; 117 118 if (fdtbus_get_reg(faa->faa_phandle, 0, &cs_addr, &cs_size) != 0) { 119 aprint_error(": couldn't get registers\n"); 120 return; 121 } 122 123 sc->sc_dev = self; 124 sc->sc_dmat = faa->faa_dmat; 125 sc->sc_bst = faa->faa_bst; 126 sc->sc_pci_bst = faa->faa_bst; 127 sc->sc_phandle = faa->faa_phandle; 128 error = bus_space_map(sc->sc_bst, cs_addr, cs_size, 129 0, &sc->sc_bsh); 130 if (error) { 131 aprint_error(": couldn't map registers: %d\n", error); 132 return; 133 } 134 sc->sc_type = of_compatible_lookup(sc->sc_phandle, compat_data)->value; 135 136 aprint_naive("\n"); 137 aprint_normal(": Generic PCI host controller\n"); 138 139 pcihost_init(&sc->sc_pc, sc); 140 pcihost_init2(sc); 141 } 142 143 void 144 pcihost_init2(struct pcihost_softc *sc) 145 { 146 struct pcibus_attach_args pba; 147 const u_int *data; 148 int len; 149 150 if ((data = fdtbus_get_prop(sc->sc_phandle, "bus-range", &len)) != NULL) { 151 if (len != 8) { 152 aprint_error_dev(sc->sc_dev, "malformed 'bus-range' property\n"); 153 return; 154 } 155 sc->sc_bus_min = be32toh(data[0]); 156 sc->sc_bus_max = be32toh(data[1]); 157 } else { 158 sc->sc_bus_min = PCIHOST_DEFAULT_BUS_MIN; 159 sc->sc_bus_max = PCIHOST_DEFAULT_BUS_MAX; 160 } 161 162 /* 163 * Assign a fixed PCI segment ("domain") number. If the property is not 164 * present, assign one. The binding spec says if this property is used to 165 * assign static segment numbers, all host bridges should have segments 166 * astatic assigned to prevent overlaps. 167 */ 168 if (of_getprop_uint32(sc->sc_phandle, "linux,pci-domain", &sc->sc_seg)) 169 sc->sc_seg = pcihost_segment++; 170 171 if (pcihost_config(sc) != 0) 172 return; 173 174 memset(&pba, 0, sizeof(pba)); 175 pba.pba_flags = PCI_FLAGS_MRL_OKAY | 176 PCI_FLAGS_MRM_OKAY | 177 PCI_FLAGS_MWI_OKAY | 178 sc->sc_pci_flags; 179 pba.pba_iot = &sc->sc_io.bst; 180 pba.pba_memt = &sc->sc_mem.bst; 181 pba.pba_dmat = sc->sc_dmat; 182 #ifdef _PCI_HAVE_DMA64 183 pba.pba_dmat64 = sc->sc_dmat; 184 #endif 185 pba.pba_pc = &sc->sc_pc; 186 pba.pba_bus = sc->sc_bus_min; 187 188 config_found(sc->sc_dev, &pba, pcibusprint, 189 CFARGS(.devhandle = device_handle(sc->sc_dev))); 190 } 191 192 void 193 pcihost_init(pci_chipset_tag_t pc, void *priv) 194 { 195 pc->pc_conf_v = priv; 196 pc->pc_attach_hook = pcihost_attach_hook; 197 pc->pc_bus_maxdevs = pcihost_bus_maxdevs; 198 pc->pc_make_tag = pcihost_make_tag; 199 pc->pc_decompose_tag = pcihost_decompose_tag; 200 pc->pc_get_segment = pcihost_get_segment; 201 pc->pc_conf_read = pcihost_conf_read; 202 pc->pc_conf_write = pcihost_conf_write; 203 pc->pc_conf_hook = pcihost_conf_hook; 204 pc->pc_conf_interrupt = pcihost_conf_interrupt; 205 206 pc->pc_intr_v = priv; 207 pc->pc_intr_map = pcihost_intr_map; 208 pc->pc_intr_string = pcihost_intr_string; 209 pc->pc_intr_evcnt = pcihost_intr_evcnt; 210 pc->pc_intr_setattr = pcihost_intr_setattr; 211 pc->pc_intr_establish = pcihost_intr_establish; 212 pc->pc_intr_disestablish = pcihost_intr_disestablish; 213 } 214 215 static int 216 pcihost_config(struct pcihost_softc *sc) 217 { 218 const u_int *ranges; 219 u_int probe_only; 220 int error, len, type; 221 bool swap; 222 223 struct pcih_bus_space * const pibs = &sc->sc_io; 224 pibs->bst = *sc->sc_pci_bst; 225 pibs->bst.bs_cookie = pibs; 226 pibs->map = pibs->bst.bs_map; 227 pibs->flags = PCI_FLAGS_IO_OKAY; 228 pibs->bst.bs_map = pcihost_bus_space_map; 229 230 struct pcih_bus_space * const pmbs = &sc->sc_mem; 231 pmbs->bst = *sc->sc_pci_bst; 232 pmbs->bst.bs_cookie = pmbs; 233 pmbs->map = pmbs->bst.bs_map; 234 pmbs->flags = PCI_FLAGS_MEM_OKAY; 235 pmbs->bst.bs_map = pcihost_bus_space_map; 236 237 /* 238 * If this flag is set, skip configuration of the PCI bus and use 239 * existing config. 240 */ 241 const int chosen = OF_finddevice("/chosen"); 242 if (chosen <= 0 || of_getprop_uint32(chosen, "linux,pci-probe-only", &probe_only)) 243 probe_only = 0; 244 245 if (sc->sc_pci_ranges != NULL) { 246 ranges = sc->sc_pci_ranges; 247 len = sc->sc_pci_ranges_cells * 4; 248 swap = false; 249 } else { 250 ranges = fdtbus_get_prop(sc->sc_phandle, "ranges", &len); 251 if (ranges == NULL) { 252 aprint_error_dev(sc->sc_dev, "missing 'ranges' property\n"); 253 return EINVAL; 254 } 255 swap = true; 256 } 257 struct pciconf_resources *pcires = pciconf_resource_init(); 258 259 /* 260 * Each entry in the ranges table contains: 261 * - bus address (3 cells) 262 * - cpu physical address (2 cells) 263 * - size (2 cells) 264 * Total size for each entry is 28 bytes (7 cells). 265 */ 266 while (len >= 28) { 267 #define DECODE32(x,o) (swap ? be32dec(&(x)[o]) : (x)[o]) 268 #define DECODE64(x,o) (swap ? be64dec(&(x)[o]) : (((uint64_t)((x)[(o)+0]) << 32) + (x)[(o)+1])) 269 const uint32_t phys_hi = DECODE32(ranges, 0); 270 uint64_t bus_phys = DECODE64(ranges, 1); 271 const uint64_t cpu_phys = DECODE64(ranges, 3); 272 uint64_t size = DECODE64(ranges, 5); 273 #undef DECODE32 274 #undef DECODE64 275 276 len -= 28; 277 ranges += 7; 278 279 const bool is64 = (__SHIFTOUT(phys_hi, PHYS_HI_SPACE) == 280 PHYS_HI_SPACE_MEM64) ? true : false; 281 switch (__SHIFTOUT(phys_hi, PHYS_HI_SPACE)) { 282 case PHYS_HI_SPACE_IO: 283 if (pibs->nranges + 1 >= __arraycount(pibs->ranges)) { 284 aprint_error_dev(sc->sc_dev, "too many IO ranges\n"); 285 continue; 286 } 287 pibs->ranges[pibs->nranges].bpci = bus_phys; 288 pibs->ranges[pibs->nranges].bbus = cpu_phys; 289 pibs->ranges[pibs->nranges].size = size; 290 ++pibs->nranges; 291 aprint_verbose_dev(sc->sc_dev, 292 "IO: %#018" PRIx64 " + %#018" PRIx64 " @ %#018" PRIx64 "\n", 293 bus_phys, size, cpu_phys); 294 /* 295 * Reserve a PC-like legacy IO ports range, perhaps 296 * for access to VGA registers. 297 */ 298 if (bus_phys == 0 && size >= 0x10000) { 299 bus_phys += 0x1000; 300 size -= 0x1000; 301 } 302 error = pciconf_resource_add(pcires, 303 PCICONF_RESOURCE_IO, bus_phys, size); 304 if (error == 0) 305 sc->sc_pci_flags |= PCI_FLAGS_IO_OKAY; 306 break; 307 case PHYS_HI_SPACE_MEM64: 308 /* FALLTHROUGH */ 309 case PHYS_HI_SPACE_MEM32: 310 if (pmbs->nranges + 1 >= __arraycount(pmbs->ranges)) { 311 aprint_error_dev(sc->sc_dev, "too many mem ranges\n"); 312 continue; 313 } 314 /* both pmem and mem spaces are in the same tag */ 315 pmbs->ranges[pmbs->nranges].bpci = bus_phys; 316 pmbs->ranges[pmbs->nranges].bbus = cpu_phys; 317 pmbs->ranges[pmbs->nranges].size = size; 318 ++pmbs->nranges; 319 if ((phys_hi & PHYS_HI_PREFETCH) != 0 || 320 __SHIFTOUT(phys_hi, PHYS_HI_SPACE) == PHYS_HI_SPACE_MEM64) { 321 type = PCICONF_RESOURCE_PREFETCHABLE_MEM; 322 aprint_verbose_dev(sc->sc_dev, 323 "MMIO (%d-bit prefetchable) : %#018" PRIx64 " + %#018" PRIx64 " @ %#018" PRIx64 "\n", 324 is64 ? 64 : 32, bus_phys, size, cpu_phys); 325 } else { 326 type = PCICONF_RESOURCE_MEM; 327 aprint_verbose_dev(sc->sc_dev, 328 "MMIO (%d-bit non-prefetchable): %#018" PRIx64 " + %#018" PRIx64 " @ %#018" PRIx64 "\n", 329 is64 ? 64 : 32, bus_phys, size, cpu_phys); 330 } 331 error = pciconf_resource_add(pcires, type, bus_phys, 332 size); 333 if (error == 0) 334 sc->sc_pci_flags |= PCI_FLAGS_MEM_OKAY; 335 break; 336 default: 337 break; 338 } 339 } 340 341 if (probe_only) { 342 error = 0; 343 } else { 344 error = pci_configure_bus(&sc->sc_pc, pcires, sc->sc_bus_min, 345 PCIHOST_CACHELINE_SIZE); 346 } 347 348 pciconf_resource_fini(pcires); 349 if (error) { 350 aprint_error_dev(sc->sc_dev, "configuration failed: %d\n", error); 351 return error; 352 } 353 354 return 0; 355 } 356 357 static void 358 pcihost_attach_hook(device_t parent, device_t self, 359 struct pcibus_attach_args *pba) 360 { 361 } 362 363 static int 364 pcihost_bus_maxdevs(void *v, int busno) 365 { 366 return 32; 367 } 368 369 static pcitag_t 370 pcihost_make_tag(void *v, int b, int d, int f) 371 { 372 return (b << 16) | (d << 11) | (f << 8); 373 } 374 375 static void 376 pcihost_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp) 377 { 378 if (bp) 379 *bp = (tag >> 16) & 0xff; 380 if (dp) 381 *dp = (tag >> 11) & 0x1f; 382 if (fp) 383 *fp = (tag >> 8) & 0x7; 384 } 385 386 static u_int 387 pcihost_get_segment(void *v) 388 { 389 struct pcihost_softc *sc = v; 390 391 return sc->sc_seg; 392 } 393 394 static pcireg_t 395 pcihost_conf_read(void *v, pcitag_t tag, int offset) 396 { 397 struct pcihost_softc *sc = v; 398 int b, d, f; 399 u_int reg; 400 401 pcihost_decompose_tag(v, tag, &b, &d, &f); 402 403 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 404 return (pcireg_t) -1; 405 406 if (sc->sc_type == PCIHOST_CAM) { 407 if (offset & ~0xff) 408 return (pcireg_t) -1; 409 reg = (b << 16) | (d << 11) | (f << 8) | offset; 410 } else if (sc->sc_type == PCIHOST_ECAM) { 411 if (offset & ~0xfff) 412 return (pcireg_t) -1; 413 reg = (b << 20) | (d << 15) | (f << 12) | offset; 414 } else { 415 return (pcireg_t) -1; 416 } 417 418 return bus_space_read_4(sc->sc_bst, sc->sc_bsh, reg); 419 } 420 421 static void 422 pcihost_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val) 423 { 424 struct pcihost_softc *sc = v; 425 int b, d, f; 426 u_int reg; 427 428 pcihost_decompose_tag(v, tag, &b, &d, &f); 429 430 if (b < sc->sc_bus_min || b > sc->sc_bus_max) 431 return; 432 433 if (sc->sc_type == PCIHOST_CAM) { 434 if (offset & ~0xff) 435 return; 436 reg = (b << 16) | (d << 11) | (f << 8) | offset; 437 } else if (sc->sc_type == PCIHOST_ECAM) { 438 if (offset & ~0xfff) 439 return; 440 reg = (b << 20) | (d << 15) | (f << 12) | offset; 441 } else { 442 return; 443 } 444 445 bus_space_write_4(sc->sc_bst, sc->sc_bsh, reg, val); 446 } 447 448 static int 449 pcihost_conf_hook(void *v, int b, int d, int f, pcireg_t id) 450 { 451 return PCI_CONF_DEFAULT; 452 } 453 454 static void 455 pcihost_conf_interrupt(void *v, int bus, int dev, int ipin, int swiz, int *ilinep) 456 { 457 } 458 459 static int 460 pcihost_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ih) 461 { 462 struct pcihost_softc *sc = pa->pa_pc->pc_intr_v; 463 u_int addr_cells, interrupt_cells; 464 const u_int *imap, *imask; 465 int imaplen, imasklen; 466 u_int match[4]; 467 int index; 468 469 if (pa->pa_intrpin == 0) 470 return EINVAL; 471 472 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 473 imask = fdtbus_get_prop(sc->sc_phandle, "interrupt-map-mask", &imasklen); 474 if (imap == NULL || imask == NULL || imasklen != 16) 475 return EINVAL; 476 477 /* Convert attach args to specifier */ 478 match[0] = htobe32( 479 __SHIFTIN(pa->pa_bus, PHYS_HI_BUS) | 480 __SHIFTIN(pa->pa_device, PHYS_HI_DEVICE) | 481 __SHIFTIN(pa->pa_function, PHYS_HI_FUNCTION) 482 ) & imask[0]; 483 match[1] = htobe32(0) & imask[1]; 484 match[2] = htobe32(0) & imask[2]; 485 match[3] = htobe32(pa->pa_intrpin) & imask[3]; 486 487 index = 0; 488 while (imaplen >= 20) { 489 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 490 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 491 addr_cells = 2; 492 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 493 interrupt_cells = 0; 494 if (imaplen < (addr_cells + interrupt_cells) * 4) 495 return ENXIO; 496 497 if ((imap[0] & imask[0]) == match[0] && 498 (imap[1] & imask[1]) == match[1] && 499 (imap[2] & imask[2]) == match[2] && 500 (imap[3] & imask[3]) == match[3]) { 501 *ih = index; 502 return 0; 503 } 504 505 imap += (5 + addr_cells + interrupt_cells); 506 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 507 index++; 508 } 509 510 return EINVAL; 511 } 512 513 static const u_int * 514 pcihost_find_intr(struct pcihost_softc *sc, pci_intr_handle_t ih, int *pihandle) 515 { 516 u_int addr_cells, interrupt_cells; 517 int imaplen, index; 518 const u_int *imap; 519 520 imap = fdtbus_get_prop(sc->sc_phandle, "interrupt-map", &imaplen); 521 KASSERT(imap != NULL); 522 523 index = 0; 524 while (imaplen >= 20) { 525 const int map_ihandle = fdtbus_get_phandle_from_native(be32toh(imap[4])); 526 if (of_getprop_uint32(map_ihandle, "#address-cells", &addr_cells)) 527 addr_cells = 2; 528 if (of_getprop_uint32(map_ihandle, "#interrupt-cells", &interrupt_cells)) 529 interrupt_cells = 0; 530 if (imaplen < (addr_cells + interrupt_cells) * 4) 531 return NULL; 532 533 if (index == ih) { 534 *pihandle = map_ihandle; 535 return imap + 5 + addr_cells; 536 } 537 538 imap += (5 + addr_cells + interrupt_cells); 539 imaplen -= (5 + addr_cells + interrupt_cells) * 4; 540 index++; 541 } 542 543 return NULL; 544 } 545 546 static const char * 547 pcihost_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 548 { 549 const int irq = __SHIFTOUT(ih, RISCV_PCI_INTR_IRQ); 550 const int vec = __SHIFTOUT(ih, RISCV_PCI_INTR_MSI_VEC); 551 struct pcihost_softc *sc = v; 552 const u_int *specifier; 553 int ihandle; 554 555 if (ih & RISCV_PCI_INTR_MSIX) { 556 snprintf(buf, len, "irq %d (MSI-X vec %d)", irq, vec); 557 } else if (ih & RISCV_PCI_INTR_MSI) { 558 snprintf(buf, len, "irq %d (MSI vec %d)", irq, vec); 559 } else { 560 specifier = pcihost_find_intr(sc, ih & RISCV_PCI_INTR_IRQ, &ihandle); 561 if (specifier == NULL) 562 return NULL; 563 564 if (!fdtbus_intr_str_raw(ihandle, specifier, buf, len)) 565 return NULL; 566 } 567 568 return buf; 569 } 570 571 const struct evcnt * 572 pcihost_intr_evcnt(void *v, pci_intr_handle_t ih) 573 { 574 return NULL; 575 } 576 577 static int 578 pcihost_intr_setattr(void *v, pci_intr_handle_t *ih, int attr, uint64_t data) 579 { 580 switch (attr) { 581 case PCI_INTR_MPSAFE: 582 if (data) 583 *ih |= RISCV_PCI_INTR_MPSAFE; 584 else 585 *ih &= ~RISCV_PCI_INTR_MPSAFE; 586 return 0; 587 default: 588 return ENODEV; 589 } 590 } 591 592 static void * 593 pcihost_intr_establish(void *v, pci_intr_handle_t pih, int ipl, 594 int (*callback)(void *), void *arg, const char *xname) 595 { 596 struct pcihost_softc *sc = v; 597 const int flags = (pih & RISCV_PCI_INTR_MPSAFE) ? FDT_INTR_MPSAFE : 0; 598 const u_int *specifier; 599 int ihandle; 600 601 specifier = pcihost_find_intr(sc, pih & RISCV_PCI_INTR_IRQ, &ihandle); 602 603 if (specifier == NULL) 604 return NULL; 605 606 return fdtbus_intr_establish_raw(ihandle, specifier, ipl, flags, 607 callback, arg, xname); 608 } 609 610 static void 611 pcihost_intr_disestablish(void *v, void *vih) 612 { 613 struct pcihost_softc *sc = v; 614 615 fdtbus_intr_disestablish(sc->sc_phandle, vih); 616 } 617 618 static int 619 pcihost_bus_space_map(void *t, bus_addr_t bpa, bus_size_t size, int flag, 620 bus_space_handle_t *bshp) 621 { 622 struct pcih_bus_space * const pbs = t; 623 624 for (size_t i = 0; i < pbs->nranges; i++) { 625 const bus_addr_t rmin = pbs->ranges[i].bpci; 626 const bus_addr_t rmax = pbs->ranges[i].bpci - 1 + pbs->ranges[i].size; 627 if ((bpa >= rmin) && ((bpa - 1 + size) <= rmax)) { 628 return pbs->map(t, bpa - pbs->ranges[i].bpci + pbs->ranges[i].bbus, size, flag, bshp); 629 } 630 } 631 632 return ERANGE; 633 } 634
Indexes created Sat Sep 20 22:09:52 GMT 2025