1 /* $NetBSD: bus_defs.h,v 1.4 2024/08/04 08:16:25 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Charles M. Hannum. All rights reserved. 35 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Christopher G. Demetriou 48 * for the NetBSD Project. 49 * 4. The name of the author may not be used to endorse or promote products 50 * derived from this software without specific prior written permission 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 */ 63 64 #ifndef _RISCV_BUS_DEFS_H_ 65 #define _RISCV_BUS_DEFS_H_ 66 67 /* 68 * Addresses (in bus space). 69 */ 70 typedef paddr_t bus_addr_t; 71 typedef u_long bus_size_t; 72 73 #define PRIxBUSADDR PRIxPADDR 74 #define PRIxBUSSIZE "lx" 75 #define PRIuBUSSIZE "lu" 76 77 /* 78 * Access methods for bus space. 79 */ 80 typedef struct bus_space *bus_space_tag_t; 81 typedef uintptr_t bus_space_handle_t; 82 83 #define PRIxBSH PRIxPTR 84 85 /* 86 * int bus_space_map(bus_space_tag_t t, bus_addr_t addr, 87 * bus_size_t size, int flags, bus_space_handle_t *bshp); 88 * 89 * Map a region of bus space. 90 */ 91 #define BUS_SPACE_MAP_BUS1 __BIT(8) 92 #define BUS_SPACE_MAP_BUS2 __BIT(9) 93 #define BUS_SPACE_MAP_BUS3 __BIT(10) 94 #define BUS_SPACE_MAP_BUS4 __BIT(11) 95 96 #define _RISCV_BUS_SPACE_MAP_STRONGLY_ORDERED BUS_SPACE_MAP_BUS1 97 98 struct bus_space { 99 /* cookie */ 100 void *bs_cookie; 101 102 int bs_stride; /* offset <<= bs_stride (if needed) */ 103 int bs_flags; 104 105 /* mapping/unmapping */ 106 int (*bs_map)(void *, bus_addr_t, bus_size_t, 107 int, bus_space_handle_t *); 108 void (*bs_unmap)(void *, bus_space_handle_t, 109 bus_size_t); 110 int (*bs_subregion)(void *, bus_space_handle_t, 111 bus_size_t, bus_size_t, bus_space_handle_t *); 112 113 /* allocation/deallocation */ 114 int (*bs_alloc)(void *, bus_addr_t, bus_addr_t, 115 bus_size_t, bus_size_t, bus_size_t, int, 116 bus_addr_t *, bus_space_handle_t *); 117 void (*bs_free)(void *, bus_space_handle_t, 118 bus_size_t); 119 120 /* get kernel virtual address */ 121 void * (*bs_vaddr)(void *, bus_space_handle_t); 122 123 /* mmap bus space for user */ 124 paddr_t (*bs_mmap)(void *, bus_addr_t, off_t, int, int); 125 126 /* barrier */ 127 void (*bs_barrier)(void *, bus_space_handle_t, 128 bus_size_t, bus_size_t, int); 129 130 /* read (single) */ 131 uint8_t (*bs_r_1)(void *, bus_space_handle_t, 132 bus_size_t); 133 uint16_t (*bs_r_2)(void *, bus_space_handle_t, 134 bus_size_t); 135 uint32_t (*bs_r_4)(void *, bus_space_handle_t, 136 bus_size_t); 137 uint64_t (*bs_r_8)(void *, bus_space_handle_t, 138 bus_size_t); 139 140 /* read multiple */ 141 void (*bs_rm_1)(void *, bus_space_handle_t, 142 bus_size_t, uint8_t *, bus_size_t); 143 void (*bs_rm_2)(void *, bus_space_handle_t, 144 bus_size_t, uint16_t *, bus_size_t); 145 void (*bs_rm_4)(void *, bus_space_handle_t, 146 bus_size_t, uint32_t *, bus_size_t); 147 void (*bs_rm_8)(void *, bus_space_handle_t, 148 bus_size_t, uint64_t *, bus_size_t); 149 150 /* read region */ 151 void (*bs_rr_1)(void *, bus_space_handle_t, 152 bus_size_t, uint8_t *, bus_size_t); 153 void (*bs_rr_2)(void *, bus_space_handle_t, 154 bus_size_t, uint16_t *, bus_size_t); 155 void (*bs_rr_4)(void *, bus_space_handle_t, 156 bus_size_t, uint32_t *, bus_size_t); 157 void (*bs_rr_8)(void *, bus_space_handle_t, 158 bus_size_t, uint64_t *, bus_size_t); 159 160 /* write (single) */ 161 void (*bs_w_1)(void *, bus_space_handle_t, 162 bus_size_t, uint8_t); 163 void (*bs_w_2)(void *, bus_space_handle_t, 164 bus_size_t, uint16_t); 165 void (*bs_w_4)(void *, bus_space_handle_t, 166 bus_size_t, uint32_t); 167 void (*bs_w_8)(void *, bus_space_handle_t, 168 bus_size_t, uint64_t); 169 170 /* write multiple */ 171 void (*bs_wm_1)(void *, bus_space_handle_t, 172 bus_size_t, const uint8_t *, bus_size_t); 173 void (*bs_wm_2)(void *, bus_space_handle_t, 174 bus_size_t, const uint16_t *, bus_size_t); 175 void (*bs_wm_4)(void *, bus_space_handle_t, 176 bus_size_t, const uint32_t *, bus_size_t); 177 void (*bs_wm_8)(void *, bus_space_handle_t, 178 bus_size_t, const uint64_t *, bus_size_t); 179 180 /* write region */ 181 void (*bs_wr_1)(void *, bus_space_handle_t, 182 bus_size_t, const uint8_t *, bus_size_t); 183 void (*bs_wr_2)(void *, bus_space_handle_t, 184 bus_size_t, const uint16_t *, bus_size_t); 185 void (*bs_wr_4)(void *, bus_space_handle_t, 186 bus_size_t, const uint32_t *, bus_size_t); 187 void (*bs_wr_8)(void *, bus_space_handle_t, 188 bus_size_t, const uint64_t *, bus_size_t); 189 190 /* set multiple */ 191 void (*bs_sm_1)(void *, bus_space_handle_t, 192 bus_size_t, uint8_t, bus_size_t); 193 void (*bs_sm_2)(void *, bus_space_handle_t, 194 bus_size_t, uint16_t, bus_size_t); 195 void (*bs_sm_4)(void *, bus_space_handle_t, 196 bus_size_t, uint32_t, bus_size_t); 197 void (*bs_sm_8)(void *, bus_space_handle_t, 198 bus_size_t, uint64_t, bus_size_t); 199 200 /* set region */ 201 void (*bs_sr_1)(void *, bus_space_handle_t, 202 bus_size_t, uint8_t, bus_size_t); 203 void (*bs_sr_2)(void *, bus_space_handle_t, 204 bus_size_t, uint16_t, bus_size_t); 205 void (*bs_sr_4)(void *, bus_space_handle_t, 206 bus_size_t, uint32_t, bus_size_t); 207 void (*bs_sr_8)(void *, bus_space_handle_t, 208 bus_size_t, uint64_t, bus_size_t); 209 210 /* copy */ 211 void (*bs_c_1)(void *, bus_space_handle_t, bus_size_t, 212 bus_space_handle_t, bus_size_t, bus_size_t); 213 void (*bs_c_2)(void *, bus_space_handle_t, bus_size_t, 214 bus_space_handle_t, bus_size_t, bus_size_t); 215 void (*bs_c_4)(void *, bus_space_handle_t, bus_size_t, 216 bus_space_handle_t, bus_size_t, bus_size_t); 217 void (*bs_c_8)(void *, bus_space_handle_t, bus_size_t, 218 bus_space_handle_t, bus_size_t, bus_size_t); 219 220 #ifdef __BUS_SPACE_HAS_STREAM_METHODS 221 /* read stream (single) */ 222 uint8_t (*bs_r_1_s)(void *, bus_space_handle_t, 223 bus_size_t); 224 uint16_t (*bs_r_2_s)(void *, bus_space_handle_t, 225 bus_size_t); 226 uint32_t (*bs_r_4_s)(void *, bus_space_handle_t, 227 bus_size_t); 228 uint64_t (*bs_r_8_s)(void *, bus_space_handle_t, 229 bus_size_t); 230 231 /* read multiple stream */ 232 void (*bs_rm_1_s)(void *, bus_space_handle_t, 233 bus_size_t, uint8_t *, bus_size_t); 234 void (*bs_rm_2_s)(void *, bus_space_handle_t, 235 bus_size_t, uint16_t *, bus_size_t); 236 void (*bs_rm_4_s)(void *, bus_space_handle_t, 237 bus_size_t, uint32_t *, bus_size_t); 238 void (*bs_rm_8_s)(void *, bus_space_handle_t, 239 bus_size_t, uint64_t *, bus_size_t); 240 241 /* read region stream */ 242 void (*bs_rr_1_s)(void *, bus_space_handle_t, 243 bus_size_t, uint8_t *, bus_size_t); 244 void (*bs_rr_2_s)(void *, bus_space_handle_t, 245 bus_size_t, uint16_t *, bus_size_t); 246 void (*bs_rr_4_s)(void *, bus_space_handle_t, 247 bus_size_t, uint32_t *, bus_size_t); 248 void (*bs_rr_8_s)(void *, bus_space_handle_t, 249 bus_size_t, uint64_t *, bus_size_t); 250 251 /* write stream (single) */ 252 void (*bs_w_1_s)(void *, bus_space_handle_t, 253 bus_size_t, uint8_t); 254 void (*bs_w_2_s)(void *, bus_space_handle_t, 255 bus_size_t, uint16_t); 256 void (*bs_w_4_s)(void *, bus_space_handle_t, 257 bus_size_t, uint32_t); 258 void (*bs_w_8_s)(void *, bus_space_handle_t, 259 bus_size_t, uint64_t); 260 261 /* write multiple stream */ 262 void (*bs_wm_1_s)(void *, bus_space_handle_t, 263 bus_size_t, const uint8_t *, bus_size_t); 264 void (*bs_wm_2_s)(void *, bus_space_handle_t, 265 bus_size_t, const uint16_t *, bus_size_t); 266 void (*bs_wm_4_s)(void *, bus_space_handle_t, 267 bus_size_t, const uint32_t *, bus_size_t); 268 void (*bs_wm_8_s)(void *, bus_space_handle_t, 269 bus_size_t, const uint64_t *, bus_size_t); 270 271 /* write region stream */ 272 void (*bs_wr_1_s)(void *, bus_space_handle_t, 273 bus_size_t, const uint8_t *, bus_size_t); 274 void (*bs_wr_2_s)(void *, bus_space_handle_t, 275 bus_size_t, const uint16_t *, bus_size_t); 276 void (*bs_wr_4_s)(void *, bus_space_handle_t, 277 bus_size_t, const uint32_t *, bus_size_t); 278 void (*bs_wr_8_s)(void *, bus_space_handle_t, 279 bus_size_t, const uint64_t *, bus_size_t); 280 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 281 282 #ifdef __BUS_SPACE_HAS_PROBING_METHODS 283 /* peek */ 284 int (*bs_pe_1)(void *, bus_space_handle_t, 285 bus_size_t, uint8_t *); 286 int (*bs_pe_2)(void *, bus_space_handle_t, 287 bus_size_t, uint16_t *); 288 int (*bs_pe_4)(void *, bus_space_handle_t, 289 bus_size_t, uint32_t *); 290 int (*bs_pe_8)(void *, bus_space_handle_t, 291 bus_size_t, uint64_t *); 292 293 /* poke */ 294 int (*bs_po_1)(void *, bus_space_handle_t, 295 bus_size_t, uint8_t); 296 int (*bs_po_2)(void *, bus_space_handle_t, 297 bus_size_t, uint16_t); 298 int (*bs_po_4)(void *, bus_space_handle_t, 299 bus_size_t, uint32_t); 300 int (*bs_po_8)(void *, bus_space_handle_t, 301 bus_size_t, uint64_t); 302 #endif /* __BUS_SPACE_HAS_PROBING_METHODS */ 303 }; 304 305 #define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t) 306 307 /* Bus Space DMA macros */ 308 309 /* 310 * Private flags stored in the DMA map. 311 */ 312 #define _BUS_DMAMAP_COHERENT __BIT(16) /* no cache flush necessary on sync */ 313 #define _BUS_DMAMAP_IS_BOUNCING __BIT(17) /* is bouncing current xfer */ 314 #define _BUS_DMAMAP_NOALLOC __BIT(18) /* don't alloc memory from this range */ 315 316 /* Forwards needed by prototypes below. */ 317 struct mbuf; 318 struct uio; 319 320 typedef struct riscv_bus_dma_tag *bus_dma_tag_t; 321 typedef struct riscv_bus_dmamap *bus_dmamap_t; 322 323 #define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0) 324 325 /* 326 * bus_dma_segment_t 327 * 328 * Describes a single contiguous DMA transaction. Values 329 * are suitable for programming into DMA registers. 330 */ 331 struct riscv_bus_dma_segment { 332 /* 333 * PUBLIC MEMBERS: these are used by machine-independent code. 334 */ 335 bus_addr_t ds_addr; /* DMA address */ 336 bus_size_t ds_len; /* length of transfer */ 337 338 /* 339 * PRIVATE MEMBERS: 340 */ 341 uint32_t _ds_flags; /* _BUS_DMAMAP_COHERENT */ 342 paddr_t _ds_paddr; /* CPU address */ 343 }; 344 typedef struct riscv_bus_dma_segment bus_dma_segment_t; 345 346 /* 347 * riscv_dma_range 348 * 349 * This structure describes a valid DMA range. 350 */ 351 struct riscv_dma_range { 352 paddr_t dr_sysbase; /* system base address */ 353 bus_addr_t dr_busbase; /* appears here on bus */ 354 bus_size_t dr_len; /* length of range */ 355 uint32_t dr_flags; /* flags for range */ 356 }; 357 358 /* 359 * bus_dma_tag_t 360 * 361 * A machine-dependent opaque type describing the implementation of 362 * DMA for a given bus. 363 */ 364 365 struct riscv_bus_dma_tag { 366 /* 367 * DMA range for this tag. If the page doesn't fall within 368 * one of these ranges, an error is returned. The caller 369 * may then decide what to do with the transfer. If the 370 * range pointer is NULL, it is ignored. 371 */ 372 struct riscv_dma_range *_ranges; 373 int _nranges; 374 375 /* 376 * Opaque cookie for use by back-end. 377 */ 378 void *_cookie; 379 380 /* 381 * DMA mapping methods. 382 */ 383 int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int, 384 bus_size_t, bus_size_t, int, bus_dmamap_t *); 385 void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t); 386 int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *, 387 bus_size_t, struct proc *, int); 388 int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t, 389 struct mbuf *, int); 390 int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t, 391 struct uio *, int); 392 int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t, 393 bus_dma_segment_t *, int, bus_size_t, int); 394 void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t); 395 void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t, 396 bus_addr_t, bus_size_t, int); 397 398 /* 399 * DMA memory utility functions. 400 */ 401 int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t, 402 bus_size_t, bus_dma_segment_t *, int, int *, int); 403 void (*_dmamem_free)(bus_dma_tag_t, 404 bus_dma_segment_t *, int); 405 int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *, 406 int, size_t, void **, int); 407 void (*_dmamem_unmap)(bus_dma_tag_t, void *, size_t); 408 paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *, 409 int, off_t, int, int); 410 411 /* 412 * DMA tag utility functions 413 */ 414 int (*_dmatag_subregion)(bus_dma_tag_t, bus_addr_t, bus_addr_t, 415 bus_dma_tag_t *, int); 416 void (*_dmatag_destroy)(bus_dma_tag_t); 417 418 /* 419 * State for bounce buffers 420 */ 421 int _tag_needs_free; 422 int (*_may_bounce)(bus_dma_tag_t, bus_dmamap_t, int, int *); 423 }; 424 425 /* 426 * bus_dmamap_t 427 * 428 * Describes a DMA mapping. 429 */ 430 struct riscv_bus_dmamap { 431 /* 432 * PRIVATE MEMBERS: not for use by machine-independent code. 433 */ 434 bus_size_t _dm_size; /* largest DMA transfer mappable */ 435 int _dm_segcnt; /* number of segs this map can map */ 436 bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */ 437 bus_size_t _dm_boundary; /* don't cross this */ 438 int _dm_flags; /* misc. flags */ 439 440 void *_dm_origbuf; /* pointer to original buffer */ 441 int _dm_buftype; /* type of buffer */ 442 struct vmspace *_dm_vmspace; /* vmspace that owns the mapping */ 443 444 void *_dm_cookie; /* cookie for bus-specific functions */ 445 446 /* 447 * PUBLIC MEMBERS: these are used by machine-independent code. 448 */ 449 450 #if defined(KASAN) 451 void *dm_buf; 452 bus_size_t dm_buflen; 453 int dm_buftype; 454 #endif 455 456 bus_size_t dm_maxsegsz; /* largest possible segment */ 457 bus_size_t dm_mapsize; /* size of the mapping */ 458 int dm_nsegs; /* # valid segments in mapping */ 459 bus_dma_segment_t dm_segs[1]; /* segments; variable length */ 460 }; 461 462 /* _dm_buftype */ 463 #define _BUS_DMA_BUFTYPE_INVALID 0 464 #define _BUS_DMA_BUFTYPE_LINEAR 1 465 #define _BUS_DMA_BUFTYPE_MBUF 2 466 #define _BUS_DMA_BUFTYPE_UIO 3 467 #define _BUS_DMA_BUFTYPE_RAW 4 468 469 #ifdef _RISCV_BUS_DMA_PRIVATE 470 #define _BUS_AVAIL_END physical_end 471 /* 472 * Cookie used for bounce buffers. A pointer to one of these it stashed in 473 * the DMA map. 474 */ 475 struct riscv_bus_dma_cookie { 476 int id_flags; /* flags; see below */ 477 478 /* 479 * Information about the original buffer used during 480 * DMA map syncs. Note that origibuflen is only used 481 * for ID_BUFTYPE_LINEAR. 482 */ 483 union { 484 void *un_origbuf; /* pointer to orig buffer if 485 bouncing */ 486 char *un_linearbuf; 487 struct mbuf *un_mbuf; 488 struct uio *un_uio; 489 } id_origbuf_un; 490 #define id_origbuf id_origbuf_un.un_origbuf 491 #define id_origlinearbuf id_origbuf_un.un_linearbuf 492 #define id_origmbuf id_origbuf_un.un_mbuf 493 #define id_origuio id_origbuf_un.un_uio 494 bus_size_t id_origbuflen; /* ...and size */ 495 496 void *id_bouncebuf; /* pointer to the bounce buffer */ 497 bus_size_t id_bouncebuflen; /* ...and size */ 498 int id_nbouncesegs; /* number of valid bounce segs */ 499 bus_dma_segment_t 500 id_bouncesegs[0];/* array of bounce buffer */ 501 /* ... physical memory segments */ 502 }; 503 504 /* id_flags */ 505 #define _BUS_DMA_IS_BOUNCING __BIT(2) /* is bouncing current xfer */ 506 #define _BUS_DMA_HAS_BOUNCE __BIT(1) /* has bounce buffers */ 507 #endif /* _RISCV_BUS_DMA_PRIVATE */ 508 #define _BUS_DMA_MIGHT_NEED_BOUNCE __BIT(0) /* may need bounce buffers */ 509 510 #endif /* _RISCV_BUS_DEFS_H_ */ 511
Indexes created Sat Sep 20 22:09:52 GMT 2025