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pte.h revision 1.4 
      1 /* $NetBSD: pte.h,v 1.4 2020/03/14 16:12:16 skrll Exp $ */
      2 
      3 /*
      4  * Copyright (c) 2014, 2019 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Matt Thomas (of 3am Software Foundry) and Maxime Villard.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _RISCV_PTE_H_
     33 #define _RISCV_PTE_H_
     34 
     35 #ifdef _LP64	/* Sv39 */
     36 #define PTE_PPN		__BITS(53, 10)
     37 #define	PTE_PPN0	__BITS(18, 10)
     38 #define	PTE_PPN1	__BITS(27, 19)
     39 #define	PTE_PPN2	__BITS(53, 28)
     40 typedef __uint64_t pt_entry_t;
     41 typedef __uint64_t pd_entry_t;
     42 #define atomic_cas_pte	atomic_cas_64
     43 #else		/* Sv32 */
     44 #define PTE_PPN		__BITS(31, 10)
     45 #define	PTE_PPN0	__BITS(19, 10)
     46 #define	PTE_PPN1	__BITS(31, 20)
     47 typedef __uint32_t pt_entry_t;
     48 typedef __uint32_t pd_entry_t;
     49 #define atomic_cas_pte	atomic_cas_32
     50 #endif
     51 
     52 #define PTE_PPN_SHIFT	10
     53 
     54 #define NPTEPG		(PAGE_SIZE / sizeof(pt_entry_t))
     55 #define NSEGPG		NPTEPG
     56 #define NPDEPG		NPTEPG
     57 
     58 /* Software PTE bits. */
     59 #define	PTE_WIRED	__BIT(8)
     60 
     61 /* Hardware PTE bits. */
     62 #define	PTE_D		__BIT(7)
     63 #define	PTE_A		__BIT(6)
     64 #define	PTE_G		__BIT(5)
     65 #define	PTE_U		__BIT(4)
     66 #define	PTE_X		__BIT(3)
     67 #define	PTE_W		__BIT(2)
     68 #define	PTE_R		__BIT(1)
     69 #define	PTE_V		__BIT(0)
     70 
     71 #define PA_TO_PTE(pa)	(((pa) >> PAGE_SHIFT) << PTE_PPN_SHIFT)
     72 #define PTE_TO_PA(pte)	(((pte) >> PTE_PPN_SHIFT) << PAGE_SHIFT)
     73 
     74 #define	L2_SHIFT	30
     75 #define	L1_SHIFT	21
     76 #define	L0_SHIFT	12
     77 
     78 #define	L2_SIZE 	(1 << L2_SHIFT)
     79 #define	L1_SIZE 	(1 << L1_SHIFT)
     80 #define	L0_SIZE 	(1 << L0_SHIFT)
     81 
     82 #define	L2_OFFSET 	(L2_SIZE - 1)
     83 #define	L1_OFFSET 	(L1_SIZE - 1)
     84 #define	L0_OFFSET 	(L0_SIZE - 1)
     85 
     86 #define	Ln_ENTRIES	(1 << 9)
     87 #define	Ln_ADDR_MASK	(Ln_ENTRIES - 1)
     88 
     89 #define pl2_i(va)	(((va) >> L2_SHIFT) & Ln_ADDR_MASK)
     90 #define pl1_i(va)	(((va) >> L1_SHIFT) & Ln_ADDR_MASK)
     91 #define pl0_i(va)	(((va) >> L0_SHIFT) & Ln_ADDR_MASK)
     92 
     93 static inline bool
     94 pte_valid_p(pt_entry_t pte)
     95 {
     96 	return (pte & PTE_V) != 0;
     97 }
     98 
     99 static inline bool
    100 pte_wired_p(pt_entry_t pte)
    101 {
    102 	return (pte & PTE_WIRED) != 0;
    103 }
    104 
    105 static inline bool
    106 pte_modified_p(pt_entry_t pte)
    107 {
    108 	return (pte & PTE_D) != 0;
    109 }
    110 
    111 static inline bool
    112 pte_cached_p(pt_entry_t pte)
    113 {
    114 	return true;
    115 }
    116 
    117 static inline bool
    118 pte_deferred_exec_p(pt_entry_t pte)
    119 {
    120 	return false;
    121 }
    122 
    123 static inline pt_entry_t
    124 pte_wire_entry(pt_entry_t pte)
    125 {
    126 	return pte | PTE_WIRED;
    127 }
    128 
    129 static inline pt_entry_t
    130 pte_unwire_entry(pt_entry_t pte)
    131 {
    132 	return pte & ~PTE_WIRED;
    133 }
    134 
    135 static inline paddr_t
    136 pte_to_paddr(pt_entry_t pte)
    137 {
    138 	return pte & ~PAGE_MASK;
    139 }
    140 
    141 static inline pt_entry_t
    142 pte_nv_entry(bool kernel_p)
    143 {
    144 	return kernel_p ? PTE_G : 0;
    145 }
    146 
    147 static inline pt_entry_t
    148 pte_prot_nowrite(pt_entry_t pte)
    149 {
    150 	return pte & ~PTE_W;
    151 }
    152 
    153 static inline pt_entry_t
    154 pte_prot_downgrade(pt_entry_t pte, vm_prot_t newprot)
    155 {
    156 	if ((newprot & VM_PROT_READ) == 0)
    157 		pte &= ~PTE_R;
    158 	if ((newprot & VM_PROT_WRITE) == 0)
    159 		pte &= ~PTE_W;
    160 	if ((newprot & VM_PROT_EXECUTE) == 0)
    161 		pte &= ~PTE_X;
    162 	return pte;
    163 }
    164 
    165 static inline pt_entry_t
    166 pte_prot_bits(struct vm_page_md *mdpg, vm_prot_t prot, bool kernel_p)
    167 {
    168 	pt_entry_t pte;
    169 
    170 	KASSERT(prot & VM_PROT_READ);
    171 
    172 	pte = PTE_R;
    173 	if (prot & VM_PROT_EXECUTE) {
    174 		pte |= PTE_X;
    175 	}
    176 	if (prot & VM_PROT_WRITE) {
    177 		pte |= PTE_W;
    178 	}
    179 
    180 	return pte;
    181 }
    182 
    183 static inline pt_entry_t
    184 pte_flag_bits(struct vm_page_md *mdpg, int flags, bool kernel_p)
    185 {
    186 #if 0
    187 	if (__predict_false(flags & PMAP_NOCACHE)) {
    188 		if (__predict_true(mdpg != NULL)) {
    189 			return pte_nocached_bits();
    190 		} else {
    191 			return pte_ionocached_bits();
    192 		}
    193 	} else {
    194 		if (__predict_false(mdpg != NULL)) {
    195 			return pte_cached_bits();
    196 		} else {
    197 			return pte_iocached_bits();
    198 		}
    199 	}
    200 #else
    201 	return 0;
    202 #endif
    203 }
    204 
    205 static inline pt_entry_t
    206 pte_make_enter(paddr_t pa, struct vm_page_md *mdpg, vm_prot_t prot,
    207     int flags, bool kernel_p)
    208 {
    209 	pt_entry_t pte = (pt_entry_t)PA_TO_PTE(pa);
    210 
    211 	pte |= pte_flag_bits(mdpg, flags, kernel_p);
    212 	pte |= pte_prot_bits(mdpg, prot, kernel_p);
    213 
    214 	if (mdpg == NULL && VM_PAGEMD_REFERENCED_P(mdpg))
    215 		pte |= PTE_V;
    216 
    217 	return pte;
    218 }
    219 
    220 static inline pt_entry_t
    221 pte_make_kenter_pa(paddr_t pa, struct vm_page_md *mdpg, vm_prot_t prot,
    222     int flags)
    223 {
    224 	pt_entry_t pte = (pt_entry_t)PA_TO_PTE(pa);
    225 
    226 	pte |= PTE_WIRED | PTE_V;
    227 	pte |= pte_flag_bits(NULL, flags, true);
    228 	pte |= pte_prot_bits(NULL, prot, true); /* pretend unmanaged */
    229 
    230 	return pte;
    231 }
    232 
    233 static inline void
    234 pte_set(pt_entry_t *ptep, pt_entry_t pte)
    235 {
    236 	*ptep = pte;
    237 }
    238 
    239 static inline pt_entry_t
    240 pte_value(pt_entry_t pte)
    241 {
    242 	return pte;
    243 }
    244 
    245 #endif /* _RISCV_PTE_H_ */
    246