| History log of /src/sys/arch/riscv/include/pte.h |
| Revision | | Date | Author | Comments |
| 1.17 |
| 13-Oct-2025 |
skrll | risc-v: pte_make_enter set PTE_D when page is known to be modified.
PR/59696: pte_make_enter() appears to have bug vis a vis already-modified managed pages
|
| 1.16 |
| 12-Oct-2025 |
skrll | Fix RV32 build. Svpbmt and Memory Attribute Extension (XTheadMae) are
SV39 and above only.
|
| 1.15 |
| 12-Oct-2025 |
thorpej | Deal with the non-standard XTheadMae (Memory Attribute Extensions)
present on some T-Head CPU cores, notably the one found in the
Allwinner D1 SoC.
This extension allows memory attributes (cacheable, bufferable,
strongly-ordered, etc.) to be specified on a per-mapping basis.
Alas, it has two unfortunate properties:
- It uses the same bits as the standard Svpbmt (Page Based Memory Types)
extension, and the bits are completely incompatible.
- Unlike Svpbmt, which if none of its extension bits are set in the
PTE, results in rational behavior, if you don't set the XTheadMae
attibutes in the PTE correctly, the system will blow up in your face
in interesting and unpredictable ways.
So, we have to probe for XTheadMae early, when we're setting up the
initial MMU tables so that the kernel is mapped correctly when the
MMU is enabled, and then we probe for it again to set some globals
that are used when creating PTEs for new kernel and user mappings
going forward. Luckily, there are combinations of XTheadMae attributes
that map reasonably well to the Svpbmt types, so Svpbmt is used as
the abstraction.
With this, my D1 Nezha board boots to the root device prompt. \o/
|
| 1.14 |
| 12-Oct-2024 |
skrll | Install pte.h for libkvm
|
| 1.13 |
| 07-May-2023 |
skrll | branches: 1.13.6;
RISC-V support that works on QEMU with a single hart.
Thanks for Simon Burge for plic(4).
|
| 1.12 |
| 22-Apr-2023 |
skrll | G/C pte_index
|
| 1.11 |
| 12-Nov-2022 |
skrll | Note some SV39 PTE bits defined in extensions.
Fix pte_nv_entry for the kernel.
Fix pte_pde_ptpage. PTE.{X,W,R} must be zero for pointer to next level.
|
| 1.10 |
| 18-Oct-2022 |
skrll | Some fixes from Simon.
|
| 1.9 |
| 15-Oct-2022 |
simonb | #define<tab>
|
| 1.8 |
| 30-Sep-2022 |
skrll | Don't set A, D in page table pointers, but do set them in leaf entries.
Beagle-v now boots to the msgbufaddr panic same as qemu
|
| 1.7 |
| 21-Sep-2022 |
skrll | Use c99 types. NFC.
|
| 1.6 |
| 01-May-2021 |
skrll | Fixup some pmap / VM related #defines and code
|
| 1.5 |
| 01-Nov-2020 |
skrll | branches: 1.5.4;
Comments from zmcgrew@
|
| 1.4 |
| 14-Mar-2020 |
skrll | branches: 1.4.4;
Trailing whitespace
|
| 1.3 |
| 16-Jun-2019 |
maxv | Misc changes in RISC-V.
|
| 1.2 |
| 01-Jun-2019 |
maxv | Misc changes in RISC-V. Start changing the memory layout, too.
|
| 1.1 |
| 19-Sep-2014 |
matt | branches: 1.1.18; 1.1.22;
New files for Userland support of UCB RISC-V (both 32-bit and 64-bit)
|
| 1.1.22.3 |
| 13-Apr-2020 |
martin | Mostly merge changes from HEAD upto 20200411
|
| 1.1.22.2 |
| 08-Apr-2020 |
martin | Merge changes from current as of 20200406
|
| 1.1.22.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.1.18.2 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.1.18.1 |
| 19-Sep-2014 |
jdolecek | file pte.h was added on branch tls-maxphys on 2017-12-03 11:36:39 +0000
|
| 1.4.4.1 |
| 14-Dec-2020 |
thorpej | Sync w/ HEAD.
|
| 1.5.4.1 |
| 13-May-2021 |
thorpej | Sync with HEAD.
|
| 1.13.6.1 |
| 02-Aug-2025 |
perseant | Sync with HEAD
|
