jh7110_clkc.c revision 1.1
1 /* $NetBSD: jh7110_clkc.c,v 1.1 2024/08/19 07:33:55 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2023 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: jh7110_clkc.c,v 1.1 2024/08/19 07:33:55 skrll Exp $"); 34 35 #include <sys/param.h> 36 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 40 #include <dev/clk/clk_backend.h> 41 42 #include <dev/fdt/fdtvar.h> 43 44 #include <riscv/starfive/jh71x0_clkc.h> 45 46 /* SYSCRG clocks */ 47 #define JH7110_SYSCLK_CPU_ROOT 0 48 #define JH7110_SYSCLK_CPU_CORE 1 49 #define JH7110_SYSCLK_CPU_BUS 2 50 #define JH7110_SYSCLK_GPU_ROOT 3 51 #define JH7110_SYSCLK_PERH_ROOT 4 52 #define JH7110_SYSCLK_BUS_ROOT 5 53 #define JH7110_SYSCLK_NOCSTG_BUS 6 54 #define JH7110_SYSCLK_AXI_CFG0 7 55 #define JH7110_SYSCLK_STG_AXIAHB 8 56 #define JH7110_SYSCLK_AHB0 9 57 #define JH7110_SYSCLK_AHB1 10 58 #define JH7110_SYSCLK_APB_BUS 11 59 #define JH7110_SYSCLK_APB0 12 60 #define JH7110_SYSCLK_PLL0_DIV2 13 61 #define JH7110_SYSCLK_PLL1_DIV2 14 62 #define JH7110_SYSCLK_PLL2_DIV2 15 63 #define JH7110_SYSCLK_AUDIO_ROOT 16 64 #define JH7110_SYSCLK_MCLK_INNER 17 65 #define JH7110_SYSCLK_MCLK 18 66 #define JH7110_SYSCLK_MCLK_OUT 19 67 #define JH7110_SYSCLK_ISP_2X 20 68 #define JH7110_SYSCLK_ISP_AXI 21 69 #define JH7110_SYSCLK_GCLK0 22 70 #define JH7110_SYSCLK_GCLK1 23 71 #define JH7110_SYSCLK_GCLK2 24 72 #define JH7110_SYSCLK_CORE 25 73 #define JH7110_SYSCLK_CORE1 26 74 #define JH7110_SYSCLK_CORE2 27 75 #define JH7110_SYSCLK_CORE3 28 76 #define JH7110_SYSCLK_CORE4 29 77 #define JH7110_SYSCLK_DEBUG 30 78 #define JH7110_SYSCLK_RTC_TOGGLE 31 79 #define JH7110_SYSCLK_TRACE0 32 80 #define JH7110_SYSCLK_TRACE1 33 81 #define JH7110_SYSCLK_TRACE2 34 82 #define JH7110_SYSCLK_TRACE3 35 83 #define JH7110_SYSCLK_TRACE4 36 84 #define JH7110_SYSCLK_TRACE_COM 37 85 #define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 86 #define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 87 #define JH7110_SYSCLK_OSC_DIV2 40 88 #define JH7110_SYSCLK_PLL1_DIV4 41 89 #define JH7110_SYSCLK_PLL1_DIV8 42 90 #define JH7110_SYSCLK_DDR_BUS 43 91 #define JH7110_SYSCLK_DDR_AXI 44 92 #define JH7110_SYSCLK_GPU_CORE 45 93 #define JH7110_SYSCLK_GPU_CORE_CLK 46 94 #define JH7110_SYSCLK_GPU_SYS_CLK 47 95 #define JH7110_SYSCLK_GPU_APB 48 96 #define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 97 #define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 98 #define JH7110_SYSCLK_ISP_TOP_CORE 51 99 #define JH7110_SYSCLK_ISP_TOP_AXI 52 100 #define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 101 #define JH7110_SYSCLK_HIFI4_CORE 54 102 #define JH7110_SYSCLK_HIFI4_AXI 55 103 #define JH7110_SYSCLK_AXI_CFG1_MAIN 56 104 #define JH7110_SYSCLK_AXI_CFG1_AHB 57 105 #define JH7110_SYSCLK_VOUT_SRC 58 106 #define JH7110_SYSCLK_VOUT_AXI 59 107 #define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 108 #define JH7110_SYSCLK_VOUT_TOP_AHB 61 109 #define JH7110_SYSCLK_VOUT_TOP_AXI 62 110 #define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 63 111 #define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 64 112 #define JH7110_SYSCLK_JPEGC_AXI 65 113 #define JH7110_SYSCLK_CODAJ12_AXI 66 114 #define JH7110_SYSCLK_CODAJ12_CORE 67 115 #define JH7110_SYSCLK_CODAJ12_APB 68 116 #define JH7110_SYSCLK_VDEC_AXI 69 117 #define JH7110_SYSCLK_WAVE511_AXI 70 118 #define JH7110_SYSCLK_WAVE511_BPU 71 119 #define JH7110_SYSCLK_WAVE511_VCE 72 120 #define JH7110_SYSCLK_WAVE511_APB 73 121 #define JH7110_SYSCLK_VDEC_JPG 74 122 #define JH7110_SYSCLK_VDEC_MAIN 75 123 #define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 124 #define JH7110_SYSCLK_VENC_AXI 77 125 #define JH7110_SYSCLK_WAVE420L_AXI 78 126 #define JH7110_SYSCLK_WAVE420L_BPU 79 127 #define JH7110_SYSCLK_WAVE420L_VCE 80 128 #define JH7110_SYSCLK_WAVE420L_APB 81 129 #define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 130 #define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83 131 #define JH7110_SYSCLK_AXI_CFG0_MAIN 84 132 #define JH7110_SYSCLK_AXI_CFG0_HIFI4 85 133 #define JH7110_SYSCLK_AXIMEM2_AXI 86 134 #define JH7110_SYSCLK_QSPI_AHB 87 135 #define JH7110_SYSCLK_QSPI_APB 88 136 #define JH7110_SYSCLK_QSPI_REF_SRC 89 137 #define JH7110_SYSCLK_QSPI_REF 90 138 #define JH7110_SYSCLK_SDIO0_AHB 91 139 #define JH7110_SYSCLK_SDIO1_AHB 92 140 #define JH7110_SYSCLK_SDIO0_SDCARD 93 141 #define JH7110_SYSCLK_SDIO1_SDCARD 94 142 #define JH7110_SYSCLK_USB_125M 95 143 #define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 144 #define JH7110_SYSCLK_GMAC1_AHB 97 145 #define JH7110_SYSCLK_GMAC1_AXI 98 146 #define JH7110_SYSCLK_GMAC_SRC 99 147 #define JH7110_SYSCLK_GMAC1_GTXCLK 100 148 #define JH7110_SYSCLK_GMAC1_RMII_RTX 101 149 #define JH7110_SYSCLK_GMAC1_PTP 102 150 #define JH7110_SYSCLK_GMAC1_RX 103 151 #define JH7110_SYSCLK_GMAC1_RX_INV 104 152 #define JH7110_SYSCLK_GMAC1_TX 105 153 #define JH7110_SYSCLK_GMAC1_TX_INV 106 154 #define JH7110_SYSCLK_GMAC1_GTXC 107 155 #define JH7110_SYSCLK_GMAC0_GTXCLK 108 156 #define JH7110_SYSCLK_GMAC0_PTP 109 157 #define JH7110_SYSCLK_GMAC_PHY 110 158 #define JH7110_SYSCLK_GMAC0_GTXC 111 159 #define JH7110_SYSCLK_IOMUX_APB 112 160 #define JH7110_SYSCLK_MAILBOX_APB 113 161 #define JH7110_SYSCLK_INT_CTRL_APB 114 162 #define JH7110_SYSCLK_CAN0_APB 115 163 #define JH7110_SYSCLK_CAN0_TIMER 116 164 #define JH7110_SYSCLK_CAN0_CAN 117 165 #define JH7110_SYSCLK_CAN1_APB 118 166 #define JH7110_SYSCLK_CAN1_TIMER 119 167 #define JH7110_SYSCLK_CAN1_CAN 120 168 #define JH7110_SYSCLK_PWM_APB 121 169 #define JH7110_SYSCLK_WDT_APB 122 170 #define JH7110_SYSCLK_WDT_CORE 123 171 #define JH7110_SYSCLK_TIMER_APB 124 172 #define JH7110_SYSCLK_TIMER0 125 173 #define JH7110_SYSCLK_TIMER1 126 174 #define JH7110_SYSCLK_TIMER2 127 175 #define JH7110_SYSCLK_TIMER3 128 176 #define JH7110_SYSCLK_TEMP_APB 129 177 #define JH7110_SYSCLK_TEMP_CORE 130 178 #define JH7110_SYSCLK_SPI0_APB 131 179 #define JH7110_SYSCLK_SPI1_APB 132 180 #define JH7110_SYSCLK_SPI2_APB 133 181 #define JH7110_SYSCLK_SPI3_APB 134 182 #define JH7110_SYSCLK_SPI4_APB 135 183 #define JH7110_SYSCLK_SPI5_APB 136 184 #define JH7110_SYSCLK_SPI6_APB 137 185 #define JH7110_SYSCLK_I2C0_APB 138 186 #define JH7110_SYSCLK_I2C1_APB 139 187 #define JH7110_SYSCLK_I2C2_APB 140 188 #define JH7110_SYSCLK_I2C3_APB 141 189 #define JH7110_SYSCLK_I2C4_APB 142 190 #define JH7110_SYSCLK_I2C5_APB 143 191 #define JH7110_SYSCLK_I2C6_APB 144 192 #define JH7110_SYSCLK_UART0_APB 145 193 #define JH7110_SYSCLK_UART0_CORE 146 194 #define JH7110_SYSCLK_UART1_APB 147 195 #define JH7110_SYSCLK_UART1_CORE 148 196 #define JH7110_SYSCLK_UART2_APB 149 197 #define JH7110_SYSCLK_UART2_CORE 150 198 #define JH7110_SYSCLK_UART3_APB 151 199 #define JH7110_SYSCLK_UART3_CORE 152 200 #define JH7110_SYSCLK_UART4_APB 153 201 #define JH7110_SYSCLK_UART4_CORE 154 202 #define JH7110_SYSCLK_UART5_APB 155 203 #define JH7110_SYSCLK_UART5_CORE 156 204 #define JH7110_SYSCLK_PWMDAC_APB 157 205 #define JH7110_SYSCLK_PWMDAC_CORE 158 206 #define JH7110_SYSCLK_SPDIF_APB 159 207 #define JH7110_SYSCLK_SPDIF_CORE 160 208 #define JH7110_SYSCLK_I2STX0_APB 161 209 #define JH7110_SYSCLK_I2STX0_BCLK_MST 162 210 #define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 211 #define JH7110_SYSCLK_I2STX0_LRCK_MST 164 212 #define JH7110_SYSCLK_I2STX0_BCLK 165 213 #define JH7110_SYSCLK_I2STX0_BCLK_INV 166 214 #define JH7110_SYSCLK_I2STX0_LRCK 167 215 #define JH7110_SYSCLK_I2STX1_APB 168 216 #define JH7110_SYSCLK_I2STX1_BCLK_MST 169 217 #define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 218 #define JH7110_SYSCLK_I2STX1_LRCK_MST 171 219 #define JH7110_SYSCLK_I2STX1_BCLK 172 220 #define JH7110_SYSCLK_I2STX1_BCLK_INV 173 221 #define JH7110_SYSCLK_I2STX1_LRCK 174 222 #define JH7110_SYSCLK_I2SRX_APB 175 223 #define JH7110_SYSCLK_I2SRX_BCLK_MST 176 224 #define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 225 #define JH7110_SYSCLK_I2SRX_LRCK_MST 178 226 #define JH7110_SYSCLK_I2SRX_BCLK 179 227 #define JH7110_SYSCLK_I2SRX_BCLK_INV 180 228 #define JH7110_SYSCLK_I2SRX_LRCK 181 229 #define JH7110_SYSCLK_PDM_DMIC 182 230 #define JH7110_SYSCLK_PDM_APB 183 231 #define JH7110_SYSCLK_TDM_AHB 184 232 #define JH7110_SYSCLK_TDM_APB 185 233 #define JH7110_SYSCLK_TDM_INTERNAL 186 234 #define JH7110_SYSCLK_TDM_TDM 187 235 #define JH7110_SYSCLK_TDM_TDM_INV 188 236 #define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 237 238 #define JH7110_SYSCLK_NCLKS 190 239 240 /* external clocks */ 241 #define JH7110_SYSCLK_PLL0_OUT (JH7110_SYSCLK_NCLKS + 0) 242 #define JH7110_SYSCLK_PLL1_OUT (JH7110_SYSCLK_NCLKS + 1) 243 #define JH7110_SYSCLK_PLL2_OUT (JH7110_SYSCLK_NCLKS + 2) 244 245 /* AONCRG clocks */ 246 #define JH7110_AONCLK_OSC_DIV4 0 247 #define JH7110_AONCLK_APB_FUNC 1 248 #define JH7110_AONCLK_GMAC0_AHB 2 249 #define JH7110_AONCLK_GMAC0_AXI 3 250 #define JH7110_AONCLK_GMAC0_RMII_RTX 4 251 #define JH7110_AONCLK_GMAC0_TX 5 252 #define JH7110_AONCLK_GMAC0_TX_INV 6 253 #define JH7110_AONCLK_GMAC0_RX 7 254 #define JH7110_AONCLK_GMAC0_RX_INV 8 255 #define JH7110_AONCLK_OTPC_APB 9 256 #define JH7110_AONCLK_RTC_APB 10 257 #define JH7110_AONCLK_RTC_INTERNAL 11 258 #define JH7110_AONCLK_RTC_32K 12 259 #define JH7110_AONCLK_RTC_CAL 13 260 261 #define JH7110_AONCLK_NCLKS 14 262 263 /* STGCRG clocks */ 264 #define JH7110_STGCLK_HIFI4_CLK_CORE 0 265 #define JH7110_STGCLK_USB0_APB 1 266 #define JH7110_STGCLK_USB0_UTMI_APB 2 267 #define JH7110_STGCLK_USB0_AXI 3 268 #define JH7110_STGCLK_USB0_LPM 4 269 #define JH7110_STGCLK_USB0_STB 5 270 #define JH7110_STGCLK_USB0_APP_125 6 271 #define JH7110_STGCLK_USB0_REFCLK 7 272 #define JH7110_STGCLK_PCIE0_AXI_MST0 8 273 #define JH7110_STGCLK_PCIE0_APB 9 274 #define JH7110_STGCLK_PCIE0_TL 10 275 #define JH7110_STGCLK_PCIE1_AXI_MST0 11 276 #define JH7110_STGCLK_PCIE1_APB 12 277 #define JH7110_STGCLK_PCIE1_TL 13 278 #define JH7110_STGCLK_PCIE_SLV_MAIN 14 279 #define JH7110_STGCLK_SEC_AHB 15 280 #define JH7110_STGCLK_SEC_MISC_AHB 16 281 #define JH7110_STGCLK_GRP0_MAIN 17 282 #define JH7110_STGCLK_GRP0_BUS 18 283 #define JH7110_STGCLK_GRP0_STG 19 284 #define JH7110_STGCLK_GRP1_MAIN 20 285 #define JH7110_STGCLK_GRP1_BUS 21 286 #define JH7110_STGCLK_GRP1_STG 22 287 #define JH7110_STGCLK_GRP1_HIFI 23 288 #define JH7110_STGCLK_E2_RTC 24 289 #define JH7110_STGCLK_E2_CORE 25 290 #define JH7110_STGCLK_E2_DBG 26 291 #define JH7110_STGCLK_DMA1P_AXI 27 292 #define JH7110_STGCLK_DMA1P_AHB 28 293 294 #define JH7110_STGCLK_NCLKS 29 295 296 /* ISPCRG clocks */ 297 #define JH7110_ISPCLK_DOM4_APB_FUNC 0 298 #define JH7110_ISPCLK_MIPI_RX0_PXL 1 299 #define JH7110_ISPCLK_DVP_INV 2 300 #define JH7110_ISPCLK_M31DPHY_CFG_IN 3 301 #define JH7110_ISPCLK_M31DPHY_REF_IN 4 302 #define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5 303 #define JH7110_ISPCLK_VIN_APB 6 304 #define JH7110_ISPCLK_VIN_SYS 7 305 #define JH7110_ISPCLK_VIN_PIXEL_IF0 8 306 #define JH7110_ISPCLK_VIN_PIXEL_IF1 9 307 #define JH7110_ISPCLK_VIN_PIXEL_IF2 10 308 #define JH7110_ISPCLK_VIN_PIXEL_IF3 11 309 #define JH7110_ISPCLK_VIN_P_AXI_WR 12 310 #define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13 311 312 #define JH7110_ISPCLK_NCLKS 14 313 314 /* VOUTCRG clocks */ 315 #define JH7110_VOUTCLK_APB 0 316 #define JH7110_VOUTCLK_DC8200_PIX 1 317 #define JH7110_VOUTCLK_DSI_SYS 2 318 #define JH7110_VOUTCLK_TX_ESC 3 319 #define JH7110_VOUTCLK_DC8200_AXI 4 320 #define JH7110_VOUTCLK_DC8200_CORE 5 321 #define JH7110_VOUTCLK_DC8200_AHB 6 322 #define JH7110_VOUTCLK_DC8200_PIX0 7 323 #define JH7110_VOUTCLK_DC8200_PIX1 8 324 #define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9 325 #define JH7110_VOUTCLK_DSITX_APB 10 326 #define JH7110_VOUTCLK_DSITX_SYS 11 327 #define JH7110_VOUTCLK_DSITX_DPI 12 328 #define JH7110_VOUTCLK_DSITX_TXESC 13 329 #define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14 330 #define JH7110_VOUTCLK_HDMI_TX_MCLK 15 331 #define JH7110_VOUTCLK_HDMI_TX_BCLK 16 332 #define JH7110_VOUTCLK_HDMI_TX_SYS 17 333 334 #define JH7110_VOUTCLK_NCLKS 18 335 336 static const char *cpu_root_parents[] = { 337 "osc", "pll0_out" 338 }; 339 340 static const char *gpu_root_parents[] = { 341 "pll2_out", "pll1_out", 342 }; 343 344 static const char *bus_root_parents[] = { 345 "osc", "pll2_out", 346 }; 347 348 static const char *mclk_parents[] = { 349 "mclk_inner", "mclk_ext" 350 }; 351 352 static const char *ddr_bus_parents[] = { 353 "osc_div2", "pll1_div2", "pll1_div4", "pll1_div8" 354 }; 355 356 static const char *qspi_ref_parents[] = { 357 "osc", "qspi_ref_src", 358 }; 359 360 static const char *isp_2x_parents[] = { 361 "pll2_out", "pll1_out" 362 }; 363 364 static const char *i2stx0_lrck_parents[] = { 365 "i2stx0_lrck_mst", "i2stx_lrck_ext", 366 }; 367 368 static const char *i2stx0_bclk_parents[] = { 369 "i2stx0_bclk_mst", "i2stx_bclk_ext", 370 }; 371 372 static const char *i2stx1_bclk_parents[] = { 373 "i2stx1_bclk_mst", "i2stx_bclk_ext", 374 }; 375 376 static const char *gmac1_rx_parents[] = { 377 "gmac1_rgmii_rxin", "gmac1_rmii_rtx", 378 }; 379 380 static const char *i2srx_bclk_root_parents[] = { 381 "i2srx_bclk_mst", "i2srx_bclk_ext", 382 }; 383 384 static const char *i2srx_lrck_parents[] = { 385 "i2srx_lrck_mst", "i2srx_lrck_ext", 386 }; 387 388 static const char *tdm_tdm_parents[] = { 389 "tdm_internal", "tdm_ext", 390 }; 391 392 static const char *i2stx1_lrck_parents[] = { 393 "i2stx1_lrck_mst", "i2stx_lrck_ext", 394 }; 395 396 static const char *i2stx1_lrck_mst_parents[] = { 397 "i2stx1_bclk_mst_inv", "i2stx1_bclk_mst", 398 }; 399 400 static const char *gmac1_tx_parents[] = { 401 "gmac1_gtxclk", "gmac1_rmii_rtx", 402 }; 403 404 static const char *perh_root_parents[] = { 405 "pll0_out", "pll2_out", 406 }; 407 408 static const char *i2stx0_lrck_mst_parents[] = { 409 "i2stx0_bclk_mst_inv", "i2stx0_bclk_mst" 410 }; 411 412 static const char *i2srx_lrck_mst_parents[] = { 413 "i2srx_bclk_mst_inv", "i2srx_bclk_mst", 414 }; 415 416 static struct jh71x0_clkc_clk jh7110_sysclk_clocks[] = { 417 418 JH71X0CLKC_FIXED_FACTOR(JH7110_SYSCLK_PLL0_OUT, "pll0_out", "osc", 3, 125), 419 JH71X0CLKC_FIXED_FACTOR(JH7110_SYSCLK_PLL1_OUT, "pll1_out", "osc", 12, 533), 420 JH71X0CLKC_FIXED_FACTOR(JH7110_SYSCLK_PLL2_OUT, "pll2_out", "osc", 2, 99), 421 422 JH71X0CLKC_MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", cpu_root_parents), 423 JH71X0CLKC_MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", gpu_root_parents), 424 JH71X0CLKC_MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", bus_root_parents), 425 426 427 JH71X0CLKC_DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, "cpu_root"), 428 JH71X0CLKC_DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, "cpu_core"), 429 430 JH71X0CLKC_MUXDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, perh_root_parents), 431 432 JH71X0CLKC_DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, "bus_root"), 433 JH71X0CLKC_DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, "bus_root"), 434 JH71X0CLKC_DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, "axi_cfg0"), 435 JH71X0CLKC_GATE(JH7110_SYSCLK_AHB0, "ahb0", "stg_axiahb"), // CLK_IS_CRITICAL, 436 JH71X0CLKC_GATE(JH7110_SYSCLK_AHB1, "ahb1", "stg_axiahb"),// CLK_IS_CRITICAL, 437 JH71X0CLKC_DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, "stg_axiahb"), 438 JH71X0CLKC_GATE(JH7110_SYSCLK_APB0, "apb0", "apb_bus"),// CLK_IS_CRITICAL, 439 JH71X0CLKC_DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, "pll0_out"), 440 JH71X0CLKC_DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, "pll1_out"), 441 JH71X0CLKC_DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, "pll2_out"), 442 JH71X0CLKC_DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, "pll2_out"), 443 JH71X0CLKC_DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, "audio_root"), 444 445 JH71X0CLKC_MUX(JH7110_SYSCLK_MCLK, "mclk", mclk_parents), 446 447 JH71X0CLKC_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", "mclk_inner"), 448 449 JH71X0CLKC_MUXDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, isp_2x_parents), 450 451 JH71X0CLKC_DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, "isp_2x"), 452 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GCLK0, "gclk0", 62, "pll0_div2"), 453 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GCLK1, "gclk1",62, "pll1_div2"), 454 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GCLK2, "gclk2",62, "pll2_div2"), 455 /* cores */ 456 JH71X0CLKC_GATE(JH7110_SYSCLK_CORE, "core", "cpu_core"),// CLK_IS_CRITICAL, 457 JH71X0CLKC_GATE(JH7110_SYSCLK_CORE1, "core1", "cpu_core"),// CLK_IS_CRITICAL, 458 JH71X0CLKC_GATE(JH7110_SYSCLK_CORE2, "core2", "cpu_core"),// CLK_IS_CRITICAL, 459 JH71X0CLKC_GATE(JH7110_SYSCLK_CORE3, "core3", "cpu_core"),// CLK_IS_CRITICAL, 460 JH71X0CLKC_GATE(JH7110_SYSCLK_CORE4, "core4", "cpu_core"),// CLK_IS_CRITICAL, 461 JH71X0CLKC_GATE(JH7110_SYSCLK_DEBUG, "debug", "cpu_bus"), 462 JH71X0CLKC_DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, "osc"), 463 JH71X0CLKC_GATE(JH7110_SYSCLK_TRACE0, "trace0", "cpu_core"), 464 JH71X0CLKC_GATE(JH7110_SYSCLK_TRACE1, "trace1", "cpu_core"), 465 JH71X0CLKC_GATE(JH7110_SYSCLK_TRACE2, "trace2", "cpu_core"), 466 JH71X0CLKC_GATE(JH7110_SYSCLK_TRACE3, "trace3", "cpu_core"), 467 JH71X0CLKC_GATE(JH7110_SYSCLK_TRACE4, "trace4", "cpu_core"), 468 JH71X0CLKC_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", "cpu_bus"), 469 /* noc */ 470 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", "cpu_bus"), // CLK_IS_CRITICAL, 471 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", "axi_cfg0"),// CLK_IS_CRITICAL, 472 /* ddr */ 473 JH71X0CLKC_DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, "osc"), 474 JH71X0CLKC_DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, "pll1_div2"), 475 JH71X0CLKC_DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, "pll1_div4"), 476 JH71X0CLKC_MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", ddr_bus_parents), 477 478 JH71X0CLKC_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", "ddr_bus"),// CLK_IS_CRITICAL, 479 /* gpu */ 480 JH71X0CLKC_DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, "gpu_root"), 481 JH71X0CLKC_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", "gpu_core"), 482 JH71X0CLKC_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", "isp_axi"), 483 JH71X0CLKC_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", "apb_bus"), 484 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 12, "osc"), 485 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", "gpu_core"), 486 /* isp */ 487 JH71X0CLKC_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", "isp_2x"), 488 JH71X0CLKC_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", "isp_axi"), 489 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", "isp_axi"), // CLK_IS_CRITICAL, 490 /* hifi4 */ 491 JH71X0CLKC_DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, "bus_root"), 492 JH71X0CLKC_DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, "hifi4_core"), 493 /* axi_cfg1 */ 494 JH71X0CLKC_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", "isp_axi"), // CLK_IS_CRITICAL 495 JH71X0CLKC_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", "ahb0"), // CLK_IS_CRITICAL 496 /* vout */ 497 JH71X0CLKC_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", "pll2_out"), 498 JH71X0CLKC_DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, "pll2_out"), 499 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", "vout_axi"), 500 JH71X0CLKC_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", "ahb1"), 501 JH71X0CLKC_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", "vout_axi"), 502 JH71X0CLKC_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", "mclk_out"), 503 JH71X0CLKC_DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2, "osc"), 504 /* jpegc */ 505 JH71X0CLKC_DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, "pll2_out"), 506 JH71X0CLKC_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", "jpegc_axi"), 507 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core",16, "pll2_out"), 508 JH71X0CLKC_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", "apb_bus"), 509 /* vdec */ 510 JH71X0CLKC_DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, "bus_root"), 511 JH71X0CLKC_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", "vdec_axi"), 512 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu",7, "bus_root"), 513 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 7, "pll0_out"), 514 JH71X0CLKC_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", "apb_bus"), 515 JH71X0CLKC_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", "jpegc_axi"), 516 JH71X0CLKC_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", "vdec_axi"), 517 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", "vdec_axi"), 518 /* venc */ 519 JH71X0CLKC_DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, "pll2_out"), 520 JH71X0CLKC_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", "venc_axi"), 521 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu",15, "pll2_out"), 522 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce",15, "pll2_out"), 523 JH71X0CLKC_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", "apb_bus"), 524 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", "venc_axi"), 525 /* axi_cfg0 */ 526 JH71X0CLKC_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", "ahb1"), // CLK_IS_CRITICAL 527 JH71X0CLKC_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", "axi_cfg0"), // CLK_IS_CRITICAL 528 JH71X0CLKC_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", "hifi4_axi"), // CLK_IS_CRITICAL, 529 /* intmem */ 530 JH71X0CLKC_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", "axi_cfg0"), 531 /* qspi */ 532 JH71X0CLKC_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", "ahb1"), 533 JH71X0CLKC_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", "apb_bus"), 534 JH71X0CLKC_DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, "pll0_out"), 535 JH71X0CLKC_MUXGATE(JH7110_SYSCLK_QSPI_REF, "qspi_ref", qspi_ref_parents), 536 537 /* sdio */ 538 JH71X0CLKC_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", "ahb0"), 539 JH71X0CLKC_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", "ahb0"), 540 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", 15, "axi_cfg0"), 541 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", 15, "axi_cfg0"), 542 /* stg */ 543 JH71X0CLKC_DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, "pll0_out"), 544 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", "nocstg_bus"), // CLK_IS_CRITICAL, 545 /* gmac1 */ 546 JH71X0CLKC_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", "ahb0"), 547 JH71X0CLKC_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", "stg_axiahb"), 548 JH71X0CLKC_DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, "pll0_out"), 549 JH71X0CLKC_DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, "pll0_out"), 550 JH71X0CLKC_DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30, "gmac1_rmii_refin"), 551 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp",31, "gmac_src"), 552 JH71X0CLKC_MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", gmac1_rx_parents), 553 554 JH71X0CLKC_INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", "gmac1_rx"), 555 JH71X0CLKC_MUXGATE_FLAGS(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx", gmac1_tx_parents, CLK_SET_RATE_PARENT), // CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 556 JH71X0CLKC_INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", "gmac1_tx"), 557 JH71X0CLKC_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", "gmac1_gtxclk"), 558 /* gmac0 */ 559 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk",15, "pll0_out"), 560 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp",31, "gmac_src"), 561 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy",31, "gmac_src"), 562 JH71X0CLKC_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", "gmac0_gtxclk"), 563 /* apb misc */ 564 JH71X0CLKC_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", "apb_bus"), 565 JH71X0CLKC_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", "apb_bus"), 566 JH71X0CLKC_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", "apb_bus"), 567 /* can0 */ 568 JH71X0CLKC_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", "apb_bus"), 569 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer",24, "osc"), 570 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can",63, "perh_root"), 571 /* can1 */ 572 JH71X0CLKC_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", "apb_bus"), 573 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer",24, "osc"), 574 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can",63, "perh_root"), 575 /* pwm */ 576 JH71X0CLKC_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", "apb_bus"), 577 /* wdt */ 578 JH71X0CLKC_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", "apb_bus"), 579 JH71X0CLKC_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", "osc"), 580 /* timer */ 581 JH71X0CLKC_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", "apb_bus"), 582 JH71X0CLKC_GATE(JH7110_SYSCLK_TIMER0, "timer0", "osc"), 583 JH71X0CLKC_GATE(JH7110_SYSCLK_TIMER1, "timer1", "osc"), 584 JH71X0CLKC_GATE(JH7110_SYSCLK_TIMER2, "timer2", "osc"), 585 JH71X0CLKC_GATE(JH7110_SYSCLK_TIMER3, "timer3", "osc"), 586 /* temp sensor */ 587 JH71X0CLKC_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", "apb_bus"), 588 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core",24, "osc"), 589 /* spi */ 590 JH71X0CLKC_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", "apb0"), 591 JH71X0CLKC_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", "apb0"), 592 JH71X0CLKC_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", "apb0"), 593 JH71X0CLKC_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", "apb_bus"), 594 JH71X0CLKC_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", "apb_bus"), 595 JH71X0CLKC_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", "apb_bus"), 596 JH71X0CLKC_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", "apb_bus"), 597 /* i2c */ 598 JH71X0CLKC_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", "apb0"), 599 JH71X0CLKC_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", "apb0"), 600 JH71X0CLKC_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", "apb0"), 601 JH71X0CLKC_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", "apb_bus"), 602 JH71X0CLKC_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", "apb_bus"), 603 JH71X0CLKC_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", "apb_bus"), 604 JH71X0CLKC_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", "apb_bus"), 605 /* uart */ 606 JH71X0CLKC_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", "apb0"), 607 JH71X0CLKC_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", "osc"), 608 JH71X0CLKC_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", "apb0"), 609 JH71X0CLKC_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", "osc"), 610 JH71X0CLKC_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", "apb0"), 611 JH71X0CLKC_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", "osc"), 612 JH71X0CLKC_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", "apb0"), 613 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core",10, "perh_root"), 614 JH71X0CLKC_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", "apb0"), 615 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core",10, "perh_root"), 616 JH71X0CLKC_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", "apb0"), 617 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core",10, "perh_root"), 618 /* pwmdac */ 619 JH71X0CLKC_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", "apb0"), 620 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core",256, "audio_root"), 621 /* spdif */ 622 JH71X0CLKC_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", "apb0"), 623 JH71X0CLKC_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", "mclk_out"), 624 /* i2stx0 */ 625 JH71X0CLKC_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", "apb0"), 626 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst",32, "mclk_out"), 627 JH71X0CLKC_INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv", "i2stx0_bclk_mst"), 628 629 JH71X0CLKC_MUXDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, i2stx0_lrck_mst_parents), 630 631 JH71X0CLKC_MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", i2stx0_bclk_parents), 632 JH71X0CLKC_INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", "i2stx0_bclk"), 633 JH71X0CLKC_MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", i2stx0_lrck_parents), 634 /* i2stx1 */ 635 JH71X0CLKC_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", "apb0"), 636 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst",32, "mclk_out"), 637 JH71X0CLKC_INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv", "i2stx1_bclk_mst"), 638 639 JH71X0CLKC_MUXDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, i2stx1_lrck_mst_parents), 640 641 JH71X0CLKC_MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", i2stx1_bclk_parents), 642 JH71X0CLKC_INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", "i2stx1_bclk"), 643 JH71X0CLKC_MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", i2stx1_lrck_parents), 644 /* i2srx */ 645 JH71X0CLKC_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", "apb0"), 646 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 32, "mclk_out"), 647 JH71X0CLKC_INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv", "i2srx_bclk_mst"), 648 649 JH71X0CLKC_MUXDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, i2srx_lrck_mst_parents), 650 651 JH71X0CLKC_MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", i2srx_bclk_root_parents), 652 JH71X0CLKC_INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", "i2srx_bclk"), 653 JH71X0CLKC_MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", i2srx_lrck_parents), 654 /* pdm */ 655 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic",64, "mclk_out"), 656 JH71X0CLKC_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", "apb0"), 657 /* tdm */ 658 JH71X0CLKC_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", "ahb0"), 659 JH71X0CLKC_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", "apb0"), 660 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal",64, "mclk_out"), 661 JH71X0CLKC_MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", tdm_tdm_parents), 662 JH71X0CLKC_INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", "tdm_tdm"), 663 /* jtag */ 664 JH71X0CLKC_DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4, "osc"), 665 }; 666 667 static const char *apb_func_parents[] = { 668 "osc_div4", "osc", 669 }; 670 671 static const char *gmac0_tx_parents[] = { 672 "gmac0_gtxclk", "gmac0_rmii_rtx" 673 }; 674 675 static const char *gmac0_rx_parents[] = { 676 "gmac0_rgmii_rxin", "gmac0_rmii_rtx", 677 }; 678 679 static const char *rtc_32k_parents[] = { 680 "rtc_osc", "rtc_internal", 681 }; 682 683 static struct jh71x0_clkc_clk jh7110_aonclk_clocks[] = { 684 /* source */ 685 JH71X0CLKC_DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, "osc"), 686 JH71X0CLKC_MUX(JH7110_AONCLK_APB_FUNC, "apb_func", apb_func_parents), 687 /* gmac0 */ 688 JH71X0CLKC_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", "stg_axiahb"), 689 JH71X0CLKC_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", "stg_axiahb"), 690 JH71X0CLKC_DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30, "gmac0_rmii_refin"), 691 JH71X0CLKC_MUXGATE(JH7110_AONCLK_GMAC0_TX, "gmac0_tx",gmac0_tx_parents), 692 JH71X0CLKC_INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", "gmac0_tx"), 693 JH71X0CLKC_MUX_FLAGS(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", gmac0_rx_parents, CLK_SET_RATE_PARENT), // CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT 694 JH71X0CLKC_INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", "gmac0_rx"), 695 /* otpc */ 696 JH71X0CLKC_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", "apb_bus"), 697 /* rtc */ 698 JH71X0CLKC_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", "apb_bus"), 699 JH71X0CLKC_DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, "osc"), 700 JH71X0CLKC_MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", rtc_32k_parents), 701 JH71X0CLKC_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", "osc"), 702 }; 703 704 705 static struct jh71x0_clkc_clk jh7110_stgclk_clocks[] = { 706 /* hifi4 */ 707 JH71X0CLKC_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", "hifi4_core"), 708 /* usb */ 709 JH71X0CLKC_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", "apb_bus"), 710 JH71X0CLKC_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", "apb_bus"), 711 JH71X0CLKC_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", "stg_axiahb"), 712 JH71X0CLKC_GATEDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 2, "osc"), 713 JH71X0CLKC_GATEDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 4, "osc"), 714 JH71X0CLKC_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", "usb_125m"), 715 JH71X0CLKC_DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, "osc"), 716 /* pci-e */ 717 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", "stg_axiahb"), 718 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", "apb_bus"), 719 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", "stg_axiahb"), 720 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", "stg_axiahb"), 721 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", "apb_bus"), 722 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", "stg_axiahb"), 723 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", "stg_axiahb"), // CLK_IS_CRITICAL 724 /* security */ 725 JH71X0CLKC_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", "stg_axiahb"), 726 JH71X0CLKC_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", "stg_axiahb"), 727 /* stg mtrx */ 728 JH71X0CLKC_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", "cpu_bus"), // CLK_IS_CRITICAL 729 JH71X0CLKC_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", "nocstg_bus"), // CLK_IS_CRITICAL 730 JH71X0CLKC_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", "stg_axiahb"), // CLK_IS_CRITICAL 731 JH71X0CLKC_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", "cpu_bus"), // CLK_IS_CRITICAL 732 JH71X0CLKC_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", "nocstg_bus"), // CLK_IS_CRITICAL 733 JH71X0CLKC_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", "stg_axiahb"), // CLK_IS_CRITICAL 734 JH71X0CLKC_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", "hifi4_axi"), // CLK_IS_CRITICAL 735 /* e24_rvpi */ 736 JH71X0CLKC_GATEDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 24, "osc"), 737 JH71X0CLKC_GATE(JH7110_STGCLK_E2_CORE, "e2_core", "stg_axiahb"), 738 JH71X0CLKC_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", "stg_axiahb"), 739 /* dw_sgdma1p */ 740 JH71X0CLKC_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", "stg_axiahb"), 741 JH71X0CLKC_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", "stg_axiahb"), 742 }; 743 744 #if 0 745 static const char *vin_p_axi_wr_parents[] = { 746 "mipi_rx0_pxl", "dvp_inv", 747 }; 748 749 static const char *ispv2_top_wrapper_c_parents[] = { 750 "mipi_rx0_pxl", "dvp_inv", 751 }; 752 753 static struct jh71x0_clkc_clk jh7110_ispclk_clocks[] = { 754 /* syscon */ 755 JH71X0CLKC_DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15, "isp_top_axi"), 756 JH71X0CLKC_DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8, "isp_top_core"), 757 JH71X0CLKC_INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", "dvp_clk"), 758 /* vin */ 759 JH71X0CLKC_DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16, "isp_top_core"), 760 JH71X0CLKC_DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16, "isp_top_core"), 761 JH71X0CLKC_DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60, "isp_top_core"), 762 JH71X0CLKC_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", "dom4_apb_func"), 763 JH71X0CLKC_DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, "isp_top_core"), 764 JH71X0CLKC_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", "mipi_rx0_pxl"), 765 JH71X0CLKC_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", "mipi_rx0_pxl"), 766 JH71X0CLKC_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", "mipi_rx0_pxl"), 767 JH71X0CLKC_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", "mipi_rx0_pxl"), 768 JH71X0CLKC_MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", vin_p_axi_wr_parents), 769 /* ispv2_top_wrapper */ 770 JH71X0CLKC_MUXGATE(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", ispv2_top_wrapper_c_parents), 771 }; 772 #endif 773 774 static const char *dc8200_pix0_parents[] = { 775 "dc8200_pix", "hdmitx0_pixelclk", 776 }; 777 778 static const char *dc8200_pix1_parents[] = { 779 "dc8200_pix", "hdmitx0_pixelclk", 780 }; 781 782 static const char *dsiTx_dpi_parents[] = { 783 "dc8200_pix", "hdmitx0_pixelclk", 784 }; 785 786 static const char *dom_vout_top_lcd_parents[] = { 787 "dc8200_pix0", "dc8200_pix1", 788 }; 789 790 static struct jh71x0_clkc_clk jh7110_voutclk_clocks[] = { 791 /* divider */ 792 JH71X0CLKC_DIV(JH7110_VOUTCLK_APB, "apb", 8, "vout_top_ahb"), 793 JH71X0CLKC_DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, "vout_src"), 794 JH71X0CLKC_DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, "vout_src"), 795 JH71X0CLKC_DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, "vout_top_ahb"), 796 /* dc8200 */ 797 JH71X0CLKC_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", "vout_top_axi"), 798 JH71X0CLKC_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", "vout_top_axi"), 799 JH71X0CLKC_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", "vout_top_ahb"), 800 JH71X0CLKC_MUXGATE(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", dc8200_pix0_parents), 801 JH71X0CLKC_MUXGATE(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", dc8200_pix1_parents), 802 /* LCD */ 803 JH71X0CLKC_MUXGATE(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", dom_vout_top_lcd_parents), 804 /* dsiTx */ 805 JH71X0CLKC_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", "dsi_sys"), 806 JH71X0CLKC_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", "dsi_sys"), 807 JH71X0CLKC_MUXGATE(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", dsiTx_dpi_parents), 808 JH71X0CLKC_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", "tx_esc"), 809 /* mipitx DPHY */ 810 JH71X0CLKC_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", "tx_esc"), 811 /* hdmi */ 812 JH71X0CLKC_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", "vout_top_hdmitx0_mclk"), 813 JH71X0CLKC_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", "i2stx0_bclk"), 814 JH71X0CLKC_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", "apb"), 815 }; 816 817 struct jh7110_clock_config { 818 struct jh71x0_clkc_clk *jhcc_clocks; 819 size_t jhcc_nclks; 820 }; 821 822 static struct jh7110_clock_config jh7110_aonclk_config = { 823 .jhcc_clocks = jh7110_aonclk_clocks, 824 .jhcc_nclks = __arraycount(jh7110_aonclk_clocks), 825 }; 826 827 #if 0 828 static struct jh7110_clock_config jh7110_ispclk_config = { 829 .jhcc_clocks = jh7110_ispclk_clocks, 830 .jhcc_nclks = __arraycount(jh7110_ispclk_clocks), 831 }; 832 #endif 833 834 static struct jh7110_clock_config jh7110_stgclk_config = { 835 .jhcc_clocks = jh7110_stgclk_clocks, 836 .jhcc_nclks = __arraycount(jh7110_stgclk_clocks), 837 }; 838 839 static struct jh7110_clock_config jh7110_sysclk_config = { 840 .jhcc_clocks = jh7110_sysclk_clocks, 841 .jhcc_nclks = __arraycount(jh7110_sysclk_clocks), 842 }; 843 844 static struct jh7110_clock_config jh7110_voutclk_config = { 845 .jhcc_clocks = jh7110_voutclk_clocks, 846 .jhcc_nclks = __arraycount(jh7110_voutclk_clocks), 847 }; 848 849 850 struct jh7110_crg { 851 const char *jhc_name; 852 struct jh7110_clock_config *jhc_clk; 853 }; 854 855 856 static struct jh7110_crg jh7110_sys_config = { 857 .jhc_name = "System", 858 .jhc_clk = &jh7110_sysclk_config, 859 }; 860 861 862 static struct jh7110_crg jh7110_aon_config = { 863 .jhc_name = "Always-On", 864 .jhc_clk = &jh7110_aonclk_config, 865 }; 866 867 #if 0 868 static struct jh7110_crg jh7110_isp_config = { 869 .jhc_name = "Image-Signal-Process", 870 .jhc_clk = &jh7110_ispclk_config, 871 }; 872 #endif 873 874 static struct jh7110_crg jh7110_stg_config = { 875 .jhc_name = "System-Top-Group", 876 .jhc_clk = &jh7110_stgclk_config, 877 }; 878 879 static struct jh7110_crg jh7110_vout_config = { 880 .jhc_name = "Video Output", 881 .jhc_clk = &jh7110_voutclk_config, 882 }; 883 884 885 static const struct device_compatible_entry compat_data[] = { 886 { .compat = "starfive,jh7110-syscrg", .data = &jh7110_sys_config }, 887 { .compat = "starfive,jh7110-aoncrg", .data = &jh7110_aon_config }, 888 #if 0 889 { .compat = "starfive,jh7110-ispcrg", .data = &jh7110_isp_config }, 890 #endif 891 { .compat = "starfive,jh7110-stgcrg", .data = &jh7110_stg_config }, 892 { .compat = "starfive,jh7110-voutcrg", .data = &jh7110_vout_config }, 893 DEVICE_COMPAT_EOL 894 }; 895 896 897 #define RD4(sc, reg) \ 898 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 899 #define WR4(sc, reg, val) \ 900 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 901 902 903 static struct clk * 904 jh7110_clkc_clock_decode(device_t dev, int phandle, const void *data, 905 size_t len) 906 { 907 struct jh71x0_clkc_softc * const sc = device_private(dev); 908 909 if (len != 4) { 910 return NULL; 911 } 912 913 u_int id = be32dec(data); 914 if (id >= sc->sc_nclks) { 915 return NULL; 916 } 917 if (sc->sc_clk[id].jcc_type == JH71X0CLK_UNKNOWN) { 918 printf("Unknown clock %d\n", id); 919 return NULL; 920 } 921 return &sc->sc_clk[id].jcc_clk; 922 } 923 924 static const struct fdtbus_clock_controller_func jh7110_clkc_fdtclock_funcs = { 925 .decode = jh7110_clkc_clock_decode 926 }; 927 928 static int 929 jh7110_clkc_match(device_t parent, cfdata_t cf, void *aux) 930 { 931 struct fdt_attach_args * const faa = aux; 932 933 return of_compatible_match(faa->faa_phandle, compat_data); 934 } 935 936 static void 937 jh7110_clkc_attach(device_t parent, device_t self, void *aux) 938 { 939 struct jh71x0_clkc_softc * const sc = device_private(self); 940 struct fdt_attach_args * const faa = aux; 941 const int phandle = faa->faa_phandle; 942 bus_addr_t addr; 943 bus_size_t size; 944 945 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 946 aprint_error(": couldn't get registers\n"); 947 return; 948 } 949 950 sc->sc_dev = self; 951 sc->sc_phandle = phandle; 952 sc->sc_bst = faa->faa_bst; 953 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 954 aprint_error(": couldn't map registers\n"); 955 return; 956 } 957 958 sc->sc_clkdom.name = device_xname(self); 959 sc->sc_clkdom.funcs = &jh71x0_clkc_funcs; 960 sc->sc_clkdom.priv = sc; 961 962 const struct jh7110_crg *jhc = 963 of_compatible_lookup(phandle, compat_data)->data; 964 KASSERT(jhc != NULL); 965 966 struct jh7110_clock_config * const jhcc = jhc->jhc_clk; 967 sc->sc_clk = jhcc->jhcc_clocks; 968 sc->sc_nclks = jhcc->jhcc_nclks; 969 970 for (size_t id = 0; id < sc->sc_nclks; id++) { 971 if (sc->sc_clk[id].jcc_type == JH71X0CLK_UNKNOWN) 972 continue; 973 974 sc->sc_clk[id].jcc_clk.domain = &sc->sc_clkdom; 975 // Names already populated. 976 clk_attach(&sc->sc_clk[id].jcc_clk); 977 } 978 979 aprint_naive("\n"); 980 aprint_normal(": JH7110 %s Clock and Reset Generator\n", 981 jhc->jhc_name); 982 983 for (size_t id = 0; id < sc->sc_nclks; id++) { 984 if (sc->sc_clk[id].jcc_type == JH71X0CLK_UNKNOWN) 985 continue; 986 987 struct clk * const clk = &sc->sc_clk[id].jcc_clk; 988 989 aprint_debug_dev(self, "id %zu [%s]: %u Hz\n", id, 990 clk->name ? clk->name : "<none>", clk_get_rate(clk)); 991 } 992 993 fdtbus_register_clock_controller(self, phandle, &jh7110_clkc_fdtclock_funcs); 994 } 995 996 CFATTACH_DECL_NEW(jh7110_clkc, sizeof(struct jh71x0_clkc_softc), 997 jh7110_clkc_match, jh7110_clkc_attach, NULL, NULL); 998
Indexes created Mon Sep 29 21:09:56 GMT 2025