jh7110_clkc.c revision 1.5
1 /* $NetBSD: jh7110_clkc.c,v 1.5 2024/09/18 10:37:03 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2023 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Nick Hudson 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: jh7110_clkc.c,v 1.5 2024/09/18 10:37:03 skrll Exp $"); 34 35 #include <sys/param.h> 36 37 #include <sys/bus.h> 38 #include <sys/device.h> 39 40 #include <dev/clk/clk_backend.h> 41 42 #include <dev/fdt/fdtvar.h> 43 44 #include <riscv/starfive/jh71x0_clkc.h> 45 46 /* SYSCRG clocks */ 47 #define JH7110_SYSCLK_CPU_ROOT 0 48 #define JH7110_SYSCLK_CPU_CORE 1 49 #define JH7110_SYSCLK_CPU_BUS 2 50 #define JH7110_SYSCLK_GPU_ROOT 3 51 #define JH7110_SYSCLK_PERH_ROOT 4 52 #define JH7110_SYSCLK_BUS_ROOT 5 53 #define JH7110_SYSCLK_NOCSTG_BUS 6 54 #define JH7110_SYSCLK_AXI_CFG0 7 55 #define JH7110_SYSCLK_STG_AXIAHB 8 56 #define JH7110_SYSCLK_AHB0 9 57 #define JH7110_SYSCLK_AHB1 10 58 #define JH7110_SYSCLK_APB_BUS 11 59 #define JH7110_SYSCLK_APB0 12 60 #define JH7110_SYSCLK_PLL0_DIV2 13 61 #define JH7110_SYSCLK_PLL1_DIV2 14 62 #define JH7110_SYSCLK_PLL2_DIV2 15 63 #define JH7110_SYSCLK_AUDIO_ROOT 16 64 #define JH7110_SYSCLK_MCLK_INNER 17 65 #define JH7110_SYSCLK_MCLK 18 66 #define JH7110_SYSCLK_MCLK_OUT 19 67 #define JH7110_SYSCLK_ISP_2X 20 68 #define JH7110_SYSCLK_ISP_AXI 21 69 #define JH7110_SYSCLK_GCLK0 22 70 #define JH7110_SYSCLK_GCLK1 23 71 #define JH7110_SYSCLK_GCLK2 24 72 #define JH7110_SYSCLK_CORE 25 73 #define JH7110_SYSCLK_CORE1 26 74 #define JH7110_SYSCLK_CORE2 27 75 #define JH7110_SYSCLK_CORE3 28 76 #define JH7110_SYSCLK_CORE4 29 77 #define JH7110_SYSCLK_DEBUG 30 78 #define JH7110_SYSCLK_RTC_TOGGLE 31 79 #define JH7110_SYSCLK_TRACE0 32 80 #define JH7110_SYSCLK_TRACE1 33 81 #define JH7110_SYSCLK_TRACE2 34 82 #define JH7110_SYSCLK_TRACE3 35 83 #define JH7110_SYSCLK_TRACE4 36 84 #define JH7110_SYSCLK_TRACE_COM 37 85 #define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38 86 #define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39 87 #define JH7110_SYSCLK_OSC_DIV2 40 88 #define JH7110_SYSCLK_PLL1_DIV4 41 89 #define JH7110_SYSCLK_PLL1_DIV8 42 90 #define JH7110_SYSCLK_DDR_BUS 43 91 #define JH7110_SYSCLK_DDR_AXI 44 92 #define JH7110_SYSCLK_GPU_CORE 45 93 #define JH7110_SYSCLK_GPU_CORE_CLK 46 94 #define JH7110_SYSCLK_GPU_SYS_CLK 47 95 #define JH7110_SYSCLK_GPU_APB 48 96 #define JH7110_SYSCLK_GPU_RTC_TOGGLE 49 97 #define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50 98 #define JH7110_SYSCLK_ISP_TOP_CORE 51 99 #define JH7110_SYSCLK_ISP_TOP_AXI 52 100 #define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53 101 #define JH7110_SYSCLK_HIFI4_CORE 54 102 #define JH7110_SYSCLK_HIFI4_AXI 55 103 #define JH7110_SYSCLK_AXI_CFG1_MAIN 56 104 #define JH7110_SYSCLK_AXI_CFG1_AHB 57 105 #define JH7110_SYSCLK_VOUT_SRC 58 106 #define JH7110_SYSCLK_VOUT_AXI 59 107 #define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60 108 #define JH7110_SYSCLK_VOUT_TOP_AHB 61 109 #define JH7110_SYSCLK_VOUT_TOP_AXI 62 110 #define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 63 111 #define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 64 112 #define JH7110_SYSCLK_JPEGC_AXI 65 113 #define JH7110_SYSCLK_CODAJ12_AXI 66 114 #define JH7110_SYSCLK_CODAJ12_CORE 67 115 #define JH7110_SYSCLK_CODAJ12_APB 68 116 #define JH7110_SYSCLK_VDEC_AXI 69 117 #define JH7110_SYSCLK_WAVE511_AXI 70 118 #define JH7110_SYSCLK_WAVE511_BPU 71 119 #define JH7110_SYSCLK_WAVE511_VCE 72 120 #define JH7110_SYSCLK_WAVE511_APB 73 121 #define JH7110_SYSCLK_VDEC_JPG 74 122 #define JH7110_SYSCLK_VDEC_MAIN 75 123 #define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76 124 #define JH7110_SYSCLK_VENC_AXI 77 125 #define JH7110_SYSCLK_WAVE420L_AXI 78 126 #define JH7110_SYSCLK_WAVE420L_BPU 79 127 #define JH7110_SYSCLK_WAVE420L_VCE 80 128 #define JH7110_SYSCLK_WAVE420L_APB 81 129 #define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82 130 #define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83 131 #define JH7110_SYSCLK_AXI_CFG0_MAIN 84 132 #define JH7110_SYSCLK_AXI_CFG0_HIFI4 85 133 #define JH7110_SYSCLK_AXIMEM2_AXI 86 134 #define JH7110_SYSCLK_QSPI_AHB 87 135 #define JH7110_SYSCLK_QSPI_APB 88 136 #define JH7110_SYSCLK_QSPI_REF_SRC 89 137 #define JH7110_SYSCLK_QSPI_REF 90 138 #define JH7110_SYSCLK_SDIO0_AHB 91 139 #define JH7110_SYSCLK_SDIO1_AHB 92 140 #define JH7110_SYSCLK_SDIO0_SDCARD 93 141 #define JH7110_SYSCLK_SDIO1_SDCARD 94 142 #define JH7110_SYSCLK_USB_125M 95 143 #define JH7110_SYSCLK_NOC_BUS_STG_AXI 96 144 #define JH7110_SYSCLK_GMAC1_AHB 97 145 #define JH7110_SYSCLK_GMAC1_AXI 98 146 #define JH7110_SYSCLK_GMAC_SRC 99 147 #define JH7110_SYSCLK_GMAC1_GTXCLK 100 148 #define JH7110_SYSCLK_GMAC1_RMII_RTX 101 149 #define JH7110_SYSCLK_GMAC1_PTP 102 150 #define JH7110_SYSCLK_GMAC1_RX 103 151 #define JH7110_SYSCLK_GMAC1_RX_INV 104 152 #define JH7110_SYSCLK_GMAC1_TX 105 153 #define JH7110_SYSCLK_GMAC1_TX_INV 106 154 #define JH7110_SYSCLK_GMAC1_GTXC 107 155 #define JH7110_SYSCLK_GMAC0_GTXCLK 108 156 #define JH7110_SYSCLK_GMAC0_PTP 109 157 #define JH7110_SYSCLK_GMAC_PHY 110 158 #define JH7110_SYSCLK_GMAC0_GTXC 111 159 #define JH7110_SYSCLK_IOMUX_APB 112 160 #define JH7110_SYSCLK_MAILBOX_APB 113 161 #define JH7110_SYSCLK_INT_CTRL_APB 114 162 #define JH7110_SYSCLK_CAN0_APB 115 163 #define JH7110_SYSCLK_CAN0_TIMER 116 164 #define JH7110_SYSCLK_CAN0_CAN 117 165 #define JH7110_SYSCLK_CAN1_APB 118 166 #define JH7110_SYSCLK_CAN1_TIMER 119 167 #define JH7110_SYSCLK_CAN1_CAN 120 168 #define JH7110_SYSCLK_PWM_APB 121 169 #define JH7110_SYSCLK_WDT_APB 122 170 #define JH7110_SYSCLK_WDT_CORE 123 171 #define JH7110_SYSCLK_TIMER_APB 124 172 #define JH7110_SYSCLK_TIMER0 125 173 #define JH7110_SYSCLK_TIMER1 126 174 #define JH7110_SYSCLK_TIMER2 127 175 #define JH7110_SYSCLK_TIMER3 128 176 #define JH7110_SYSCLK_TEMP_APB 129 177 #define JH7110_SYSCLK_TEMP_CORE 130 178 #define JH7110_SYSCLK_SPI0_APB 131 179 #define JH7110_SYSCLK_SPI1_APB 132 180 #define JH7110_SYSCLK_SPI2_APB 133 181 #define JH7110_SYSCLK_SPI3_APB 134 182 #define JH7110_SYSCLK_SPI4_APB 135 183 #define JH7110_SYSCLK_SPI5_APB 136 184 #define JH7110_SYSCLK_SPI6_APB 137 185 #define JH7110_SYSCLK_I2C0_APB 138 186 #define JH7110_SYSCLK_I2C1_APB 139 187 #define JH7110_SYSCLK_I2C2_APB 140 188 #define JH7110_SYSCLK_I2C3_APB 141 189 #define JH7110_SYSCLK_I2C4_APB 142 190 #define JH7110_SYSCLK_I2C5_APB 143 191 #define JH7110_SYSCLK_I2C6_APB 144 192 #define JH7110_SYSCLK_UART0_APB 145 193 #define JH7110_SYSCLK_UART0_CORE 146 194 #define JH7110_SYSCLK_UART1_APB 147 195 #define JH7110_SYSCLK_UART1_CORE 148 196 #define JH7110_SYSCLK_UART2_APB 149 197 #define JH7110_SYSCLK_UART2_CORE 150 198 #define JH7110_SYSCLK_UART3_APB 151 199 #define JH7110_SYSCLK_UART3_CORE 152 200 #define JH7110_SYSCLK_UART4_APB 153 201 #define JH7110_SYSCLK_UART4_CORE 154 202 #define JH7110_SYSCLK_UART5_APB 155 203 #define JH7110_SYSCLK_UART5_CORE 156 204 #define JH7110_SYSCLK_PWMDAC_APB 157 205 #define JH7110_SYSCLK_PWMDAC_CORE 158 206 #define JH7110_SYSCLK_SPDIF_APB 159 207 #define JH7110_SYSCLK_SPDIF_CORE 160 208 #define JH7110_SYSCLK_I2STX0_APB 161 209 #define JH7110_SYSCLK_I2STX0_BCLK_MST 162 210 #define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163 211 #define JH7110_SYSCLK_I2STX0_LRCK_MST 164 212 #define JH7110_SYSCLK_I2STX0_BCLK 165 213 #define JH7110_SYSCLK_I2STX0_BCLK_INV 166 214 #define JH7110_SYSCLK_I2STX0_LRCK 167 215 #define JH7110_SYSCLK_I2STX1_APB 168 216 #define JH7110_SYSCLK_I2STX1_BCLK_MST 169 217 #define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170 218 #define JH7110_SYSCLK_I2STX1_LRCK_MST 171 219 #define JH7110_SYSCLK_I2STX1_BCLK 172 220 #define JH7110_SYSCLK_I2STX1_BCLK_INV 173 221 #define JH7110_SYSCLK_I2STX1_LRCK 174 222 #define JH7110_SYSCLK_I2SRX_APB 175 223 #define JH7110_SYSCLK_I2SRX_BCLK_MST 176 224 #define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177 225 #define JH7110_SYSCLK_I2SRX_LRCK_MST 178 226 #define JH7110_SYSCLK_I2SRX_BCLK 179 227 #define JH7110_SYSCLK_I2SRX_BCLK_INV 180 228 #define JH7110_SYSCLK_I2SRX_LRCK 181 229 #define JH7110_SYSCLK_PDM_DMIC 182 230 #define JH7110_SYSCLK_PDM_APB 183 231 #define JH7110_SYSCLK_TDM_AHB 184 232 #define JH7110_SYSCLK_TDM_APB 185 233 #define JH7110_SYSCLK_TDM_INTERNAL 186 234 #define JH7110_SYSCLK_TDM_TDM 187 235 #define JH7110_SYSCLK_TDM_TDM_INV 188 236 #define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189 237 238 #define JH7110_SYSCLK_NCLKS 190 239 240 /* external clocks */ 241 #define JH7110_SYSCLK_PLL0_OUT (JH7110_SYSCLK_NCLKS + 0) 242 #define JH7110_SYSCLK_PLL1_OUT (JH7110_SYSCLK_NCLKS + 1) 243 #define JH7110_SYSCLK_PLL2_OUT (JH7110_SYSCLK_NCLKS + 2) 244 245 /* AONCRG clocks */ 246 #define JH7110_AONCLK_OSC_DIV4 0 247 #define JH7110_AONCLK_APB_FUNC 1 248 #define JH7110_AONCLK_GMAC0_AHB 2 249 #define JH7110_AONCLK_GMAC0_AXI 3 250 #define JH7110_AONCLK_GMAC0_RMII_RTX 4 251 #define JH7110_AONCLK_GMAC0_TX 5 252 #define JH7110_AONCLK_GMAC0_TX_INV 6 253 #define JH7110_AONCLK_GMAC0_RX 7 254 #define JH7110_AONCLK_GMAC0_RX_INV 8 255 #define JH7110_AONCLK_OTPC_APB 9 256 #define JH7110_AONCLK_RTC_APB 10 257 #define JH7110_AONCLK_RTC_INTERNAL 11 258 #define JH7110_AONCLK_RTC_32K 12 259 #define JH7110_AONCLK_RTC_CAL 13 260 261 #define JH7110_AONCLK_NCLKS 14 262 263 /* STGCRG clocks */ 264 #define JH7110_STGCLK_HIFI4_CLK_CORE 0 265 #define JH7110_STGCLK_USB0_APB 1 266 #define JH7110_STGCLK_USB0_UTMI_APB 2 267 #define JH7110_STGCLK_USB0_AXI 3 268 #define JH7110_STGCLK_USB0_LPM 4 269 #define JH7110_STGCLK_USB0_STB 5 270 #define JH7110_STGCLK_USB0_APP_125 6 271 #define JH7110_STGCLK_USB0_REFCLK 7 272 #define JH7110_STGCLK_PCIE0_AXI_MST0 8 273 #define JH7110_STGCLK_PCIE0_APB 9 274 #define JH7110_STGCLK_PCIE0_TL 10 275 #define JH7110_STGCLK_PCIE1_AXI_MST0 11 276 #define JH7110_STGCLK_PCIE1_APB 12 277 #define JH7110_STGCLK_PCIE1_TL 13 278 #define JH7110_STGCLK_PCIE_SLV_MAIN 14 279 #define JH7110_STGCLK_SEC_AHB 15 280 #define JH7110_STGCLK_SEC_MISC_AHB 16 281 #define JH7110_STGCLK_GRP0_MAIN 17 282 #define JH7110_STGCLK_GRP0_BUS 18 283 #define JH7110_STGCLK_GRP0_STG 19 284 #define JH7110_STGCLK_GRP1_MAIN 20 285 #define JH7110_STGCLK_GRP1_BUS 21 286 #define JH7110_STGCLK_GRP1_STG 22 287 #define JH7110_STGCLK_GRP1_HIFI 23 288 #define JH7110_STGCLK_E2_RTC 24 289 #define JH7110_STGCLK_E2_CORE 25 290 #define JH7110_STGCLK_E2_DBG 26 291 #define JH7110_STGCLK_DMA1P_AXI 27 292 #define JH7110_STGCLK_DMA1P_AHB 28 293 294 #define JH7110_STGCLK_NCLKS 29 295 296 /* ISPCRG clocks */ 297 #define JH7110_ISPCLK_DOM4_APB_FUNC 0 298 #define JH7110_ISPCLK_MIPI_RX0_PXL 1 299 #define JH7110_ISPCLK_DVP_INV 2 300 #define JH7110_ISPCLK_M31DPHY_CFG_IN 3 301 #define JH7110_ISPCLK_M31DPHY_REF_IN 4 302 #define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0 5 303 #define JH7110_ISPCLK_VIN_APB 6 304 #define JH7110_ISPCLK_VIN_SYS 7 305 #define JH7110_ISPCLK_VIN_PIXEL_IF0 8 306 #define JH7110_ISPCLK_VIN_PIXEL_IF1 9 307 #define JH7110_ISPCLK_VIN_PIXEL_IF2 10 308 #define JH7110_ISPCLK_VIN_PIXEL_IF3 11 309 #define JH7110_ISPCLK_VIN_P_AXI_WR 12 310 #define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C 13 311 312 #define JH7110_ISPCLK_NCLKS 14 313 314 /* VOUTCRG clocks */ 315 #define JH7110_VOUTCLK_APB 0 316 #define JH7110_VOUTCLK_DC8200_PIX 1 317 #define JH7110_VOUTCLK_DSI_SYS 2 318 #define JH7110_VOUTCLK_TX_ESC 3 319 #define JH7110_VOUTCLK_DC8200_AXI 4 320 #define JH7110_VOUTCLK_DC8200_CORE 5 321 #define JH7110_VOUTCLK_DC8200_AHB 6 322 #define JH7110_VOUTCLK_DC8200_PIX0 7 323 #define JH7110_VOUTCLK_DC8200_PIX1 8 324 #define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD 9 325 #define JH7110_VOUTCLK_DSITX_APB 10 326 #define JH7110_VOUTCLK_DSITX_SYS 11 327 #define JH7110_VOUTCLK_DSITX_DPI 12 328 #define JH7110_VOUTCLK_DSITX_TXESC 13 329 #define JH7110_VOUTCLK_MIPITX_DPHY_TXESC 14 330 #define JH7110_VOUTCLK_HDMI_TX_MCLK 15 331 #define JH7110_VOUTCLK_HDMI_TX_BCLK 16 332 #define JH7110_VOUTCLK_HDMI_TX_SYS 17 333 334 #define JH7110_VOUTCLK_NCLKS 18 335 336 static const char *cpu_root_parents[] = { 337 "osc", "pll0_out" 338 }; 339 340 static const char *gpu_root_parents[] = { 341 "pll2_out", "pll1_out", 342 }; 343 344 static const char *bus_root_parents[] = { 345 "osc", "pll2_out", 346 }; 347 348 static const char *mclk_parents[] = { 349 "mclk_inner", "mclk_ext" 350 }; 351 352 static const char *ddr_bus_parents[] = { 353 "osc_div2", "pll1_div2", "pll1_div4", "pll1_div8" 354 }; 355 356 static const char *qspi_ref_parents[] = { 357 "osc", "qspi_ref_src", 358 }; 359 360 static const char *isp_2x_parents[] = { 361 "pll2_out", "pll1_out" 362 }; 363 364 static const char *i2stx0_lrck_parents[] = { 365 "i2stx0_lrck_mst", "i2stx_lrck_ext", 366 }; 367 368 static const char *i2stx0_bclk_parents[] = { 369 "i2stx0_bclk_mst", "i2stx_bclk_ext", 370 }; 371 372 static const char *i2stx1_bclk_parents[] = { 373 "i2stx1_bclk_mst", "i2stx_bclk_ext", 374 }; 375 376 static const char *gmac1_rx_parents[] = { 377 "gmac1_rgmii_rxin", "gmac1_rmii_rtx", 378 }; 379 380 static const char *i2srx_bclk_root_parents[] = { 381 "i2srx_bclk_mst", "i2srx_bclk_ext", 382 }; 383 384 static const char *i2srx_lrck_parents[] = { 385 "i2srx_lrck_mst", "i2srx_lrck_ext", 386 }; 387 388 static const char *tdm_tdm_parents[] = { 389 "tdm_internal", "tdm_ext", 390 }; 391 392 static const char *i2stx1_lrck_parents[] = { 393 "i2stx1_lrck_mst", "i2stx_lrck_ext", 394 }; 395 396 static const char *i2stx1_lrck_mst_parents[] = { 397 "i2stx1_bclk_mst_inv", "i2stx1_bclk_mst", 398 }; 399 400 static const char *gmac1_tx_parents[] = { 401 "gmac1_gtxclk", "gmac1_rmii_rtx", 402 }; 403 404 static const char *perh_root_parents[] = { 405 "pll0_out", "pll2_out", 406 }; 407 408 static const char *i2stx0_lrck_mst_parents[] = { 409 "i2stx0_bclk_mst_inv", "i2stx0_bclk_mst" 410 }; 411 412 static const char *i2srx_lrck_mst_parents[] = { 413 "i2srx_bclk_mst_inv", "i2srx_bclk_mst", 414 }; 415 416 static struct jh71x0_clkc_clk jh7110_sysclk_clocks[] = { 417 JH71X0CLKC_FIXED_FACTOR(JH7110_SYSCLK_PLL0_OUT, "pll0_out", "osc", 3, 125), 418 JH71X0CLKC_FIXED_FACTOR(JH7110_SYSCLK_PLL1_OUT, "pll1_out", "osc", 12, 533), 419 JH71X0CLKC_FIXED_FACTOR(JH7110_SYSCLK_PLL2_OUT, "pll2_out", "osc", 2, 99), 420 421 JH71X0CLKC_MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", cpu_root_parents), 422 JH71X0CLKC_MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", gpu_root_parents), 423 JH71X0CLKC_MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", bus_root_parents), 424 425 JH71X0CLKC_DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, "cpu_root"), 426 JH71X0CLKC_DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, "cpu_core"), 427 428 JH71X0CLKC_MUXDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, perh_root_parents), 429 430 JH71X0CLKC_DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, "bus_root"), 431 JH71X0CLKC_DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, "bus_root"), 432 JH71X0CLKC_DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, "axi_cfg0"), 433 JH71X0CLKC_GATE(JH7110_SYSCLK_AHB0, "ahb0", "stg_axiahb"), // CLK_IS_CRITICAL, 434 JH71X0CLKC_GATE(JH7110_SYSCLK_AHB1, "ahb1", "stg_axiahb"),// CLK_IS_CRITICAL, 435 JH71X0CLKC_DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, "stg_axiahb"), 436 JH71X0CLKC_GATE(JH7110_SYSCLK_APB0, "apb0", "apb_bus"),// CLK_IS_CRITICAL, 437 JH71X0CLKC_DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, "pll0_out"), 438 JH71X0CLKC_DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, "pll1_out"), 439 JH71X0CLKC_DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, "pll2_out"), 440 JH71X0CLKC_DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, "pll2_out"), 441 JH71X0CLKC_DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, "audio_root"), 442 443 JH71X0CLKC_MUX(JH7110_SYSCLK_MCLK, "mclk", mclk_parents), 444 445 JH71X0CLKC_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", "mclk_inner"), 446 447 JH71X0CLKC_MUXDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, isp_2x_parents), 448 449 JH71X0CLKC_DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, "isp_2x"), 450 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GCLK0, "gclk0", 62, "pll0_div2"), 451 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GCLK1, "gclk1",62, "pll1_div2"), 452 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GCLK2, "gclk2",62, "pll2_div2"), 453 /* cores */ 454 JH71X0CLKC_GATE(JH7110_SYSCLK_CORE, "core", "cpu_core"),// CLK_IS_CRITICAL, 455 JH71X0CLKC_GATE(JH7110_SYSCLK_CORE1, "core1", "cpu_core"),// CLK_IS_CRITICAL, 456 JH71X0CLKC_GATE(JH7110_SYSCLK_CORE2, "core2", "cpu_core"),// CLK_IS_CRITICAL, 457 JH71X0CLKC_GATE(JH7110_SYSCLK_CORE3, "core3", "cpu_core"),// CLK_IS_CRITICAL, 458 JH71X0CLKC_GATE(JH7110_SYSCLK_CORE4, "core4", "cpu_core"),// CLK_IS_CRITICAL, 459 JH71X0CLKC_GATE(JH7110_SYSCLK_DEBUG, "debug", "cpu_bus"), 460 JH71X0CLKC_DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, "osc"), 461 JH71X0CLKC_GATE(JH7110_SYSCLK_TRACE0, "trace0", "cpu_core"), 462 JH71X0CLKC_GATE(JH7110_SYSCLK_TRACE1, "trace1", "cpu_core"), 463 JH71X0CLKC_GATE(JH7110_SYSCLK_TRACE2, "trace2", "cpu_core"), 464 JH71X0CLKC_GATE(JH7110_SYSCLK_TRACE3, "trace3", "cpu_core"), 465 JH71X0CLKC_GATE(JH7110_SYSCLK_TRACE4, "trace4", "cpu_core"), 466 JH71X0CLKC_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", "cpu_bus"), 467 /* noc */ 468 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", "cpu_bus"), // CLK_IS_CRITICAL, 469 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", "axi_cfg0"),// CLK_IS_CRITICAL, 470 /* ddr */ 471 JH71X0CLKC_DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, "osc"), 472 JH71X0CLKC_DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, "pll1_div2"), 473 JH71X0CLKC_DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, "pll1_div4"), 474 JH71X0CLKC_MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", ddr_bus_parents), 475 476 JH71X0CLKC_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", "ddr_bus"),// CLK_IS_CRITICAL, 477 /* gpu */ 478 JH71X0CLKC_DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, "gpu_root"), 479 JH71X0CLKC_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", "gpu_core"), 480 JH71X0CLKC_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", "isp_axi"), 481 JH71X0CLKC_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", "apb_bus"), 482 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 12, "osc"), 483 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", "gpu_core"), 484 /* isp */ 485 JH71X0CLKC_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", "isp_2x"), 486 JH71X0CLKC_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", "isp_axi"), 487 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", "isp_axi"), // CLK_IS_CRITICAL, 488 /* hifi4 */ 489 JH71X0CLKC_DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, "bus_root"), 490 JH71X0CLKC_DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, "hifi4_core"), 491 /* axi_cfg1 */ 492 JH71X0CLKC_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", "isp_axi"), // CLK_IS_CRITICAL 493 JH71X0CLKC_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", "ahb0"), // CLK_IS_CRITICAL 494 /* vout */ 495 JH71X0CLKC_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", "pll2_out"), 496 JH71X0CLKC_DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, "pll2_out"), 497 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", "vout_axi"), 498 JH71X0CLKC_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", "ahb1"), 499 JH71X0CLKC_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", "vout_axi"), 500 JH71X0CLKC_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", "mclk_out"), 501 JH71X0CLKC_DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2, "osc"), 502 /* jpegc */ 503 JH71X0CLKC_DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, "pll2_out"), 504 JH71X0CLKC_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", "jpegc_axi"), 505 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core",16, "pll2_out"), 506 JH71X0CLKC_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", "apb_bus"), 507 /* vdec */ 508 JH71X0CLKC_DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, "bus_root"), 509 JH71X0CLKC_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", "vdec_axi"), 510 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu",7, "bus_root"), 511 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 7, "pll0_out"), 512 JH71X0CLKC_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", "apb_bus"), 513 JH71X0CLKC_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", "jpegc_axi"), 514 JH71X0CLKC_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", "vdec_axi"), 515 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", "vdec_axi"), 516 /* venc */ 517 JH71X0CLKC_DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, "pll2_out"), 518 JH71X0CLKC_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", "venc_axi"), 519 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu",15, "pll2_out"), 520 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce",15, "pll2_out"), 521 JH71X0CLKC_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", "apb_bus"), 522 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", "venc_axi"), 523 /* axi_cfg0 */ 524 JH71X0CLKC_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", "ahb1"), // CLK_IS_CRITICAL 525 JH71X0CLKC_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", "axi_cfg0"), // CLK_IS_CRITICAL 526 JH71X0CLKC_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", "hifi4_axi"), // CLK_IS_CRITICAL, 527 /* intmem */ 528 JH71X0CLKC_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", "axi_cfg0"), 529 /* qspi */ 530 JH71X0CLKC_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", "ahb1"), 531 JH71X0CLKC_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", "apb_bus"), 532 JH71X0CLKC_DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, "pll0_out"), 533 JH71X0CLKC_MUXGATE(JH7110_SYSCLK_QSPI_REF, "qspi_ref", qspi_ref_parents), 534 535 /* sdio */ 536 JH71X0CLKC_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", "ahb0"), 537 JH71X0CLKC_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", "ahb0"), 538 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", 15, "axi_cfg0"), 539 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", 15, "axi_cfg0"), 540 /* stg */ 541 JH71X0CLKC_DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, "pll0_out"), 542 JH71X0CLKC_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", "nocstg_bus"), // CLK_IS_CRITICAL, 543 /* gmac1 */ 544 JH71X0CLKC_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", "ahb0"), 545 JH71X0CLKC_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", "stg_axiahb"), 546 JH71X0CLKC_DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, "pll0_out"), 547 JH71X0CLKC_DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, "pll0_out"), 548 JH71X0CLKC_DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30, "gmac1_rmii_refin"), 549 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp",31, "gmac_src"), 550 JH71X0CLKC_MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", gmac1_rx_parents), 551 552 JH71X0CLKC_INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", "gmac1_rx"), 553 JH71X0CLKC_MUXGATE_FLAGS(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx", gmac1_tx_parents, CLK_SET_RATE_PARENT), // CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 554 JH71X0CLKC_INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", "gmac1_tx"), 555 JH71X0CLKC_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", "gmac1_gtxclk"), 556 /* gmac0 */ 557 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk",15, "pll0_out"), 558 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp",31, "gmac_src"), 559 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy",31, "gmac_src"), 560 JH71X0CLKC_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", "gmac0_gtxclk"), 561 /* apb misc */ 562 JH71X0CLKC_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", "apb_bus"), 563 JH71X0CLKC_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", "apb_bus"), 564 JH71X0CLKC_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", "apb_bus"), 565 /* can0 */ 566 JH71X0CLKC_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", "apb_bus"), 567 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer",24, "osc"), 568 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can",63, "perh_root"), 569 /* can1 */ 570 JH71X0CLKC_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", "apb_bus"), 571 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer",24, "osc"), 572 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can",63, "perh_root"), 573 /* pwm */ 574 JH71X0CLKC_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", "apb_bus"), 575 /* wdt */ 576 JH71X0CLKC_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", "apb_bus"), 577 JH71X0CLKC_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", "osc"), 578 /* timer */ 579 JH71X0CLKC_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", "apb_bus"), 580 JH71X0CLKC_GATE(JH7110_SYSCLK_TIMER0, "timer0", "osc"), 581 JH71X0CLKC_GATE(JH7110_SYSCLK_TIMER1, "timer1", "osc"), 582 JH71X0CLKC_GATE(JH7110_SYSCLK_TIMER2, "timer2", "osc"), 583 JH71X0CLKC_GATE(JH7110_SYSCLK_TIMER3, "timer3", "osc"), 584 /* temp sensor */ 585 JH71X0CLKC_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", "apb_bus"), 586 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core",24, "osc"), 587 /* spi */ 588 JH71X0CLKC_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", "apb0"), 589 JH71X0CLKC_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", "apb0"), 590 JH71X0CLKC_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", "apb0"), 591 JH71X0CLKC_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", "apb_bus"), 592 JH71X0CLKC_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", "apb_bus"), 593 JH71X0CLKC_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", "apb_bus"), 594 JH71X0CLKC_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", "apb_bus"), 595 /* i2c */ 596 JH71X0CLKC_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", "apb0"), 597 JH71X0CLKC_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", "apb0"), 598 JH71X0CLKC_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", "apb0"), 599 JH71X0CLKC_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", "apb_bus"), 600 JH71X0CLKC_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", "apb_bus"), 601 JH71X0CLKC_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", "apb_bus"), 602 JH71X0CLKC_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", "apb_bus"), 603 /* uart */ 604 JH71X0CLKC_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", "apb0"), 605 JH71X0CLKC_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", "osc"), 606 JH71X0CLKC_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", "apb0"), 607 JH71X0CLKC_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", "osc"), 608 JH71X0CLKC_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", "apb0"), 609 JH71X0CLKC_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", "osc"), 610 JH71X0CLKC_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", "apb0"), 611 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core",10, "perh_root"), 612 JH71X0CLKC_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", "apb0"), 613 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core",10, "perh_root"), 614 JH71X0CLKC_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", "apb0"), 615 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core",10, "perh_root"), 616 /* pwmdac */ 617 JH71X0CLKC_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", "apb0"), 618 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core",256, "audio_root"), 619 /* spdif */ 620 JH71X0CLKC_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", "apb0"), 621 JH71X0CLKC_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", "mclk_out"), 622 /* i2stx0 */ 623 JH71X0CLKC_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", "apb0"), 624 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst",32, "mclk_out"), 625 JH71X0CLKC_INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv", "i2stx0_bclk_mst"), 626 627 JH71X0CLKC_MUXDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, i2stx0_lrck_mst_parents), 628 629 JH71X0CLKC_MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", i2stx0_bclk_parents), 630 JH71X0CLKC_INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", "i2stx0_bclk"), 631 JH71X0CLKC_MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", i2stx0_lrck_parents), 632 /* i2stx1 */ 633 JH71X0CLKC_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", "apb0"), 634 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst",32, "mclk_out"), 635 JH71X0CLKC_INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv", "i2stx1_bclk_mst"), 636 637 JH71X0CLKC_MUXDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, i2stx1_lrck_mst_parents), 638 639 JH71X0CLKC_MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", i2stx1_bclk_parents), 640 JH71X0CLKC_INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", "i2stx1_bclk"), 641 JH71X0CLKC_MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", i2stx1_lrck_parents), 642 /* i2srx */ 643 JH71X0CLKC_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", "apb0"), 644 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 32, "mclk_out"), 645 JH71X0CLKC_INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv", "i2srx_bclk_mst"), 646 647 JH71X0CLKC_MUXDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, i2srx_lrck_mst_parents), 648 649 JH71X0CLKC_MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", i2srx_bclk_root_parents), 650 JH71X0CLKC_INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", "i2srx_bclk"), 651 JH71X0CLKC_MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", i2srx_lrck_parents), 652 /* pdm */ 653 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic",64, "mclk_out"), 654 JH71X0CLKC_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", "apb0"), 655 /* tdm */ 656 JH71X0CLKC_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", "ahb0"), 657 JH71X0CLKC_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", "apb0"), 658 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal",64, "mclk_out"), 659 JH71X0CLKC_MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", tdm_tdm_parents), 660 JH71X0CLKC_INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", "tdm_tdm"), 661 /* jtag */ 662 JH71X0CLKC_DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4, "osc"), 663 }; 664 665 static const char *apb_func_parents[] = { 666 "osc_div4", "osc", 667 }; 668 669 static const char *gmac0_tx_parents[] = { 670 "gmac0_gtxclk", "gmac0_rmii_rtx" 671 }; 672 673 static const char *gmac0_rx_parents[] = { 674 "gmac0_rgmii_rxin", "gmac0_rmii_rtx", 675 }; 676 677 static const char *rtc_32k_parents[] = { 678 "rtc_osc", "rtc_internal", 679 }; 680 681 static struct jh71x0_clkc_clk jh7110_aonclk_clocks[] = { 682 /* source */ 683 JH71X0CLKC_DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, "osc"), 684 JH71X0CLKC_MUX(JH7110_AONCLK_APB_FUNC, "apb_func", apb_func_parents), 685 /* gmac0 */ 686 JH71X0CLKC_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", "stg_axiahb"), 687 JH71X0CLKC_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", "stg_axiahb"), 688 JH71X0CLKC_DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30, "gmac0_rmii_refin"), 689 JH71X0CLKC_MUXGATE(JH7110_AONCLK_GMAC0_TX, "gmac0_tx",gmac0_tx_parents), 690 JH71X0CLKC_INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", "gmac0_tx"), 691 JH71X0CLKC_MUX_FLAGS(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", gmac0_rx_parents, CLK_SET_RATE_PARENT), // CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT 692 JH71X0CLKC_INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", "gmac0_rx"), 693 /* otpc */ 694 JH71X0CLKC_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", "apb_bus"), 695 /* rtc */ 696 JH71X0CLKC_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", "apb_bus"), 697 JH71X0CLKC_DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, "osc"), 698 JH71X0CLKC_MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", rtc_32k_parents), 699 JH71X0CLKC_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", "osc"), 700 }; 701 702 703 static struct jh71x0_clkc_clk jh7110_stgclk_clocks[] = { 704 /* hifi4 */ 705 JH71X0CLKC_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", "hifi4_core"), 706 /* usb */ 707 JH71X0CLKC_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", "apb_bus"), 708 JH71X0CLKC_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", "apb_bus"), 709 JH71X0CLKC_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", "stg_axiahb"), 710 JH71X0CLKC_GATEDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 2, "osc"), 711 JH71X0CLKC_GATEDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 4, "osc"), 712 JH71X0CLKC_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", "usb_125m"), 713 JH71X0CLKC_DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, "osc"), 714 /* pci-e */ 715 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", "stg_axiahb"), 716 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", "apb_bus"), 717 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", "stg_axiahb"), 718 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", "stg_axiahb"), 719 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", "apb_bus"), 720 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", "stg_axiahb"), 721 JH71X0CLKC_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", "stg_axiahb"), // CLK_IS_CRITICAL 722 /* security */ 723 JH71X0CLKC_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", "stg_axiahb"), 724 JH71X0CLKC_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", "stg_axiahb"), 725 /* stg mtrx */ 726 JH71X0CLKC_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", "cpu_bus"), // CLK_IS_CRITICAL 727 JH71X0CLKC_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", "nocstg_bus"), // CLK_IS_CRITICAL 728 JH71X0CLKC_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", "stg_axiahb"), // CLK_IS_CRITICAL 729 JH71X0CLKC_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", "cpu_bus"), // CLK_IS_CRITICAL 730 JH71X0CLKC_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", "nocstg_bus"), // CLK_IS_CRITICAL 731 JH71X0CLKC_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", "stg_axiahb"), // CLK_IS_CRITICAL 732 JH71X0CLKC_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", "hifi4_axi"), // CLK_IS_CRITICAL 733 /* e24_rvpi */ 734 JH71X0CLKC_GATEDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 24, "osc"), 735 JH71X0CLKC_GATE(JH7110_STGCLK_E2_CORE, "e2_core", "stg_axiahb"), 736 JH71X0CLKC_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", "stg_axiahb"), 737 /* dw_sgdma1p */ 738 JH71X0CLKC_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", "stg_axiahb"), 739 JH71X0CLKC_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", "stg_axiahb"), 740 }; 741 742 static const char *vin_p_axi_wr_parents[] = { 743 "mipi_rx0_pxl", "dvp_inv", 744 }; 745 746 static const char *ispv2_top_wrapper_c_parents[] = { 747 "mipi_rx0_pxl", "dvp_inv", 748 }; 749 750 static struct jh71x0_clkc_clk jh7110_ispclk_clocks[] = { 751 /* syscon */ 752 JH71X0CLKC_DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15, "isp_top_axi"), 753 JH71X0CLKC_DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8, "isp_top_core"), 754 JH71X0CLKC_INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", "dvp_clk"), 755 /* vin */ 756 JH71X0CLKC_DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16, "isp_top_core"), 757 JH71X0CLKC_DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16, "isp_top_core"), 758 JH71X0CLKC_DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60, "isp_top_core"), 759 JH71X0CLKC_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", "dom4_apb_func"), 760 JH71X0CLKC_DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, "isp_top_core"), 761 JH71X0CLKC_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", "mipi_rx0_pxl"), 762 JH71X0CLKC_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", "mipi_rx0_pxl"), 763 JH71X0CLKC_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", "mipi_rx0_pxl"), 764 JH71X0CLKC_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", "mipi_rx0_pxl"), 765 JH71X0CLKC_MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", vin_p_axi_wr_parents), 766 /* ispv2_top_wrapper */ 767 JH71X0CLKC_MUXGATE(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", ispv2_top_wrapper_c_parents), 768 }; 769 770 static const char *dc8200_pix0_parents[] = { 771 "dc8200_pix", "hdmitx0_pixelclk", 772 }; 773 774 static const char *dc8200_pix1_parents[] = { 775 "dc8200_pix", "hdmitx0_pixelclk", 776 }; 777 778 static const char *dsiTx_dpi_parents[] = { 779 "dc8200_pix", "hdmitx0_pixelclk", 780 }; 781 782 static const char *dom_vout_top_lcd_parents[] = { 783 "dc8200_pix0", "dc8200_pix1", 784 }; 785 786 static struct jh71x0_clkc_clk jh7110_voutclk_clocks[] = { 787 /* divider */ 788 JH71X0CLKC_DIV(JH7110_VOUTCLK_APB, "apb", 8, "vout_top_ahb"), 789 JH71X0CLKC_DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, "vout_src"), 790 JH71X0CLKC_DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, "vout_src"), 791 JH71X0CLKC_DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, "vout_top_ahb"), 792 /* dc8200 */ 793 JH71X0CLKC_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", "vout_top_axi"), 794 JH71X0CLKC_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", "vout_top_axi"), 795 JH71X0CLKC_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", "vout_top_ahb"), 796 JH71X0CLKC_MUXGATE(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", dc8200_pix0_parents), 797 JH71X0CLKC_MUXGATE(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", dc8200_pix1_parents), 798 /* LCD */ 799 JH71X0CLKC_MUXGATE(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", dom_vout_top_lcd_parents), 800 /* dsiTx */ 801 JH71X0CLKC_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", "dsi_sys"), 802 JH71X0CLKC_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", "dsi_sys"), 803 JH71X0CLKC_MUXGATE(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", dsiTx_dpi_parents), 804 JH71X0CLKC_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", "tx_esc"), 805 /* mipitx DPHY */ 806 JH71X0CLKC_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", "tx_esc"), 807 /* hdmi */ 808 JH71X0CLKC_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", "vout_top_hdmitx0_mclk"), 809 JH71X0CLKC_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", "i2stx0_bclk"), 810 JH71X0CLKC_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", "apb"), 811 }; 812 813 struct jh7110_clock_config { 814 struct jh71x0_clkc_clk *jhcc_clocks; 815 size_t jhcc_nclks; 816 }; 817 818 static struct jh7110_clock_config jh7110_aonclk_config = { 819 .jhcc_clocks = jh7110_aonclk_clocks, 820 .jhcc_nclks = __arraycount(jh7110_aonclk_clocks), 821 }; 822 823 static struct jh7110_clock_config jh7110_ispclk_config = { 824 .jhcc_clocks = jh7110_ispclk_clocks, 825 .jhcc_nclks = __arraycount(jh7110_ispclk_clocks), 826 }; 827 828 static struct jh7110_clock_config jh7110_stgclk_config = { 829 .jhcc_clocks = jh7110_stgclk_clocks, 830 .jhcc_nclks = __arraycount(jh7110_stgclk_clocks), 831 }; 832 833 static struct jh7110_clock_config jh7110_sysclk_config = { 834 .jhcc_clocks = jh7110_sysclk_clocks, 835 .jhcc_nclks = __arraycount(jh7110_sysclk_clocks), 836 }; 837 838 static struct jh7110_clock_config jh7110_voutclk_config = { 839 .jhcc_clocks = jh7110_voutclk_clocks, 840 .jhcc_nclks = __arraycount(jh7110_voutclk_clocks), 841 }; 842 843 844 #define JH7110_SYSRST_ASSERT 0x2f8 845 #define JH7110_SYSRST_STATUS 0x308 846 #define JH7110_SYSRST_NRESETS 126 847 848 #define JH7110_AONRST_ASSERT 0x38 849 #define JH7110_AONRST_STATUS 0x3c 850 #define JH7110_AONRST_NRESETS 8 851 852 #define JH7110_STGRST_ASSERT 0x74 853 #define JH7110_STGRST_STATUS 0x78 854 #define JH7110_STGRST_NRESETS 23 855 856 #define JH7110_ISPRST_ASSERT 0x38 857 #define JH7110_ISPRST_STATUS 0x3c 858 #define JH7110_ISPRST_NRESETS 12 859 860 #define JH7110_VOUTRST_ASSERT 0x48 861 #define JH7110_VOUTRST_STATUS 0x4c 862 #define JH7110_VOUTRST_NRESETS 12 863 864 struct jh7110_reset_config { 865 size_t jhcr_nresets; 866 bus_size_t jhcr_assert; 867 bus_size_t jhcr_status; 868 }; 869 870 static struct jh7110_reset_config jh7110_sysrst_config = { 871 .jhcr_nresets = JH7110_SYSRST_NRESETS, 872 .jhcr_assert = JH7110_SYSRST_ASSERT, 873 .jhcr_status = JH7110_SYSRST_STATUS, 874 }; 875 876 static struct jh7110_reset_config jh7110_aonrst_config = { 877 .jhcr_nresets = JH7110_AONRST_NRESETS, 878 .jhcr_assert = JH7110_AONRST_ASSERT, 879 .jhcr_status = JH7110_AONRST_STATUS, 880 }; 881 882 static struct jh7110_reset_config jh7110_stgrst_config = { 883 .jhcr_nresets = JH7110_STGRST_NRESETS, 884 .jhcr_assert = JH7110_STGRST_ASSERT, 885 .jhcr_status = JH7110_STGRST_STATUS, 886 }; 887 888 static struct jh7110_reset_config jh7110_isprst_config = { 889 .jhcr_nresets = JH7110_ISPRST_NRESETS, 890 .jhcr_assert = JH7110_ISPRST_ASSERT, 891 .jhcr_status = JH7110_ISPRST_STATUS, 892 }; 893 894 static struct jh7110_reset_config jh7110_voutrst_config = { 895 .jhcr_nresets = JH7110_VOUTRST_NRESETS, 896 .jhcr_assert = JH7110_VOUTRST_ASSERT, 897 .jhcr_status = JH7110_VOUTRST_STATUS, 898 }; 899 900 struct jh7110_crg { 901 const char *jhc_name; 902 struct jh7110_clock_config *jhc_clk; 903 struct jh7110_reset_config *jhc_rst; 904 bool jhc_debug; 905 }; 906 907 908 static struct jh7110_crg jh7110_sys_config = { 909 .jhc_name = "System", 910 .jhc_clk = &jh7110_sysclk_config, 911 .jhc_rst = &jh7110_sysrst_config, 912 .jhc_debug = true, 913 }; 914 915 916 static struct jh7110_crg jh7110_aon_config = { 917 .jhc_name = "Always-On", 918 .jhc_clk = &jh7110_aonclk_config, 919 .jhc_rst = &jh7110_aonrst_config, 920 .jhc_debug = true, 921 }; 922 923 static struct jh7110_crg jh7110_isp_config = { 924 .jhc_name = "Image-Signal-Process", 925 .jhc_clk = &jh7110_ispclk_config, 926 .jhc_rst = &jh7110_isprst_config, 927 }; 928 929 static struct jh7110_crg jh7110_stg_config = { 930 .jhc_name = "System-Top-Group", 931 .jhc_clk = &jh7110_stgclk_config, 932 .jhc_rst = &jh7110_stgrst_config, 933 }; 934 935 static struct jh7110_crg jh7110_vout_config = { 936 .jhc_name = "Video Output", 937 .jhc_clk = &jh7110_voutclk_config, 938 .jhc_rst = &jh7110_voutrst_config, 939 }; 940 941 942 static const struct device_compatible_entry compat_data[] = { 943 { .compat = "starfive,jh7110-syscrg", .data = &jh7110_sys_config }, 944 { .compat = "starfive,jh7110-aoncrg", .data = &jh7110_aon_config }, 945 { .compat = "starfive,jh7110-ispcrg", .data = &jh7110_isp_config }, 946 { .compat = "starfive,jh7110-stgcrg", .data = &jh7110_stg_config }, 947 { .compat = "starfive,jh7110-voutcrg", .data = &jh7110_vout_config }, 948 DEVICE_COMPAT_EOL 949 }; 950 951 #define CLK_LOCK(sc) \ 952 mutex_enter(&sc->sc_lock); 953 #define CLK_UNLOCK(sc) \ 954 mutex_exit(&sc->sc_lock); 955 956 #define RD4(sc, reg) \ 957 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg)) 958 #define WR4(sc, reg, val) \ 959 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val)) 960 961 #define JH7110_RESET_RETRIES 1000 962 963 static void * 964 jh7110_clkc_reset_acquire(device_t dev, const void *data, size_t len) 965 { 966 struct jh71x0_clkc_softc * const sc = device_private(dev); 967 968 if (len != sizeof(uint32_t)) 969 return NULL; 970 971 const uint32_t reset_id = be32dec(data); 972 if (reset_id >= sc->sc_nrsts) 973 return NULL; 974 975 uint32_t *reset = kmem_alloc(sizeof(uint32_t), KM_SLEEP); 976 *reset = reset_id; 977 978 return reset; 979 } 980 981 static void 982 jh7110_clkc_reset_release(device_t dev, void *priv) 983 { 984 985 kmem_free(priv, sizeof(uint32_t)); 986 } 987 988 static int 989 jh7110_clkc_reset_set(struct jh71x0_clkc_softc *sc, unsigned reset_id, 990 bool assert) 991 { 992 const uint32_t off = (reset_id / 32) * sizeof(uint32_t); 993 const uint32_t bit = reset_id % 32; 994 const bus_size_t assert_reg = sc->sc_reset_assert + off; 995 const bus_size_t status_reg = sc->sc_reset_status + off; 996 997 CLK_LOCK(sc); 998 999 const uint32_t val = RD4(sc, assert_reg); 1000 if (assert) 1001 WR4(sc, assert_reg, val | __BIT(bit)); 1002 else 1003 WR4(sc, assert_reg, val & ~__BIT(bit)); 1004 1005 unsigned i; 1006 uint32_t status; 1007 for (i = 0; i < JH7110_RESET_RETRIES; i++) { 1008 status = RD4(sc, status_reg); 1009 bool asserted = (status & __BIT(bit)) == 0; 1010 if (asserted == assert) 1011 break; 1012 } 1013 CLK_UNLOCK(sc); 1014 1015 if (i >= JH7110_RESET_RETRIES) { 1016 printf("%s: reset %3d status %#010x / %2d didn't %sassert\n", 1017 __func__, reset_id, status, bit, assert ? "" : "de"); 1018 return ETIMEDOUT; 1019 } 1020 1021 return 0; 1022 } 1023 1024 static int 1025 jh7110_clkc_reset_assert(device_t dev, void *priv) 1026 { 1027 struct jh71x0_clkc_softc * const sc = device_private(dev); 1028 const uint32_t *reset = priv; 1029 const uint32_t reset_id = *reset; 1030 1031 return jh7110_clkc_reset_set(sc, reset_id, true); 1032 } 1033 1034 static int 1035 jh7110_clkc_reset_deassert(device_t dev, void *priv) 1036 { 1037 struct jh71x0_clkc_softc * const sc = device_private(dev); 1038 const uint32_t *reset = priv; 1039 const uint32_t reset_id = *reset; 1040 1041 return jh7110_clkc_reset_set(sc, reset_id, false); 1042 } 1043 1044 1045 static const struct fdtbus_reset_controller_func jh7110_clkc_fdtreset_funcs = { 1046 .acquire = jh7110_clkc_reset_acquire, 1047 .release = jh7110_clkc_reset_release, 1048 .reset_assert = jh7110_clkc_reset_assert, 1049 .reset_deassert = jh7110_clkc_reset_deassert, 1050 }; 1051 1052 1053 static struct clk * 1054 jh7110_clkc_clock_decode(device_t dev, int phandle, const void *data, 1055 size_t len) 1056 { 1057 struct jh71x0_clkc_softc * const sc = device_private(dev); 1058 1059 if (len != sizeof(uint32_t)) 1060 return NULL; 1061 1062 u_int id = be32dec(data); 1063 if (id >= sc->sc_nclks) { 1064 return NULL; 1065 } 1066 if (sc->sc_clk[id].jcc_type == JH71X0CLK_UNKNOWN) { 1067 printf("Unknown clock %d\n", id); 1068 return NULL; 1069 } 1070 return &sc->sc_clk[id].jcc_clk; 1071 } 1072 1073 static const struct fdtbus_clock_controller_func jh7110_clkc_fdtclock_funcs = { 1074 .decode = jh7110_clkc_clock_decode 1075 }; 1076 1077 static int 1078 jh7110_clkc_match(device_t parent, cfdata_t cf, void *aux) 1079 { 1080 struct fdt_attach_args * const faa = aux; 1081 1082 return of_compatible_match(faa->faa_phandle, compat_data); 1083 } 1084 1085 static void 1086 jh7110_clkc_attach(device_t parent, device_t self, void *aux) 1087 { 1088 struct jh71x0_clkc_softc * const sc = device_private(self); 1089 struct fdt_attach_args * const faa = aux; 1090 const int phandle = faa->faa_phandle; 1091 bus_addr_t addr; 1092 bus_size_t size; 1093 1094 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 1095 aprint_error(": couldn't get registers\n"); 1096 return; 1097 } 1098 1099 sc->sc_dev = self; 1100 sc->sc_phandle = phandle; 1101 sc->sc_bst = faa->faa_bst; 1102 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 1103 aprint_error(": couldn't map registers\n"); 1104 return; 1105 } 1106 1107 sc->sc_clkdom.name = device_xname(self); 1108 sc->sc_clkdom.funcs = &jh71x0_clkc_funcs; 1109 sc->sc_clkdom.priv = sc; 1110 1111 const struct jh7110_crg *jhc = 1112 of_compatible_lookup(phandle, compat_data)->data; 1113 KASSERT(jhc != NULL); 1114 1115 struct jh7110_clock_config * const jhcc = jhc->jhc_clk; 1116 struct jh7110_reset_config * const jhcr = jhc->jhc_rst; 1117 sc->sc_clk = jhcc->jhcc_clocks; 1118 sc->sc_nclks = jhcc->jhcc_nclks; 1119 1120 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE); 1121 sc->sc_nrsts = jhcr->jhcr_nresets; 1122 sc->sc_reset_assert = jhcr->jhcr_assert; 1123 sc->sc_reset_status = jhcr->jhcr_status; 1124 1125 for (size_t id = 0; id < sc->sc_nclks; id++) { 1126 if (sc->sc_clk[id].jcc_type == JH71X0CLK_UNKNOWN) 1127 continue; 1128 1129 sc->sc_clk[id].jcc_clk.domain = &sc->sc_clkdom; 1130 // Names already populated. 1131 clk_attach(&sc->sc_clk[id].jcc_clk); 1132 } 1133 1134 aprint_naive("\n"); 1135 aprint_normal(": JH7110 %s Clock and Reset Generator\n", 1136 jhc->jhc_name); 1137 1138 if (jhc->jhc_debug) { 1139 for (size_t id = 0; id < sc->sc_nclks; id++) { 1140 if (sc->sc_clk[id].jcc_type == JH71X0CLK_UNKNOWN) 1141 continue; 1142 1143 struct clk * const clk = &sc->sc_clk[id].jcc_clk; 1144 1145 aprint_debug_dev(self, "id %zu [%s]: %u Hz\n", id, 1146 clk->name ? clk->name : "<none>", clk_get_rate(clk)); 1147 } 1148 } 1149 1150 fdtbus_register_clock_controller(self, phandle, &jh7110_clkc_fdtclock_funcs); 1151 fdtbus_register_reset_controller(self, phandle, &jh7110_clkc_fdtreset_funcs); 1152 } 1153 1154 CFATTACH_DECL_NEW(jh7110_clkc, sizeof(struct jh71x0_clkc_softc), 1155 jh7110_clkc_match, jh7110_clkc_attach, NULL, NULL); 1156
Indexes created Tue Sep 30 06:09:59 GMT 2025