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jh7110_pciephy.c revision 1.1 
      1 /* $NetBSD: jh7110_pciephy.c,v 1.1 2024/11/11 20:01:38 skrll Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2024 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Nick Hudson
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: jh7110_pciephy.c,v 1.1 2024/11/11 20:01:38 skrll Exp $");
     34 
     35 #include <sys/param.h>
     36 
     37 #include <dev/fdt/fdtvar.h>
     38 #include <dev/fdt/syscon.h>
     39 
     40 
     41 struct jh7110_pciephy_softc {
     42 	device_t		sc_dev;
     43 	bus_space_tag_t		sc_bst;
     44 	bus_space_handle_t	sc_bsh;
     45 	int			sc_phandle;
     46 #if 0
     47 	struct syscon *		sc_sys_syscon;
     48 	bus_size_t		sc_phy_connect;
     49 
     50 	struct syscon *		sc_stg_syscon;
     51 	bus_size_t		sc_stg_pcie_mode;
     52 	bus_size_t		sc_stg_pcie_usb;
     53 #endif
     54 };
     55 
     56 /* Register definitions */
     57 #define PCIE_KVCO_LEVEL			0x28
     58 #define  PCEI_PHY_KVCO_FINE_TUNE_LEVEL	0x91
     59 
     60 #define PCIE_USB3_PHY_PLL_CTL		0x7c
     61 
     62 #define PCIE_KVCO_TUNE_SIGNAL		0x80
     63 #define	 PCIE_KVO_FINE_TUNE_SIGNALS	0x0c
     64 
     65 #if 0
     66 
     67 #define USB_PDRSTN_SPLIT		__BIT(17)
     68 
     69 #define PCIE_PHY_MODE			__BIT(20)
     70 #define PCIE_PHY_MODE_MASK		__BITS(21, 20)
     71 #define PCIE_USB3_BUS_WIDTH_MASK	__BITS(3, 2)
     72 #define PCIE_USB3_PHY_ENABLE		__BIT(4)
     73 #define PCIE_USB3_BUS_WIDTH		__BIT(3)
     74 #endif
     75 
     76 #define RD4(sc, reg)							      \
     77 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
     78 #define WR4(sc, reg, val)						      \
     79 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
     80 
     81 static void *
     82 jh7110pciephy_acquire(device_t dev, const void *data, size_t len)
     83 {
     84 	struct jh7110_pciephy_softc * const sc = device_private(dev);
     85 
     86 	if (len != 0) {
     87 		aprint_verbose("phy acquire with len %zu", len);
     88 		return NULL;
     89 	}
     90 
     91 	return sc;
     92 }
     93 
     94 static void
     95 jh7110pciephy_release(device_t dev, void *data)
     96 {
     97 }
     98 
     99 static int
    100 jh7110pciephy_enable(device_t dev, void *priv, bool enable)
    101 {
    102 
    103 	return 0;
    104 }
    105 
    106 const struct fdtbus_phy_controller_func jh7110pciephy_funcs = {
    107 	.acquire = jh7110pciephy_acquire,
    108 	.release = jh7110pciephy_release,
    109 	.enable = jh7110pciephy_enable,
    110 };
    111 
    112 /* Compat string(s) */
    113 static const struct device_compatible_entry compat_data[] = {
    114 	{ .compat = "starfive,jh7110-pcie-phy" },
    115 	DEVICE_COMPAT_EOL
    116 };
    117 
    118 static int
    119 jh7110_pciephy_match(device_t parent, cfdata_t cf, void *aux)
    120 {
    121 	struct fdt_attach_args * const faa = aux;
    122 
    123 	return of_compatible_match(faa->faa_phandle, compat_data);
    124 }
    125 
    126 static void
    127 jh7110_pciephy_attach(device_t parent, device_t self, void *aux)
    128 {
    129 	struct jh7110_pciephy_softc *sc = device_private(self);
    130 	struct fdt_attach_args * const faa = aux;
    131 	const int phandle = faa->faa_phandle;
    132 	const bus_space_tag_t bst = faa->faa_bst;
    133 	bus_addr_t addr;
    134 	bus_size_t size;
    135 	int error;
    136 
    137 	error = fdtbus_get_reg(phandle, 0, &addr, &size);
    138 	if (error) {
    139 		aprint_error(": couldn't get registers\n");
    140 		return;
    141 	}
    142 	error = bus_space_map(bst, addr, size, 0, &sc->sc_bsh);
    143 	if (error) {
    144 		aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr,
    145 		    error);
    146 		return;
    147 	}
    148 
    149 	sc->sc_dev = self;
    150 	sc->sc_phandle = phandle;
    151 	sc->sc_bst = bst;
    152 
    153 	aprint_naive("\n");
    154 	aprint_normal(": JH7110 PCIe PHY\n");
    155 
    156 	WR4(sc, PCIE_KVCO_LEVEL, PCEI_PHY_KVCO_FINE_TUNE_LEVEL);
    157 	WR4(sc, PCIE_KVCO_TUNE_SIGNAL, PCIE_KVO_FINE_TUNE_SIGNALS);
    158 
    159         fdtbus_register_phy_controller(self, faa->faa_phandle,
    160 	    &jh7110pciephy_funcs);
    161 }
    162 
    163 CFATTACH_DECL_NEW(jh7110_pciephy, sizeof(struct jh7110_pciephy_softc),
    164 	jh7110_pciephy_match, jh7110_pciephy_attach, NULL, NULL);
    165