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      1 /* $NetBSD: jh7110_pciephy.c,v 1.3 2025/01/01 17:35:44 skrll Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2024 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Nick Hudson
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #include <sys/cdefs.h>
     33 __KERNEL_RCSID(0, "$NetBSD: jh7110_pciephy.c,v 1.3 2025/01/01 17:35:44 skrll Exp $");
     34 
     35 #include <sys/param.h>
     36 
     37 #include <dev/fdt/fdtvar.h>
     38 #include <dev/fdt/syscon.h>
     39 
     40 
     41 struct jh7110_pciephy_softc {
     42 	device_t		sc_dev;
     43 	bus_space_tag_t		sc_bst;
     44 	bus_space_handle_t	sc_bsh;
     45 	int			sc_phandle;
     46 };
     47 
     48 /* Register definitions */
     49 #define PCIE_KVCO_LEVEL			0x28
     50 #define  PCEI_PHY_KVCO_FINE_TUNE_LEVEL	0x91
     51 
     52 #define PCIE_USB3_PHY_PLL_CTL		0x7c
     53 
     54 #define PCIE_KVCO_TUNE_SIGNAL		0x80
     55 #define	 PCIE_KVO_FINE_TUNE_SIGNALS	0x0c
     56 
     57 #define RD4(sc, reg)							      \
     58 	bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
     59 #define WR4(sc, reg, val)						      \
     60 	bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
     61 
     62 static void *
     63 jh7110pciephy_acquire(device_t dev, const void *data, size_t len)
     64 {
     65 	struct jh7110_pciephy_softc * const sc = device_private(dev);
     66 
     67 	if (len != 0) {
     68 		aprint_verbose("phy acquire with len %zu", len);
     69 		return NULL;
     70 	}
     71 
     72 	return sc;
     73 }
     74 
     75 static void
     76 jh7110pciephy_release(device_t dev, void *data)
     77 {
     78 }
     79 
     80 static int
     81 jh7110pciephy_enable(device_t dev, void *priv, bool enable)
     82 {
     83 
     84 	return 0;
     85 }
     86 
     87 const struct fdtbus_phy_controller_func jh7110pciephy_funcs = {
     88 	.acquire = jh7110pciephy_acquire,
     89 	.release = jh7110pciephy_release,
     90 	.enable = jh7110pciephy_enable,
     91 };
     92 
     93 /* Compat string(s) */
     94 static const struct device_compatible_entry compat_data[] = {
     95 	{ .compat = "starfive,jh7110-pcie-phy" },
     96 	DEVICE_COMPAT_EOL
     97 };
     98 
     99 static int
    100 jh7110_pciephy_match(device_t parent, cfdata_t cf, void *aux)
    101 {
    102 	struct fdt_attach_args * const faa = aux;
    103 
    104 	return of_compatible_match(faa->faa_phandle, compat_data);
    105 }
    106 
    107 static void
    108 jh7110_pciephy_attach(device_t parent, device_t self, void *aux)
    109 {
    110 	struct jh7110_pciephy_softc *sc = device_private(self);
    111 	struct fdt_attach_args * const faa = aux;
    112 	const int phandle = faa->faa_phandle;
    113 	const bus_space_tag_t bst = faa->faa_bst;
    114 	bus_addr_t addr;
    115 	bus_size_t size;
    116 	int error;
    117 
    118 	error = fdtbus_get_reg(phandle, 0, &addr, &size);
    119 	if (error) {
    120 		aprint_error(": couldn't get registers\n");
    121 		return;
    122 	}
    123 	error = bus_space_map(bst, addr, size, 0, &sc->sc_bsh);
    124 	if (error) {
    125 		aprint_error(": couldn't map %#" PRIxBUSADDR ": %d", addr,
    126 		    error);
    127 		return;
    128 	}
    129 
    130 	sc->sc_dev = self;
    131 	sc->sc_phandle = phandle;
    132 	sc->sc_bst = bst;
    133 
    134 	aprint_naive("\n");
    135 	aprint_normal(": JH7110 PCIe PHY\n");
    136 
    137 	WR4(sc, PCIE_KVCO_LEVEL, PCEI_PHY_KVCO_FINE_TUNE_LEVEL);
    138 	WR4(sc, PCIE_KVCO_TUNE_SIGNAL, PCIE_KVO_FINE_TUNE_SIGNALS);
    139 
    140 	fdtbus_register_phy_controller(self, faa->faa_phandle,
    141 	    &jh7110pciephy_funcs);
    142 }
    143 
    144 CFATTACH_DECL_NEW(jh7110_pciephy, sizeof(struct jh7110_pciephy_softc),
    145 	jh7110_pciephy_match, jh7110_pciephy_attach, NULL, NULL);
    146