1 /* $NetBSD: sun20i_d1_gpio.c,v 1.1 2024/08/13 07:20:23 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2024 Rui-Xiang Guo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: sun20i_d1_gpio.c,v 1.1 2024/08/13 07:20:23 skrll Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/types.h> 37 38 #include <arm/sunxi/sunxi_gpio.h> 39 40 static const struct sunxi_gpio_pins d1_pins[] = { 41 {"PB0", 1, 0, {"gpio_in", "gpio_out", "pwm3", "ir", "i2c2", "spi1", "uart0", "uart2", "spdif", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 0}, 42 {"PB1", 1, 1, {"gpio_in", "gpio_out", "pwm4", "i2s2", "i2c2", "i2s2", "uart0", "uart2", "ir", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 1}, 43 {"PB2", 1, 2, {"gpio_in", "gpio_out", "lcd0", "i2s2", "i2c0", "i2s2", "lcd0", "uart4", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 2}, 44 {"PB3", 1, 3, {"gpio_in", "gpio_out", "lcd0", "i2s2", "i2c0", "i2s2", "lcd0", "uart4", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 3}, 45 {"PB4", 1, 4, {"gpio_in", "gpio_out", "lcd0", "i2s2", "i2c1", "i2s2", "lcd0", "uart5", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 4}, 46 {"PB5", 1, 5, {"gpio_in", "gpio_out", "lcd0", "i2s2", "i2c1", "pwm0", "lcd0", "uart5", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 5}, 47 {"PB6", 1, 6, {"gpio_in", "gpio_out", "lcd0", "i2s2", "i2c3", "pwm1", "lcd0", "uart3", "cpu", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 6}, 48 {"PB7", 1, 7, {"gpio_in", "gpio_out", "lcd0", "i2s2", "i2c3", "ir", "lcd0", "uart3", "cpu", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 7}, 49 {"PB8", 1, 8, {"gpio_in", "gpio_out", "dmic", "pwm5", "i2c2", "spi1", "uart0", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 8}, 50 {"PB9", 1, 9, {"gpio_in", "gpio_out", "dmic", "pwm6", "i2c2", "spi1", "uart0", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 9}, 51 {"PB10", 1, 10, {"gpio_in", "gpio_out", "dmic", "pwm7", "i2c0", "spi1", "clk", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 10}, 52 {"PB11", 1, 11, {"gpio_in", "gpio_out", "dmic", "pwm2", "i2c0", "spi1", "clk", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 11}, 53 {"PB12", 1, 12, {"gpio_in", "gpio_out", "dmic", "pwm0", "spdif", "spi1", "clk", "ir", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 12}, 54 55 {"PC0", 2, 0, {"gpio_in", "gpio_out", "uart2", "i2c2", "ledc", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 0}, 56 {"PC1", 2, 1, {"gpio_in", "gpio_out", "uart2", "i2c2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 1}, 57 {"PC2", 2, 2, {"gpio_in", "gpio_out", "spi0", "mmc2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 2}, 58 {"PC3", 2, 3, {"gpio_in", "gpio_out", "spi0", "mmc2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 3}, 59 {"PC4", 2, 4, {"gpio_in", "gpio_out", "spi0", "mmc2", "boot", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 4}, 60 {"PC5", 2, 5, {"gpio_in", "gpio_out", "spi0", "mmc2", "boot", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 5}, 61 {"PC6", 2, 6, {"gpio_in", "gpio_out", "spi0", "mmc2", "uart3", "i2c3", "dbg", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 6}, 62 {"PC7", 2, 7, {"gpio_in", "gpio_out", "spi0", "mmc2", "uart3", "i2c3", "tcon", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 7}, 63 64 {"PD0", 3, 0, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "i2c0", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 0}, 65 {"PD1", 3, 1, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 1}, 66 {"PD2", 3, 2, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 2}, 67 {"PD3", 3, 3, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 3}, 68 {"PD4", 3, 4, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 4}, 69 {"PD5", 3, 5, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart5", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 5}, 70 {"PD6", 3, 6, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart5", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 6}, 71 {"PD7", 3, 7, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart4", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 7}, 72 {"PD8", 3, 8, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "uart4", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 8}, 73 {"PD9", 3, 9, {"gpio_in", "gpio_out", "lcd0", "lvds0", "dsi", "pwm6", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 9}, 74 {"PD10", 3, 10, {"gpio_in", "gpio_out", "lcd0", "lvds1", "spi1", "uart3", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 10}, 75 {"PD11", 3, 11, {"gpio_in", "gpio_out", "lcd0", "lvds1", "spi1", "uart3", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 11}, 76 {"PD12", 3, 12, {"gpio_in", "gpio_out", "lcd0", "lvds1", "spi1", "i2c0", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 12}, 77 {"PD13", 3, 13, {"gpio_in", "gpio_out", "lcd0", "lvds1", "spi1", "uart3", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 13}, 78 {"PD14", 3, 14, {"gpio_in", "gpio_out", "lcd0", "lvds1", "spi1", "uart3", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 14}, 79 {"PD15", 3, 15, {"gpio_in", "gpio_out", "lcd0", "lvds1", "spi1", "ir", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 15}, 80 {"PD16", 3, 16, {"gpio_in", "gpio_out", "lcd0", "lvds1", "dmic", "pwm0", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 16}, 81 {"PD17", 3, 17, {"gpio_in", "gpio_out", "lcd0", "lvds1", "dmic", "pwm1", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 17}, 82 {"PD18", 3, 18, {"gpio_in", "gpio_out", "lcd0", "lvds1", "dmic", "pwm2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 18}, 83 {"PD19", 3, 19, {"gpio_in", "gpio_out", "lcd0", "lvds1", "dmic", "pwm3", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 19}, 84 {"PD20", 3, 20, {"gpio_in", "gpio_out", "lcd0", "i2c2", "dmic", "pwm4", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 20}, 85 {"PD21", 3, 21, {"gpio_in", "gpio_out", "lcd0", "i2c2", "uart1", "pwm5", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 21}, 86 {"PD22", 3, 22, {"gpio_in", "gpio_out", "spdif", "ir", "uart1", "pwm7", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 22}, 87 88 {"PE0", 4, 0, {"gpio_in", "gpio_out", "ncsi0", "uart2", "i2c1", "lcd0", NULL, NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 0}, 89 {"PE1", 4, 1, {"gpio_in", "gpio_out", "ncsi0", "uart2", "i2c1", "lcd0", NULL, NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 1}, 90 {"PE2", 4, 2, {"gpio_in", "gpio_out", "ncsi0", "uart2", "i2c0", "clk", "uart0", NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 2}, 91 {"PE3", 4, 3, {"gpio_in", "gpio_out", "ncsi0", "uart2", "i2c0", "clk", "uart0", NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 3}, 92 {"PE4", 4, 4, {"gpio_in", "gpio_out", "ncsi0", "uart4", "i2c2", "clk", "jtag", "jtag", "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 4}, 93 {"PE5", 4, 5, {"gpio_in", "gpio_out", "ncsi0", "uart4", "i2c2", "ledc", "jtag", "jtag", "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 5}, 94 {"PE6", 4, 6, {"gpio_in", "gpio_out", "ncsi0", "uart5", "i2c3", "spdif", "jtag", "jtag", "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 6}, 95 {"PE7", 4, 7, {"gpio_in", "gpio_out", "ncsi0", "uart5", "i2c3", "spdif", "jtag", "jtag", "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 7}, 96 {"PE8", 4, 8, {"gpio_in", "gpio_out", "ncsi0", "uart1", "pwm2", "uart3", NULL, NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 8}, 97 {"PE9", 4, 9, {"gpio_in", "gpio_out", "ncsi0", "uart1", "pwm3", "uart3", NULL, NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 9}, 98 {"PE10", 4, 10, {"gpio_in", "gpio_out", "ncsi0", "uart1", "pwm4", "ir", NULL, NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 10}, 99 {"PE11", 4, 11, {"gpio_in", "gpio_out", "ncsi0", "uart1", "i2s0", "i2s0", NULL, NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 11}, 100 {"PE12", 4, 12, {"gpio_in", "gpio_out", "i2c2", "ncsi0", "i2s0", "i2s0", NULL, NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 12}, 101 {"PE13", 4, 13, {"gpio_in", "gpio_out", "i2c2", "pwm5", "i2s0", "i2s0", "dmic", NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 13}, 102 {"PE14", 4, 14, {"gpio_in", "gpio_out", "i2c1", "jtag", "i2s0", "i2s0", "dmic", NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 14}, 103 {"PE15", 4, 15, {"gpio_in", "gpio_out", "i2c1", "jtag", "pwm6", "i2s0", "dmic", NULL, "emac", NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 15}, 104 {"PE16", 4, 16, {"gpio_in", "gpio_out", "i2c3", "jtag", "pwm7", "i2s0", "dmic", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 16}, 105 {"PE17", 4, 17, {"gpio_in", "gpio_out", "i2c3", "jtag", "ir", "i2s0", "dmic", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 17}, 106 107 {"PF0", 5, 0, {"gpio_in", "gpio_out", "mmc0", NULL, "jtag", "i2s2", "i2s2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 0}, 108 {"PF1", 5, 1, {"gpio_in", "gpio_out", "mmc0", NULL, "jtag", "i2s2", "i2s2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 1}, 109 {"PF2", 5, 2, {"gpio_in", "gpio_out", "mmc0", "uart0", "i2c0", "ledc", "spdif", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 2}, 110 {"PF3", 5, 3, {"gpio_in", "gpio_out", "mmc0", NULL, "jtag", "i2s2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 3}, 111 {"PF4", 5, 4, {"gpio_in", "gpio_out", "mmc0", "uart0", "i2c0", "pwm6", "ir", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 4}, 112 {"PF5", 5, 5, {"gpio_in", "gpio_out", "mmc0", NULL, "jtag", "i2s2", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 5}, 113 {"PF6", 5, 6, {"gpio_in", "gpio_out", NULL, "spdif", "ir", "i2s2", "pwm5", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 6}, 114 115 {"PG0", 6, 0, {"gpio_in", "gpio_out", "mmc1", "uart3", "emac", "pwm7", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 0}, 116 {"PG1", 6, 1, {"gpio_in", "gpio_out", "mmc1", "uart3", "emac", "pwm6", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 1}, 117 {"PG2", 6, 2, {"gpio_in", "gpio_out", "mmc1", "uart3", "emac", "uart4", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 2}, 118 {"PG3", 6, 3, {"gpio_in", "gpio_out", "mmc1", "uart3", "emac", "uart4", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 3}, 119 {"PG4", 6, 4, {"gpio_in", "gpio_out", "mmc1", "uart5", "emac", "pwm5", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 4}, 120 {"PG5", 6, 5, {"gpio_in", "gpio_out", "mmc1", "uart5", "emac", "pwm4", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 5}, 121 {"PG6", 6, 6, {"gpio_in", "gpio_out", "uart1", "i2c2", "emac", "pwm1", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 6}, 122 {"PG7", 6, 7, {"gpio_in", "gpio_out", "uart1", "i2c2", "emac", "spdif", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 7}, 123 {"PG8", 6, 8, {"gpio_in", "gpio_out", "uart1", "i2c1", "emac", "uart3", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 8}, 124 {"PG9", 6, 9, {"gpio_in", "gpio_out", "uart1", "i2c1", "emac", "uart3", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 9}, 125 {"PG10", 6, 10, {"gpio_in", "gpio_out", "pwm3", "i2c3", "emac", "clk", "ir", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 10}, 126 {"PG11", 6, 11, {"gpio_in", "gpio_out", "i2s1", "i2c3", "emac", "clk", "tcon", NULL, NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 11}, 127 {"PG12", 6, 12, {"gpio_in", "gpio_out", "i2s1", "i2c0", "emac", "clk", "pwm0", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 12}, 128 {"PG13", 6, 13, {"gpio_in", "gpio_out", "i2s1", "i2c0", "emac", "pwm2", "ledc", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 13}, 129 {"PG14", 6, 14, {"gpio_in", "gpio_out", "i2s1", "i2c2", "emac", "i2s1", "spi0", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 14}, 130 {"PG15", 6, 15, {"gpio_in", "gpio_out", "i2s1", "i2c2", "emac", "i2s1", "spi0", "uart1", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 15}, 131 {"PG16", 6, 16, {"gpio_in", "gpio_out", "ir", "tcon", "pwm5", "clk", "spdif", "ledc", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 16}, 132 {"PG17", 6, 17, {"gpio_in", "gpio_out", "uart2", "i2c3", "pwm7", "clk", "ir", "uart0", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 17}, 133 {"PG18", 6, 18, {"gpio_in", "gpio_out", "uart2", "i2c3", "pwm6", "clk", "spdif", "uart0", NULL, NULL, NULL, NULL, NULL, NULL, "irq"}, 14, 18}, 134 }; 135 136 const struct sunxi_gpio_padconf sun20i_d1_padconf = { 137 .npins = __arraycount(d1_pins), 138 .pins = d1_pins, 139 }; 140
Indexes created Tue Sep 30 20:09:53 GMT 2025