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      1  1.2  rumble /*	$NetBSD: int1reg.h,v 1.2 2009/02/12 06:33:57 rumble Exp $	*/
      2  1.1  rumble 
      3  1.1  rumble /*
      4  1.1  rumble  * Copyright (c) 2009 Stephen M. Rumble
      5  1.1  rumble  * All rights reserved.
      6  1.1  rumble  *
      7  1.1  rumble  * Redistribution and use in source and binary forms, with or without
      8  1.1  rumble  * modification, are permitted provided that the following conditions
      9  1.1  rumble  * are met:
     10  1.1  rumble  * 1. Redistributions of source code must retain the above copyright
     11  1.1  rumble  *    notice, this list of conditions and the following disclaimer.
     12  1.1  rumble  * 2. The name of the author may not be used to endorse or promote products
     13  1.1  rumble  *    derived from this software without specific prior written permission.
     14  1.1  rumble  *
     15  1.1  rumble  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  1.1  rumble  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     17  1.1  rumble  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     18  1.1  rumble  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     19  1.1  rumble  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     20  1.1  rumble  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     21  1.1  rumble  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     22  1.1  rumble  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     23  1.1  rumble  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     24  1.1  rumble  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     25  1.1  rumble  */
     26  1.1  rumble 
     27  1.1  rumble #if !defined(_ARCH_SGIMIPS_DEV_INT1REG_H_)
     28  1.1  rumble #define	_ARCH_SGIMIPS_DEV_INT1REG_H_
     29  1.1  rumble 
     30  1.1  rumble /* The INT has known locations on all SGI machines */
     31  1.1  rumble #define	INT1_IP6_IP10		0x1f980000
     32  1.1  rumble 
     33  1.1  rumble /*
     34  1.1  rumble  * NB: The STATUS register is backwards w.r.t. INT2: a bit set implies
     35  1.2  rumble  *     no pending interrupt. The MASK register is like INT2: a bit
     36  1.1  rumble  *     set implies that the interrupt is enabled.
     37  1.1  rumble  */
     38  1.1  rumble #define INT1_LOCAL_STATUS	0x000002	/* 16-bit */
     39  1.1  rumble #define INT1_LOCAL_MASK		0x00000b	/*  8-bit */
     40  1.1  rumble 
     41  1.1  rumble /* i8254 is actually its own chip, but we can pretend to be like INT2... */
     42  1.1  rumble #define INT1_TIMER_0_ACK	0x0a0000	/*  8-bit */
     43  1.1  rumble #define INT1_TIMER_1_ACK	0x080000	/*  8-bit */
     44  1.1  rumble #define INT1_TIMER_0		0x1c0000	/*  8-bit */
     45  1.1  rumble #define	INT1_TIMER_1		0x1c0004	/*  8-bit */
     46  1.1  rumble #define	INT1_TIMER_2		0x1c0008	/*  8-bit */
     47  1.1  rumble #define INT1_TIMER_CONTROL	0x1c000c	/*  8-bit */
     48  1.1  rumble 
     49  1.1  rumble #endif /* _ARCH_SGIMIPS_DEV_INT1REG_H_ */
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