int1reg.h revision 1.2.4.2
1 1.2.4.2 yamt /* $NetBSD: int1reg.h,v 1.2.4.2 2009/05/04 08:11:49 yamt Exp $ */ 2 1.2.4.2 yamt 3 1.2.4.2 yamt /* 4 1.2.4.2 yamt * Copyright (c) 2009 Stephen M. Rumble 5 1.2.4.2 yamt * All rights reserved. 6 1.2.4.2 yamt * 7 1.2.4.2 yamt * Redistribution and use in source and binary forms, with or without 8 1.2.4.2 yamt * modification, are permitted provided that the following conditions 9 1.2.4.2 yamt * are met: 10 1.2.4.2 yamt * 1. Redistributions of source code must retain the above copyright 11 1.2.4.2 yamt * notice, this list of conditions and the following disclaimer. 12 1.2.4.2 yamt * 2. The name of the author may not be used to endorse or promote products 13 1.2.4.2 yamt * derived from this software without specific prior written permission. 14 1.2.4.2 yamt * 15 1.2.4.2 yamt * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 1.2.4.2 yamt * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 1.2.4.2 yamt * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 1.2.4.2 yamt * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 1.2.4.2 yamt * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 1.2.4.2 yamt * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 1.2.4.2 yamt * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 1.2.4.2 yamt * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 1.2.4.2 yamt * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 1.2.4.2 yamt * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 1.2.4.2 yamt */ 26 1.2.4.2 yamt 27 1.2.4.2 yamt #if !defined(_ARCH_SGIMIPS_DEV_INT1REG_H_) 28 1.2.4.2 yamt #define _ARCH_SGIMIPS_DEV_INT1REG_H_ 29 1.2.4.2 yamt 30 1.2.4.2 yamt /* The INT has known locations on all SGI machines */ 31 1.2.4.2 yamt #define INT1_IP6_IP10 0x1f980000 32 1.2.4.2 yamt 33 1.2.4.2 yamt /* 34 1.2.4.2 yamt * NB: The STATUS register is backwards w.r.t. INT2: a bit set implies 35 1.2.4.2 yamt * no pending interrupt. The MASK register is like INT2: a bit 36 1.2.4.2 yamt * set implies that the interrupt is enabled. 37 1.2.4.2 yamt */ 38 1.2.4.2 yamt #define INT1_LOCAL_STATUS 0x000002 /* 16-bit */ 39 1.2.4.2 yamt #define INT1_LOCAL_MASK 0x00000b /* 8-bit */ 40 1.2.4.2 yamt 41 1.2.4.2 yamt /* i8254 is actually its own chip, but we can pretend to be like INT2... */ 42 1.2.4.2 yamt #define INT1_TIMER_0_ACK 0x0a0000 /* 8-bit */ 43 1.2.4.2 yamt #define INT1_TIMER_1_ACK 0x080000 /* 8-bit */ 44 1.2.4.2 yamt #define INT1_TIMER_0 0x1c0000 /* 8-bit */ 45 1.2.4.2 yamt #define INT1_TIMER_1 0x1c0004 /* 8-bit */ 46 1.2.4.2 yamt #define INT1_TIMER_2 0x1c0008 /* 8-bit */ 47 1.2.4.2 yamt #define INT1_TIMER_CONTROL 0x1c000c /* 8-bit */ 48 1.2.4.2 yamt 49 1.2.4.2 yamt #endif /* _ARCH_SGIMIPS_DEV_INT1REG_H_ */ 50
Indexes created Thu Oct 23 22:10:10 GMT 2025