if_mecreg.h revision 1.1
1 /* $NetBSD: if_mecreg.h,v 1.1 2004/01/18 04:06:43 sekiya Exp $ */ 2 3 /* 4 * Copyright (c) 2001 Christopher Sekiya 5 * Copyright (c) 2000 Soren S. Jorvang 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed for the 19 * NetBSD Project. See http://www.NetBSD.org/ for 20 * information about NetBSD. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 /* 37 * MACE MAC110 ethernet register definitions 38 */ 39 40 #define MEC_MAC_CONTROL 0 41 42 #define MEC_MAC_CORE_RESET 0x0000000000000001 43 #define MEC_MAC_FULL_DUPLEX 0x0000000000000002 /* 1 to enable */ 44 #define MEC_MAC_INT_LOOPBACK 0x0000000000000004 /* 0 = normal oper */ 45 #define MEC_MAC_SPEED_SELECT 0x0000000000000008 /* 0/1 10/100 */ 46 #define MEC_MAC_MII_SELECT 0x0000000000000010 47 #define MEC_MAC_FILTER_STATION 0x0000000000000000 48 #define MEC_MAC_FILTER_MATCHMULTI 0x0000000000000020 49 #define MEC_MAC_FILTER_ALLMULTI 0x0000000000000040 50 #define MEC_MAC_FILTER_PROMISC 0x0000000000000060 51 #define MEC_MAC_LINK_FAILURE 0x0000000000000080 52 #define MEC_MAC_IPGT 0x0000000000007f00 53 #define MEC_MAC_IPGT_SHIFT 8 54 #define MEC_MAC_IPGR1 0x00000000003f8000 55 #define MEC_MAC_IPGR1_SHIFT 15 56 #define MEC_MAC_IPGR2 0x000000001fc00000 57 #define MEC_MAC_IPGR2_SHIFT 22 58 #define MEC_MAC_REVISION 0x00000000e0000000 59 #define MEC_MAC_REVISION_SHIFT 29 60 61 #define MEC_INT_STATUS 0x08 62 #define MEC_INT_TX_EMPTY 0x00000001 63 #define MEC_INT_TX_PACKET_SENT 0x00000002 64 #define MEC_INT_TX_LINK_FAIL 0x00000004 65 #define MEC_INT_TX_MEM_ERROR 0x00000008 66 #define MEC_INT_TX_ABORT 0x00000010 67 #define MEC_INT_RX_THRESHOLD 0x00000020 68 #define MEC_INT_RX_FIFO_UNDERFLOW 0x00000040 69 #define MEC_INT_RX_DMA_UNDERFLOW 0x00000080 70 #define MEC_INT_RX_MCL_FIFO_ALIAS 0x00001f00 71 #define MEC_INT_TX_RING_BUFFER_ALIAS 0x01ff0000 72 #define MEC_INT_RX_SEQUENCE_NUMBER 0x3e000000 73 #define MEC_INT_MCAST_HASH_OUTPUT 0x40000000 74 75 #define MEC_DMA_CONTROL 0x10 76 #define MEC_DMA_TX_INT_ENABLE 0x00000001 77 #define MEC_DMA_TX_DMA_ENABLE 0x00000002 78 #define MEC_DMA_TX_RING_SIZE_MASK 0x0000000c 79 #define MEC_DMA_RX_INT_THRESHOLD 0x000001f0 80 #define MEC_DMA_RX_INT_ENABLE 0x00000200 81 #define MEC_DMA_RX_RUNT 0x00000400 82 #define MEC_DMA_RX_PACKET_GATHER 0x00000800 83 #define MEC_DMA_RX_DMA_OFFSET 0x00007000 84 #define MEC_DMA_RX_DMA_ENABLE 0x00008000 85 86 #define MEC_TIMER 0x18 87 #define MEC_TX_ALIAS 0x20 88 #define MEC_TX_ALIAS_INT_ENABLE 0x01 89 90 #define MEC_RX_ALIAS 0x28 91 #define MEC_RX_ALIAS_INT_ENABLE 0x200 92 #define MEC_RX_ALIAS_INT_THRESHOLD 0x1f0 93 94 #define MEC_TX_RING_PTR 0x30 95 #define MEC_TX_RING_WRITE_PTR 0x000001ff 96 #define MEC_TX_RING_READ_PTR 0x01ff0000 97 #define MEC_TX_RING_PTR_ALIAS 0x38 98 99 #define MEC_RX_FIFO 0x40 100 #define MEC_RX_FIFO_ELEMENT_COUNT 0x0000001f 101 #define MEC_RX_FIFO_READ_PTR 0x00000f00 102 #define MEC_RX_FIFO_GEN_NUMBER 0x00001000 103 #define MEC_RX_FIFO_WRITE_PTR 0x000f0000 104 #define MEC_RX_FIFO_GEN_NUMBER_2 0x00100000 105 106 #define MEC_RX_FIFO_ALIAS1 0x48 107 #define MEC_RX_FIFO_ALIAS2 0x50 108 #define MEC_TX_VECTOR 0x58 109 #define MEC_IRQ_VECTOR 0x58 110 111 #define MEC_PHY_DATA 12 << 3 112 #define MEC_PHY_DATA_BUSY 0x8000 113 #define MEC_PHY_DATA_VALUE 0x7fff 114 115 #define MEC_PHY_ADDRESS 13 << 3 116 #define MEC_PHY_ADDR_REGISTER 0x000000000000001f 117 #define MEC_PHY_ADDR_DEVICE 0x00000000000003e0 118 #define MEC_PHY_ADDR_DEVSHIFT 5 119 120 #define MEC_PHY_READ_INITIATE 14 << 3 121 122 #define MEC_PHY_BACKOFF 15 << 3 123 124 #define MEC_STATION 0xa0 125 #define MEC_STATION_ALT 0xa8 126 #define MEC_STATION_MASK 0x0000ffffffffffff 127 128 #define MEC_MULTICAST 0xb0 129 #define MEC_TX_RING_BASE 0xb8 130 #define MEC_TX_PKT1_CMD_1 0xc0 131 #define MEC_TX_PKT1_BUFFER_1 0xc8 132 #define MEC_TX_PKT1_BUFFER_2 0xd0 133 #define MEC_TX_PKT1_BUFFER_3 0xd8 134 #define MEC_TX_PKT2_CMD_1 0xe0 135 #define MEC_TX_PKT2_BUFFER_1 0xe8 136 #define MEC_TX_PKT2_BUFFER_2 0xf0 137 #define MEC_TX_PKT2_BUFFER_3 0xf8 138 #define MEC_MCL_RX_FIFO 0x100 139 140 /* these structs should be moved to if_mecvar.h */ 141 142 /* the first eight bytes of the tx vector are status. it can be a command 143 header, a transmit concatenation pointer, or a status vector. */ 144 145 #define MEC_TX_COMMAND_HDR_LENGTH 0x0000ffff /* length, bytes-1 */ 146 #define MEC_TX_COMMAND_HDR_START_OFFSET 0x007f0000 /* minimum 8 bytes */ 147 #define MEC_TX_COMMAND_HDR_TX_IRQ 0x00800000 /* raise TX DMA on abort */ 148 #define MEC_TX_COMMAND_CONCAT_1 0x01000000 149 #define MEC_TX_COMMAND_CONCAT_2 0x02000000 150 #define MEC_TX_COMMAND_CONCAT_3 0x04000000 151 152 #define MEC_TX_CONCAT_PTR_ADDRESS 0x00000000fffffff8 153 #define MEC_TX_CONCAT_PTR_LENGTH 0x0000ffff00000000 154 155 #define MEC_TX_STATUS_VECTOR_LENGTH 0x000000000000ffff 156 #define MEC_TX_STATUS_VECTOR_COL_RETRY 0x00000000000f0000 157 #define MEC_TX_STATUS_VECTOR_LATE_COLLISION 0x0000000000100000 158 #define MEC_TX_STATUS_VECTOR_CRC_ERROR 0x0000000000200000 159 #define MEC_TX_STATUS_VECTOR_DEFERRED 0x0000000000400000 160 #define MEC_TX_STATUS_VECTOR_TX_SUCCESS 0x0000000000800000 161 #define MEC_TX_STATUS_VECTOR_TOOBIG 0x0000000001000000 162 #define MEC_TX_STATUS_VECTOR_UNDERRUN 0x0000000002000000 163 #define MEC_TX_STATUS_VECTOR_COLLISIONS 0x0000000004000000 164 #define MEC_TX_STATUS_VECTOR_EX_DEFERRAL 0x0000000008000000 165 #define MEC_TX_STATUS_VECTOR_COLLIDED 0x0000000010000000 166 #define MEC_TX_STATUS_VECTOR_VALID 0x8000000000000000 167 168 struct tx_fifo { 169 u_int64_t control; 170 u_int8_t data[120]; 171 }; 172 173 struct rx_fifo { 174 u_int64_t control; 175 u_int8_t data[120]; 176 }; 177
Indexes created Wed Oct 01 07:09:59 GMT 2025