mace.c revision 1.19
1 /* $NetBSD: mace.c,v 1.19 2012/10/27 17:18:10 chs Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Christopher Sekiya 5 * Copyright (c) 2002,2003 Rafal K. Boni 6 * Copyright (c) 2000 Soren S. Jorvang 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * O2 MACE 39 * 40 * The MACE is weird -- although it is a 32-bit device, writes only seem to 41 * work properly if they are 64-bit-at-once writes (at least, out in ISA 42 * space and probably MEC space -- the PCI stuff seems to be okay with _4). 43 * Therefore, the _8* routines are used even though the top 32 bits are 44 * thrown away. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: mace.c,v 1.19 2012/10/27 17:18:10 chs Exp $"); 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/callout.h> 54 #include <sys/mbuf.h> 55 #include <sys/malloc.h> 56 #include <sys/kernel.h> 57 #include <sys/socket.h> 58 #include <sys/ioctl.h> 59 #include <sys/errno.h> 60 #include <sys/syslog.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #define _SGIMIPS_BUS_DMA_PRIVATE 65 #include <sys/bus.h> 66 #include <machine/cpu.h> 67 #include <machine/locore.h> 68 #include <machine/autoconf.h> 69 #include <machine/machtype.h> 70 71 #include <sgimips/mace/macevar.h> 72 #include <sgimips/mace/macereg.h> 73 #include <sgimips/dev/crimevar.h> 74 #include <sgimips/dev/crimereg.h> 75 76 #include "locators.h" 77 78 #define MACE_NINTR 32 /* actually only 8, but interrupts are shared */ 79 80 struct { 81 unsigned int irq; 82 unsigned int intrmask; 83 int (*func)(void *); 84 void *arg; 85 struct evcnt evcnt; 86 char evname[32]; 87 } maceintrtab[MACE_NINTR]; 88 89 struct mace_softc { 90 device_t sc_dev; 91 92 bus_space_tag_t iot; 93 bus_space_handle_t ioh; 94 bus_dma_tag_t dmat; /* 32KB ring buffers, 4KB segments, for ISA */ 95 int nsegs; 96 bus_dma_segment_t seg; 97 bus_dmamap_t map; 98 99 void *isa_ringbuffer; 100 }; 101 102 static int mace_match(device_t, cfdata_t, void *); 103 static void mace_attach(device_t, device_t, void *); 104 static int mace_print(void *, const char *); 105 static int mace_search(device_t, cfdata_t, const int *, void *); 106 107 CFATTACH_DECL_NEW(mace, sizeof(struct mace_softc), 108 mace_match, mace_attach, NULL, NULL); 109 110 #if defined(BLINK) 111 static callout_t mace_blink_ch; 112 static void mace_blink(void *); 113 #endif 114 115 static int 116 mace_match(device_t parent, struct cfdata *match, void *aux) 117 { 118 119 /* 120 * The MACE is in the O2. 121 */ 122 if (mach_type == MACH_SGI_IP32) 123 return 1; 124 125 return 0; 126 } 127 128 static void 129 mace_attach(device_t parent, device_t self, void *aux) 130 { 131 struct mace_softc *sc = device_private(self); 132 struct mainbus_attach_args *ma = aux; 133 uint32_t scratch; 134 135 sc->sc_dev = self; 136 #ifdef BLINK 137 callout_init(&mace_blink_ch, 0); 138 #endif 139 140 sc->iot = SGIMIPS_BUS_SPACE_MACE; 141 sc->dmat = &sgimips_default_bus_dma_tag; 142 143 if (bus_space_map(sc->iot, ma->ma_addr, 0, 144 BUS_SPACE_MAP_LINEAR, &sc->ioh)) 145 panic("mace_attach: could not allocate memory\n"); 146 147 aprint_normal("\n"); 148 149 aprint_debug("%s: isa sts %#"PRIx64"\n", device_xname(self), 150 bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS)); 151 aprint_debug("%s: isa msk %#"PRIx64"\n", device_xname(self), 152 bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK)); 153 154 /* 155 * Turn on most ISA interrupts. These are actually masked and 156 * registered via the CRIME, as the MACE ISA interrupt mask is 157 * really whacky and nigh on impossible to map to a sane autoconfig 158 * scheme. We do, however, turn off the count/compare timer and RTC 159 * interrupts as they are unused and conflict with the PS/2 160 * keyboard and mouse interrupts. 161 */ 162 163 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK, 0xffff0aff); 164 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS, 0); 165 166 /* set up LED for solid green or blink, if that's your fancy */ 167 scratch = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); 168 scratch |= MACE_ISA_LED_RED; 169 scratch &= ~(MACE_ISA_LED_GREEN); 170 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, scratch); 171 172 #if defined(BLINK) 173 mace_blink(sc); 174 #endif 175 176 /* Initialize the maceintr elements to sane values */ 177 for (scratch = 0; scratch < MACE_NINTR; scratch++) { 178 maceintrtab[scratch].func = NULL; 179 maceintrtab[scratch].irq = 0; 180 } 181 182 config_search_ia(mace_search, self, "mace", NULL); 183 } 184 185 186 static int 187 mace_print(void *aux, const char *pnp) 188 { 189 struct mace_attach_args *maa = aux; 190 191 if (pnp != 0) 192 return QUIET; 193 194 if (maa->maa_offset != MACECF_OFFSET_DEFAULT) 195 aprint_normal(" offset 0x%lx", maa->maa_offset); 196 if (maa->maa_intr != MACECF_INTR_DEFAULT) 197 aprint_normal(" intr %d", maa->maa_intr); 198 if (maa->maa_offset != MACECF_INTRMASK_DEFAULT) 199 aprint_normal(" intrmask 0x%x", maa->maa_intrmask); 200 201 return UNCONF; 202 } 203 204 static int 205 mace_search(device_t parent, struct cfdata *cf, const int *ldesc, void *aux) 206 { 207 struct mace_softc *sc = device_private(parent); 208 struct mace_attach_args maa; 209 int tryagain; 210 211 do { 212 maa.maa_offset = cf->cf_loc[MACECF_OFFSET]; 213 maa.maa_intr = cf->cf_loc[MACECF_INTR]; 214 maa.maa_intrmask = cf->cf_loc[MACECF_INTRMASK]; 215 maa.maa_st = SGIMIPS_BUS_SPACE_MACE; 216 maa.maa_sh = sc->ioh; /* XXX */ 217 maa.maa_dmat = &sgimips_default_bus_dma_tag; 218 maa.isa_ringbuffer = sc->isa_ringbuffer; 219 220 tryagain = 0; 221 if (config_match(parent, cf, &maa) > 0) { 222 config_attach(parent, cf, &maa, mace_print); 223 tryagain = (cf->cf_fstate == FSTATE_STAR); 224 } 225 226 } while (tryagain); 227 228 return 0; 229 } 230 231 void * 232 mace_intr_establish(int intr, int level, int (*func)(void *), void *arg) 233 { 234 int i; 235 236 if (intr < 0 || intr >= 16) 237 panic("invalid interrupt number"); 238 239 for (i = 0; i < MACE_NINTR; i++) 240 if (maceintrtab[i].func == NULL) { 241 maceintrtab[i].func = func; 242 maceintrtab[i].arg = arg; 243 maceintrtab[i].irq = (1 << intr); 244 maceintrtab[i].intrmask = level; 245 snprintf(maceintrtab[i].evname, 246 sizeof(maceintrtab[i].evname), 247 "intr %d level 0x%x", intr, level); 248 evcnt_attach_dynamic(&maceintrtab[i].evcnt, 249 EVCNT_TYPE_INTR, NULL, 250 "mace", maceintrtab[i].evname); 251 break; 252 } 253 254 crime_intr_mask(intr); 255 aprint_debug("mace: established interrupt %d (level %x)\n", 256 intr, level); 257 return (void *)&maceintrtab[i]; 258 } 259 260 void 261 mace_intr_disestablish(void *cookie) 262 { 263 int intr = -1, level = 0, irq = 0, i; 264 265 for (i = 0; i < MACE_NINTR; i++) 266 if (&maceintrtab[i] == cookie) { 267 evcnt_detach(&maceintrtab[i].evcnt); 268 for (intr = 0; 269 maceintrtab[i].irq == (1 << intr); intr++); 270 level = maceintrtab[i].intrmask; 271 irq = maceintrtab[i].irq; 272 273 maceintrtab[i].irq = 0; 274 maceintrtab[i].intrmask = 0; 275 maceintrtab[i].func = NULL; 276 maceintrtab[i].arg = NULL; 277 memset(&maceintrtab[i].evcnt, 0, sizeof (struct evcnt)); 278 memset(&maceintrtab[i].evname, 0, 279 sizeof (maceintrtab[i].evname)); 280 break; 281 } 282 if (intr == -1) 283 panic("mace: lost maceintrtab"); 284 285 /* do not do an unmask when irq is shared. */ 286 for (i = 0; i < MACE_NINTR; i++) 287 if (&maceintrtab[i].func != NULL && maceintrtab[i].irq == irq) 288 break; 289 if (i == MACE_NINTR) 290 crime_intr_unmask(intr); 291 aprint_debug("mace: disestablished interrupt %d (level %x)\n", 292 intr, level); 293 } 294 295 void 296 mace_intr(int irqs) 297 { 298 uint64_t isa_irq, isa_mask; 299 int i; 300 301 /* irq 4 is the ISA cascade interrupt. Must handle with care. */ 302 if (irqs & (1 << 4)) { 303 isa_mask = mips3_ld((volatile uint64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE 304 + MACE_ISA_INT_MASK)); 305 isa_irq = mips3_ld((volatile uint64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE 306 + MACE_ISA_INT_STATUS)); 307 for (i = 0; i < MACE_NINTR; i++) { 308 if ((maceintrtab[i].irq == (1 << 4)) && 309 (isa_irq & maceintrtab[i].intrmask)) { 310 (maceintrtab[i].func)(maceintrtab[i].arg); 311 maceintrtab[i].evcnt.ev_count++; 312 } 313 } 314 irqs &= ~(1 << 4); 315 } 316 317 for (i = 0; i < MACE_NINTR; i++) 318 if ((irqs & maceintrtab[i].irq)) { 319 (maceintrtab[i].func)(maceintrtab[i].arg); 320 maceintrtab[i].evcnt.ev_count++; 321 } 322 } 323 324 #if defined(BLINK) 325 static void 326 mace_blink(void *self) 327 { 328 struct mace_softc *sc = device_private(self); 329 register int s; 330 int value; 331 332 s = splhigh(); 333 value = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); 334 value ^= MACE_ISA_LED_GREEN; 335 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, value); 336 splx(s); 337 /* 338 * Blink rate is: 339 * full cycle every second if completely idle (loadav = 0) 340 * full cycle every 2 seconds if loadav = 1 341 * full cycle every 3 seconds if loadav = 2 342 * etc. 343 */ 344 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 345 callout_reset(&mace_blink_ch, s, mace_blink, sc); 346 347 } 348 #endif 349
Indexes created Mon Sep 29 21:09:56 GMT 2025