mace.c revision 1.2
1 /* $NetBSD: mace.c,v 1.2 2004/07/10 07:39:13 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Christopher Sekiya 5 * Copyright (c) 2002,2003 Rafal K. Boni 6 * Copyright (c) 2000 Soren S. Jorvang 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * O2 MACE 39 * 40 * The MACE is weird -- although it is a 32-bit device, writes only seem to 41 * work properly if they are 64-bit-at-once writes (at least, out in ISA 42 * space and probably MEC space -- the PCI stuff seems to be okay with _4). 43 * Therefore, the _8* routines are used even though the top 32 bits are 44 * thrown away. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: mace.c,v 1.2 2004/07/10 07:39:13 tsutsui Exp $"); 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/callout.h> 54 #include <sys/mbuf.h> 55 #include <sys/malloc.h> 56 #include <sys/kernel.h> 57 #include <sys/socket.h> 58 #include <sys/ioctl.h> 59 #include <sys/errno.h> 60 #include <sys/syslog.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #define _SGIMIPS_BUS_DMA_PRIVATE 65 #include <machine/bus.h> 66 #include <machine/cpu.h> 67 #include <machine/locore.h> 68 #include <machine/autoconf.h> 69 #include <machine/machtype.h> 70 71 #include <sgimips/mace/macevar.h> 72 #include <sgimips/mace/macereg.h> 73 #include <sgimips/dev/crimevar.h> 74 #include <sgimips/dev/crimereg.h> 75 76 #include "locators.h" 77 78 #define MACE_NINTR 32 /* actually only 8, but interrupts are shared */ 79 80 struct { 81 unsigned int irq; 82 unsigned int intrmask; 83 int (*func)(void *); 84 void *arg; 85 } maceintrtab[MACE_NINTR]; 86 87 struct mace_softc { 88 struct device sc_dev; 89 90 bus_space_tag_t iot; 91 bus_space_handle_t ioh; 92 bus_dma_tag_t dmat; /* 32KB ring buffers, 4KB segments, for ISA */ 93 int nsegs; 94 bus_dma_segment_t seg; 95 bus_dmamap_t map; 96 97 void *isa_ringbuffer; 98 }; 99 100 static int mace_match(struct device *, struct cfdata *, void *); 101 static void mace_attach(struct device *, struct device *, void *); 102 static int mace_print(void *, const char *); 103 static int mace_search(struct device *, struct cfdata *, void *); 104 105 CFATTACH_DECL(mace, sizeof(struct mace_softc), 106 mace_match, mace_attach, NULL, NULL); 107 108 #if defined(BLINK) 109 static struct callout mace_blink_ch = CALLOUT_INITIALIZER; 110 static void mace_blink(void *); 111 #endif 112 113 static int 114 mace_match(struct device *parent, struct cfdata *match, void *aux) 115 { 116 117 /* 118 * The MACE is in the O2. 119 */ 120 if (mach_type == MACH_SGI_IP32) 121 return (1); 122 123 return (0); 124 } 125 126 static void 127 mace_attach(struct device *parent, struct device *self, void *aux) 128 { 129 struct mace_softc *sc = (struct mace_softc *)self; 130 struct mainbus_attach_args *ma = aux; 131 u_int32_t scratch; 132 133 sc->iot = SGIMIPS_BUS_SPACE_MACE; 134 sc->dmat = &sgimips_default_bus_dma_tag; 135 136 if (bus_space_map(sc->iot, ma->ma_addr, 0, 137 BUS_SPACE_MAP_LINEAR, &sc->ioh)) 138 panic("mace_attach: could not allocate memory\n"); 139 140 #if 0 141 /* 142 * There's something deeply wrong with the alloc() routine -- it 143 * returns a pointer to memory that is used by the kernel i/o 144 * buffers. Disable for now. 145 */ 146 147 if ((bus_dmamem_alloc(sc->dmat, 32768, PAGE_SIZE, 32768, 148 &sc->seg, 1, &sc->nsegs, BUS_DMA_NOWAIT)) != 0) { 149 printf(": unable to allocate DMA memory\n"); 150 return; 151 } 152 153 if ((bus_dmamem_map(sc->dmat, &sc->seg, sc->nsegs, 32768, 154 (caddr_t *)&sc->isa_ringbuffer, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) 155 != 0) { 156 printf(": unable to map control data\n"); 157 return; 158 } 159 160 if ((bus_dmamap_create(sc->dmat, 32768, 1, 32768, 0, 161 BUS_DMA_NOWAIT, &sc->map)) != 0) { 162 printf(": unable to create DMA map for control data\n"); 163 return; 164 } 165 166 if ((scratch = bus_dmamap_load(sc->dmat, sc->map, sc->isa_ringbuffer, 167 32768, NULL, BUS_DMA_NOWAIT)) != 0) { 168 printf(": unable to load DMA map for control data %i\n", 169 scratch); 170 } 171 172 memset(sc->isa_ringbuffer, 0, 32768); 173 174 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_RINGBASE, 175 MIPS_KSEG1_TO_PHYS(sc->isa_ringbuffer) & 0xffff8000); 176 177 aprint_normal(" isa ringbuffer 0x%x size 32k", 178 MIPS_KSEG1_TO_PHYS((unsigned long)sc->isa_ringbuffer)); 179 #endif 180 181 aprint_normal("\n"); 182 183 aprint_debug("%s: isa sts %llx\n", self->dv_xname, 184 bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS)); 185 aprint_debug("%s: isa msk %llx\n", self->dv_xname, 186 bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK)); 187 188 /* 189 * Turn on all ISA interrupts. These are actually masked and 190 * registered via the CRIME, as the MACE ISA interrupt mask is 191 * really whacky and nigh on impossible to map to a sane autoconfig 192 * scheme. 193 */ 194 195 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK, 0xffffffff); 196 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS, 0); 197 198 /* set up LED for solid green or blink, if that's your fancy */ 199 scratch = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); 200 scratch |= MACE_ISA_LED_RED; 201 scratch &= ~(MACE_ISA_LED_GREEN); 202 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, scratch); 203 204 #if defined(BLINK) 205 mace_blink(sc); 206 #endif 207 208 /* Initialize the maceintr elements to sane values */ 209 for (scratch = 0; scratch < MACE_NINTR; scratch++) { 210 maceintrtab[scratch].func = NULL; 211 maceintrtab[scratch].irq = 0; 212 } 213 214 config_search(mace_search, self, NULL); 215 } 216 217 218 static int 219 mace_print(void *aux, const char *pnp) 220 { 221 struct mace_attach_args *maa = aux; 222 223 if (pnp != 0) 224 return QUIET; 225 226 if (maa->maa_offset != MACECF_OFFSET_DEFAULT) 227 aprint_normal(" offset 0x%lx", maa->maa_offset); 228 if (maa->maa_intr != MACECF_INTR_DEFAULT) 229 aprint_normal(" intr %d", maa->maa_intr); 230 if (maa->maa_offset != MACECF_INTRMASK_DEFAULT) 231 aprint_normal(" intrmask 0x%x", maa->maa_intrmask); 232 233 return UNCONF; 234 } 235 236 static int 237 mace_search(struct device *parent, struct cfdata *cf, void *aux) 238 { 239 struct mace_softc *sc = (struct mace_softc *)parent; 240 struct mace_attach_args maa; 241 int tryagain; 242 243 do { 244 maa.maa_offset = cf->cf_loc[MACECF_OFFSET]; 245 maa.maa_intr = cf->cf_loc[MACECF_INTR]; 246 maa.maa_intrmask = cf->cf_loc[MACECF_INTRMASK]; 247 maa.maa_st = SGIMIPS_BUS_SPACE_MACE; 248 maa.maa_sh = sc->ioh; /* XXX */ 249 maa.maa_dmat = &sgimips_default_bus_dma_tag; 250 maa.isa_ringbuffer = sc->isa_ringbuffer; 251 252 tryagain = 0; 253 if (config_match(parent, cf, &maa) > 0) { 254 config_attach(parent, cf, &maa, mace_print); 255 tryagain = (cf->cf_fstate == FSTATE_STAR); 256 } 257 258 } while (tryagain); 259 260 return 0; 261 } 262 263 void * 264 mace_intr_establish(int intr, int level, int (*func)(void *), void *arg) 265 { 266 int i; 267 268 if (intr < 0 || intr >= 8) 269 panic("invalid interrupt number"); 270 271 for (i = 0; i < MACE_NINTR; i++) 272 if (maceintrtab[i].func == NULL) { 273 maceintrtab[i].func = func; 274 maceintrtab[i].arg = arg; 275 maceintrtab[i].irq = (1 << intr); 276 maceintrtab[i].intrmask = level; 277 break; 278 } 279 280 crime_intr_mask(intr); 281 aprint_normal("mace: established interrupt %d (level %x)\n", 282 intr, level); 283 return (void *)&maceintrtab[i]; 284 } 285 286 void 287 mace_intr(int irqs) 288 { 289 u_int64_t isa_irq, isa_mask; 290 int i; 291 292 /* irq 4 is the ISA cascade interrupt. Must handle with care. */ 293 if (irqs & (1 << 4)) { 294 isa_mask = mips3_ld((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE 295 + MACE_ISA_INT_MASK)); 296 isa_irq = mips3_ld((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE 297 + MACE_ISA_INT_STATUS)); 298 for (i = 0; i < MACE_NINTR; i++) { 299 if ((maceintrtab[i].irq == (1 << 4)) && 300 (isa_irq & maceintrtab[i].intrmask)) { 301 if (isa_irq & 0xfc000000) 302 printf("dispatching\n"); 303 304 (maceintrtab[i].func)(maceintrtab[i].arg); 305 } 306 } 307 #if 0 308 mips3_sd((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE 309 + MACE_ISA_INT_STATUS), isa_mask); 310 #endif 311 irqs &= ~(1 << 4); 312 } 313 314 for (i = 0; i < MACE_NINTR; i++) 315 if ((irqs & maceintrtab[i].irq)) 316 (maceintrtab[i].func)(maceintrtab[i].arg); 317 } 318 319 #if defined(BLINK) 320 static void 321 mace_blink(void *self) 322 { 323 struct mace_softc *sc = (struct mace_softc *) self; 324 register int s; 325 int value; 326 327 s = splhigh(); 328 value = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); 329 value ^= MACE_ISA_LED_GREEN; 330 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, value); 331 splx(s); 332 /* 333 * Blink rate is: 334 * full cycle every second if completely idle (loadav = 0) 335 * full cycle every 2 seconds if loadav = 1 336 * full cycle every 3 seconds if loadav = 2 337 * etc. 338 */ 339 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 340 callout_reset(&mace_blink_ch, s, mace_blink, sc); 341 342 } 343 #endif 344
Indexes created Mon Sep 29 21:09:56 GMT 2025