mace.c revision 1.4
1 /* $NetBSD: mace.c,v 1.4 2004/07/10 08:47:33 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Christopher Sekiya 5 * Copyright (c) 2002,2003 Rafal K. Boni 6 * Copyright (c) 2000 Soren S. Jorvang 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * O2 MACE 39 * 40 * The MACE is weird -- although it is a 32-bit device, writes only seem to 41 * work properly if they are 64-bit-at-once writes (at least, out in ISA 42 * space and probably MEC space -- the PCI stuff seems to be okay with _4). 43 * Therefore, the _8* routines are used even though the top 32 bits are 44 * thrown away. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: mace.c,v 1.4 2004/07/10 08:47:33 tsutsui Exp $"); 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/callout.h> 54 #include <sys/mbuf.h> 55 #include <sys/malloc.h> 56 #include <sys/kernel.h> 57 #include <sys/socket.h> 58 #include <sys/ioctl.h> 59 #include <sys/errno.h> 60 #include <sys/syslog.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #define _SGIMIPS_BUS_DMA_PRIVATE 65 #include <machine/bus.h> 66 #include <machine/cpu.h> 67 #include <machine/locore.h> 68 #include <machine/autoconf.h> 69 #include <machine/machtype.h> 70 71 #include <sgimips/mace/macevar.h> 72 #include <sgimips/mace/macereg.h> 73 #include <sgimips/dev/crimevar.h> 74 #include <sgimips/dev/crimereg.h> 75 76 #include "locators.h" 77 78 #define MACE_NINTR 32 /* actually only 8, but interrupts are shared */ 79 80 struct { 81 unsigned int irq; 82 unsigned int intrmask; 83 int (*func)(void *); 84 void *arg; 85 struct evcnt evcnt; 86 char evname[32]; 87 } maceintrtab[MACE_NINTR]; 88 89 struct mace_softc { 90 struct device sc_dev; 91 92 bus_space_tag_t iot; 93 bus_space_handle_t ioh; 94 bus_dma_tag_t dmat; /* 32KB ring buffers, 4KB segments, for ISA */ 95 int nsegs; 96 bus_dma_segment_t seg; 97 bus_dmamap_t map; 98 99 void *isa_ringbuffer; 100 }; 101 102 static int mace_match(struct device *, struct cfdata *, void *); 103 static void mace_attach(struct device *, struct device *, void *); 104 static int mace_print(void *, const char *); 105 static int mace_search(struct device *, struct cfdata *, void *); 106 107 CFATTACH_DECL(mace, sizeof(struct mace_softc), 108 mace_match, mace_attach, NULL, NULL); 109 110 #if defined(BLINK) 111 static struct callout mace_blink_ch = CALLOUT_INITIALIZER; 112 static void mace_blink(void *); 113 #endif 114 115 static int 116 mace_match(struct device *parent, struct cfdata *match, void *aux) 117 { 118 119 /* 120 * The MACE is in the O2. 121 */ 122 if (mach_type == MACH_SGI_IP32) 123 return (1); 124 125 return (0); 126 } 127 128 static void 129 mace_attach(struct device *parent, struct device *self, void *aux) 130 { 131 struct mace_softc *sc = (struct mace_softc *)self; 132 struct mainbus_attach_args *ma = aux; 133 u_int32_t scratch; 134 135 sc->iot = SGIMIPS_BUS_SPACE_MACE; 136 sc->dmat = &sgimips_default_bus_dma_tag; 137 138 if (bus_space_map(sc->iot, ma->ma_addr, 0, 139 BUS_SPACE_MAP_LINEAR, &sc->ioh)) 140 panic("mace_attach: could not allocate memory\n"); 141 142 #if 0 143 /* 144 * There's something deeply wrong with the alloc() routine -- it 145 * returns a pointer to memory that is used by the kernel i/o 146 * buffers. Disable for now. 147 */ 148 149 if ((bus_dmamem_alloc(sc->dmat, 32768, PAGE_SIZE, 32768, 150 &sc->seg, 1, &sc->nsegs, BUS_DMA_NOWAIT)) != 0) { 151 printf(": unable to allocate DMA memory\n"); 152 return; 153 } 154 155 if ((bus_dmamem_map(sc->dmat, &sc->seg, sc->nsegs, 32768, 156 (caddr_t *)&sc->isa_ringbuffer, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) 157 != 0) { 158 printf(": unable to map control data\n"); 159 return; 160 } 161 162 if ((bus_dmamap_create(sc->dmat, 32768, 1, 32768, 0, 163 BUS_DMA_NOWAIT, &sc->map)) != 0) { 164 printf(": unable to create DMA map for control data\n"); 165 return; 166 } 167 168 if ((scratch = bus_dmamap_load(sc->dmat, sc->map, sc->isa_ringbuffer, 169 32768, NULL, BUS_DMA_NOWAIT)) != 0) { 170 printf(": unable to load DMA map for control data %i\n", 171 scratch); 172 } 173 174 memset(sc->isa_ringbuffer, 0, 32768); 175 176 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_RINGBASE, 177 MIPS_KSEG1_TO_PHYS(sc->isa_ringbuffer) & 0xffff8000); 178 179 aprint_normal(" isa ringbuffer 0x%x size 32k", 180 MIPS_KSEG1_TO_PHYS((unsigned long)sc->isa_ringbuffer)); 181 #endif 182 183 aprint_normal("\n"); 184 185 aprint_debug("%s: isa sts %llx\n", self->dv_xname, 186 bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS)); 187 aprint_debug("%s: isa msk %llx\n", self->dv_xname, 188 bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK)); 189 190 /* 191 * Turn on all ISA interrupts. These are actually masked and 192 * registered via the CRIME, as the MACE ISA interrupt mask is 193 * really whacky and nigh on impossible to map to a sane autoconfig 194 * scheme. 195 */ 196 197 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK, 0xffffffff); 198 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS, 0); 199 200 /* set up LED for solid green or blink, if that's your fancy */ 201 scratch = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); 202 scratch |= MACE_ISA_LED_RED; 203 scratch &= ~(MACE_ISA_LED_GREEN); 204 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, scratch); 205 206 #if defined(BLINK) 207 mace_blink(sc); 208 #endif 209 210 /* Initialize the maceintr elements to sane values */ 211 for (scratch = 0; scratch < MACE_NINTR; scratch++) { 212 maceintrtab[scratch].func = NULL; 213 maceintrtab[scratch].irq = 0; 214 } 215 216 config_search(mace_search, self, NULL); 217 } 218 219 220 static int 221 mace_print(void *aux, const char *pnp) 222 { 223 struct mace_attach_args *maa = aux; 224 225 if (pnp != 0) 226 return QUIET; 227 228 if (maa->maa_offset != MACECF_OFFSET_DEFAULT) 229 aprint_normal(" offset 0x%lx", maa->maa_offset); 230 if (maa->maa_intr != MACECF_INTR_DEFAULT) 231 aprint_normal(" intr %d", maa->maa_intr); 232 if (maa->maa_offset != MACECF_INTRMASK_DEFAULT) 233 aprint_normal(" intrmask 0x%x", maa->maa_intrmask); 234 235 return UNCONF; 236 } 237 238 static int 239 mace_search(struct device *parent, struct cfdata *cf, void *aux) 240 { 241 struct mace_softc *sc = (struct mace_softc *)parent; 242 struct mace_attach_args maa; 243 int tryagain; 244 245 do { 246 maa.maa_offset = cf->cf_loc[MACECF_OFFSET]; 247 maa.maa_intr = cf->cf_loc[MACECF_INTR]; 248 maa.maa_intrmask = cf->cf_loc[MACECF_INTRMASK]; 249 maa.maa_st = SGIMIPS_BUS_SPACE_MACE; 250 maa.maa_sh = sc->ioh; /* XXX */ 251 maa.maa_dmat = &sgimips_default_bus_dma_tag; 252 maa.isa_ringbuffer = sc->isa_ringbuffer; 253 254 tryagain = 0; 255 if (config_match(parent, cf, &maa) > 0) { 256 config_attach(parent, cf, &maa, mace_print); 257 tryagain = (cf->cf_fstate == FSTATE_STAR); 258 } 259 260 } while (tryagain); 261 262 return 0; 263 } 264 265 void * 266 mace_intr_establish(int intr, int level, int (*func)(void *), void *arg) 267 { 268 int i; 269 270 if (intr < 0 || intr >= 8) 271 panic("invalid interrupt number"); 272 273 for (i = 0; i < MACE_NINTR; i++) 274 if (maceintrtab[i].func == NULL) { 275 maceintrtab[i].func = func; 276 maceintrtab[i].arg = arg; 277 maceintrtab[i].irq = (1 << intr); 278 maceintrtab[i].intrmask = level; 279 snprintf(maceintrtab[i].evname, 280 sizeof(maceintrtab[i].evname), 281 "intr %d level 0x%x", intr, level); 282 evcnt_attach_dynamic(&maceintrtab[i].evcnt, 283 EVCNT_TYPE_INTR, NULL, 284 "mace", maceintrtab[i].evname); 285 break; 286 } 287 288 crime_intr_mask(intr); 289 aprint_normal("mace: established interrupt %d (level %x)\n", 290 intr, level); 291 return (void *)&maceintrtab[i]; 292 } 293 294 void 295 mace_intr(int irqs) 296 { 297 u_int64_t isa_irq, isa_mask; 298 int i; 299 300 /* irq 4 is the ISA cascade interrupt. Must handle with care. */ 301 if (irqs & (1 << 4)) { 302 isa_mask = mips3_ld((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE 303 + MACE_ISA_INT_MASK)); 304 isa_irq = mips3_ld((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE 305 + MACE_ISA_INT_STATUS)); 306 for (i = 0; i < MACE_NINTR; i++) { 307 if ((maceintrtab[i].irq == (1 << 4)) && 308 (isa_irq & maceintrtab[i].intrmask)) { 309 (maceintrtab[i].func)(maceintrtab[i].arg); 310 maceintrtab[i].evcnt.ev_count++; 311 } 312 } 313 #if 0 314 mips3_sd((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE 315 + MACE_ISA_INT_STATUS), isa_mask); 316 #endif 317 irqs &= ~(1 << 4); 318 } 319 320 for (i = 0; i < MACE_NINTR; i++) 321 if ((irqs & maceintrtab[i].irq)) { 322 (maceintrtab[i].func)(maceintrtab[i].arg); 323 maceintrtab[i].evcnt.ev_count++; 324 } 325 } 326 327 #if defined(BLINK) 328 static void 329 mace_blink(void *self) 330 { 331 struct mace_softc *sc = (struct mace_softc *) self; 332 register int s; 333 int value; 334 335 s = splhigh(); 336 value = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); 337 value ^= MACE_ISA_LED_GREEN; 338 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, value); 339 splx(s); 340 /* 341 * Blink rate is: 342 * full cycle every second if completely idle (loadav = 0) 343 * full cycle every 2 seconds if loadav = 1 344 * full cycle every 3 seconds if loadav = 2 345 * etc. 346 */ 347 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 348 callout_reset(&mace_blink_ch, s, mace_blink, sc); 349 350 } 351 #endif 352
Indexes created Mon Sep 29 03:10:08 GMT 2025