mace.c revision 1.8
1 /* $NetBSD: mace.c,v 1.8 2005/11/26 06:18:40 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Christopher Sekiya 5 * Copyright (c) 2002,2003 Rafal K. Boni 6 * Copyright (c) 2000 Soren S. Jorvang 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the 20 * NetBSD Project. See http://www.NetBSD.org/ for 21 * information about NetBSD. 22 * 4. The name of the author may not be used to endorse or promote products 23 * derived from this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37 /* 38 * O2 MACE 39 * 40 * The MACE is weird -- although it is a 32-bit device, writes only seem to 41 * work properly if they are 64-bit-at-once writes (at least, out in ISA 42 * space and probably MEC space -- the PCI stuff seems to be okay with _4). 43 * Therefore, the _8* routines are used even though the top 32 bits are 44 * thrown away. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: mace.c,v 1.8 2005/11/26 06:18:40 tsutsui Exp $"); 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/device.h> 53 #include <sys/callout.h> 54 #include <sys/mbuf.h> 55 #include <sys/malloc.h> 56 #include <sys/kernel.h> 57 #include <sys/socket.h> 58 #include <sys/ioctl.h> 59 #include <sys/errno.h> 60 #include <sys/syslog.h> 61 62 #include <uvm/uvm_extern.h> 63 64 #define _SGIMIPS_BUS_DMA_PRIVATE 65 #include <machine/bus.h> 66 #include <machine/cpu.h> 67 #include <machine/locore.h> 68 #include <machine/autoconf.h> 69 #include <machine/machtype.h> 70 71 #include <sgimips/mace/macevar.h> 72 #include <sgimips/mace/macereg.h> 73 #include <sgimips/dev/crimevar.h> 74 #include <sgimips/dev/crimereg.h> 75 76 #include "locators.h" 77 78 #define MACE_NINTR 32 /* actually only 8, but interrupts are shared */ 79 80 struct { 81 unsigned int irq; 82 unsigned int intrmask; 83 int (*func)(void *); 84 void *arg; 85 struct evcnt evcnt; 86 char evname[32]; 87 } maceintrtab[MACE_NINTR]; 88 89 struct mace_softc { 90 struct device sc_dev; 91 92 bus_space_tag_t iot; 93 bus_space_handle_t ioh; 94 bus_dma_tag_t dmat; /* 32KB ring buffers, 4KB segments, for ISA */ 95 int nsegs; 96 bus_dma_segment_t seg; 97 bus_dmamap_t map; 98 99 void *isa_ringbuffer; 100 }; 101 102 static int mace_match(struct device *, struct cfdata *, void *); 103 static void mace_attach(struct device *, struct device *, void *); 104 static int mace_print(void *, const char *); 105 static int mace_search(struct device *, struct cfdata *, 106 const int *, void *); 107 108 CFATTACH_DECL(mace, sizeof(struct mace_softc), 109 mace_match, mace_attach, NULL, NULL); 110 111 #if defined(BLINK) 112 static struct callout mace_blink_ch = CALLOUT_INITIALIZER; 113 static void mace_blink(void *); 114 #endif 115 116 static int 117 mace_match(struct device *parent, struct cfdata *match, void *aux) 118 { 119 120 /* 121 * The MACE is in the O2. 122 */ 123 if (mach_type == MACH_SGI_IP32) 124 return (1); 125 126 return (0); 127 } 128 129 static void 130 mace_attach(struct device *parent, struct device *self, void *aux) 131 { 132 struct mace_softc *sc = (struct mace_softc *)self; 133 struct mainbus_attach_args *ma = aux; 134 u_int32_t scratch; 135 136 sc->iot = SGIMIPS_BUS_SPACE_MACE; 137 sc->dmat = &sgimips_default_bus_dma_tag; 138 139 if (bus_space_map(sc->iot, ma->ma_addr, 0, 140 BUS_SPACE_MAP_LINEAR, &sc->ioh)) 141 panic("mace_attach: could not allocate memory\n"); 142 143 #if 0 144 /* 145 * There's something deeply wrong with the alloc() routine -- it 146 * returns a pointer to memory that is used by the kernel i/o 147 * buffers. Disable for now. 148 */ 149 150 if ((bus_dmamem_alloc(sc->dmat, 32768, PAGE_SIZE, 32768, 151 &sc->seg, 1, &sc->nsegs, BUS_DMA_NOWAIT)) != 0) { 152 printf(": unable to allocate DMA memory\n"); 153 return; 154 } 155 156 if ((bus_dmamem_map(sc->dmat, &sc->seg, sc->nsegs, 32768, 157 (caddr_t *)&sc->isa_ringbuffer, BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) 158 != 0) { 159 printf(": unable to map control data\n"); 160 return; 161 } 162 163 if ((bus_dmamap_create(sc->dmat, 32768, 1, 32768, 0, 164 BUS_DMA_NOWAIT, &sc->map)) != 0) { 165 printf(": unable to create DMA map for control data\n"); 166 return; 167 } 168 169 if ((scratch = bus_dmamap_load(sc->dmat, sc->map, sc->isa_ringbuffer, 170 32768, NULL, BUS_DMA_NOWAIT)) != 0) { 171 printf(": unable to load DMA map for control data %i\n", 172 scratch); 173 } 174 175 memset(sc->isa_ringbuffer, 0, 32768); 176 177 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_RINGBASE, 178 MIPS_KSEG1_TO_PHYS(sc->isa_ringbuffer) & 0xffff8000); 179 180 aprint_normal(" isa ringbuffer 0x%x size 32k", 181 MIPS_KSEG1_TO_PHYS((unsigned long)sc->isa_ringbuffer)); 182 #endif 183 184 aprint_normal("\n"); 185 186 aprint_debug("%s: isa sts %llx\n", self->dv_xname, 187 bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS)); 188 aprint_debug("%s: isa msk %llx\n", self->dv_xname, 189 bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK)); 190 191 /* 192 * Turn on all ISA interrupts. These are actually masked and 193 * registered via the CRIME, as the MACE ISA interrupt mask is 194 * really whacky and nigh on impossible to map to a sane autoconfig 195 * scheme. 196 */ 197 198 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_MASK, 0xffffffff); 199 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_INT_STATUS, 0); 200 201 /* set up LED for solid green or blink, if that's your fancy */ 202 scratch = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); 203 scratch |= MACE_ISA_LED_RED; 204 scratch &= ~(MACE_ISA_LED_GREEN); 205 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, scratch); 206 207 #if defined(BLINK) 208 mace_blink(sc); 209 #endif 210 211 /* Initialize the maceintr elements to sane values */ 212 for (scratch = 0; scratch < MACE_NINTR; scratch++) { 213 maceintrtab[scratch].func = NULL; 214 maceintrtab[scratch].irq = 0; 215 } 216 217 config_search_ia(mace_search, self, "mace", NULL); 218 } 219 220 221 static int 222 mace_print(void *aux, const char *pnp) 223 { 224 struct mace_attach_args *maa = aux; 225 226 if (pnp != 0) 227 return QUIET; 228 229 if (maa->maa_offset != MACECF_OFFSET_DEFAULT) 230 aprint_normal(" offset 0x%lx", maa->maa_offset); 231 if (maa->maa_intr != MACECF_INTR_DEFAULT) 232 aprint_normal(" intr %d", maa->maa_intr); 233 if (maa->maa_offset != MACECF_INTRMASK_DEFAULT) 234 aprint_normal(" intrmask 0x%x", maa->maa_intrmask); 235 236 return UNCONF; 237 } 238 239 static int 240 mace_search(struct device *parent, struct cfdata *cf, 241 const int *ldesc, void *aux) 242 { 243 struct mace_softc *sc = (struct mace_softc *)parent; 244 struct mace_attach_args maa; 245 int tryagain; 246 247 do { 248 maa.maa_offset = cf->cf_loc[MACECF_OFFSET]; 249 maa.maa_intr = cf->cf_loc[MACECF_INTR]; 250 maa.maa_intrmask = cf->cf_loc[MACECF_INTRMASK]; 251 maa.maa_st = SGIMIPS_BUS_SPACE_MACE; 252 maa.maa_sh = sc->ioh; /* XXX */ 253 maa.maa_dmat = &sgimips_default_bus_dma_tag; 254 maa.isa_ringbuffer = sc->isa_ringbuffer; 255 256 tryagain = 0; 257 if (config_match(parent, cf, &maa) > 0) { 258 config_attach(parent, cf, &maa, mace_print); 259 tryagain = (cf->cf_fstate == FSTATE_STAR); 260 } 261 262 } while (tryagain); 263 264 return 0; 265 } 266 267 void * 268 mace_intr_establish(int intr, int level, int (*func)(void *), void *arg) 269 { 270 int i; 271 272 if (intr < 0 || intr >= 16) 273 panic("invalid interrupt number"); 274 275 for (i = 0; i < MACE_NINTR; i++) 276 if (maceintrtab[i].func == NULL) { 277 maceintrtab[i].func = func; 278 maceintrtab[i].arg = arg; 279 maceintrtab[i].irq = (1 << intr); 280 maceintrtab[i].intrmask = level; 281 snprintf(maceintrtab[i].evname, 282 sizeof(maceintrtab[i].evname), 283 "intr %d level 0x%x", intr, level); 284 evcnt_attach_dynamic(&maceintrtab[i].evcnt, 285 EVCNT_TYPE_INTR, NULL, 286 "mace", maceintrtab[i].evname); 287 break; 288 } 289 290 crime_intr_mask(intr); 291 aprint_debug("mace: established interrupt %d (level %x)\n", 292 intr, level); 293 return (void *)&maceintrtab[i]; 294 } 295 296 void 297 mace_intr_disestablish(void *cookie) 298 { 299 int intr = -1, level = 0, irq = 0, i; 300 301 for (i = 0; i < MACE_NINTR; i++) 302 if (&maceintrtab[i] == cookie) { 303 evcnt_detach(&maceintrtab[i].evcnt); 304 for (intr = 0; 305 maceintrtab[i].irq == (1 << intr); intr ++); 306 level = maceintrtab[i].intrmask; 307 irq = maceintrtab[i].irq; 308 309 maceintrtab[i].irq = 0; 310 maceintrtab[i].intrmask = 0; 311 maceintrtab[i].func = NULL; 312 maceintrtab[i].arg = NULL; 313 bzero(&maceintrtab[i].evcnt, sizeof (struct evcnt)); 314 bzero(&maceintrtab[i].evname, 315 sizeof (maceintrtab[i].evname)); 316 break; 317 } 318 if (intr == -1) 319 panic("mace: lost maceintrtab"); 320 321 /* do not do a unmask, when irq is being shared. */ 322 for (i = 0; i < MACE_NINTR; i++) 323 if (&maceintrtab[i].func != NULL && maceintrtab[i].irq == irq) 324 break; 325 if (i == MACE_NINTR) 326 crime_intr_unmask(intr); 327 aprint_debug("mace: disestablished interrupt %d (level %x)\n", 328 intr, level); 329 } 330 331 void 332 mace_intr(int irqs) 333 { 334 u_int64_t isa_irq, isa_mask; 335 int i; 336 337 /* irq 4 is the ISA cascade interrupt. Must handle with care. */ 338 if (irqs & (1 << 4)) { 339 isa_mask = mips3_ld((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE 340 + MACE_ISA_INT_MASK)); 341 isa_irq = mips3_ld((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE 342 + MACE_ISA_INT_STATUS)); 343 for (i = 0; i < MACE_NINTR; i++) { 344 if ((maceintrtab[i].irq == (1 << 4)) && 345 (isa_irq & maceintrtab[i].intrmask)) { 346 (maceintrtab[i].func)(maceintrtab[i].arg); 347 maceintrtab[i].evcnt.ev_count++; 348 } 349 } 350 #if 0 351 mips3_sd((u_int64_t *)MIPS_PHYS_TO_KSEG1(MACE_BASE 352 + MACE_ISA_INT_STATUS), isa_mask); 353 #endif 354 irqs &= ~(1 << 4); 355 } 356 357 for (i = 0; i < MACE_NINTR; i++) 358 if ((irqs & maceintrtab[i].irq)) { 359 (maceintrtab[i].func)(maceintrtab[i].arg); 360 maceintrtab[i].evcnt.ev_count++; 361 } 362 } 363 364 #if defined(BLINK) 365 static void 366 mace_blink(void *self) 367 { 368 struct mace_softc *sc = (struct mace_softc *) self; 369 register int s; 370 int value; 371 372 s = splhigh(); 373 value = bus_space_read_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG); 374 value ^= MACE_ISA_LED_GREEN; 375 bus_space_write_8(sc->iot, sc->ioh, MACE_ISA_FLASH_NIC_REG, value); 376 splx(s); 377 /* 378 * Blink rate is: 379 * full cycle every second if completely idle (loadav = 0) 380 * full cycle every 2 seconds if loadav = 1 381 * full cycle every 3 seconds if loadav = 2 382 * etc. 383 */ 384 s = (((averunnable.ldavg[0] + FSCALE) * hz) >> (FSHIFT + 1)); 385 callout_reset(&mace_blink_ch, s, mace_blink, sc); 386 387 } 388 #endif 389
Indexes created Sun Sep 28 16:09:52 GMT 2025