scif.c revision 1.33 1 1.33 jdolecek /* $NetBSD: scif.c,v 1.33 2002/10/23 09:11:56 jdolecek Exp $ */
2 1.1 itojun
3 1.1 itojun /*-
4 1.1 itojun * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved.
5 1.1 itojun *
6 1.1 itojun * Redistribution and use in source and binary forms, with or without
7 1.1 itojun * modification, are permitted provided that the following conditions
8 1.1 itojun * are met:
9 1.1 itojun * 1. Redistributions of source code must retain the above copyright
10 1.1 itojun * notice, this list of conditions and the following disclaimer.
11 1.1 itojun * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 itojun * notice, this list of conditions and the following disclaimer in the
13 1.1 itojun * documentation and/or other materials provided with the distribution.
14 1.1 itojun * 3. The name of the author may not be used to endorse or promote products
15 1.1 itojun * derived from this software without specific prior written permission.
16 1.1 itojun *
17 1.1 itojun * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 1.1 itojun * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 1.1 itojun * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 1.1 itojun * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 1.1 itojun * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 1.1 itojun * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 1.1 itojun * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 1.1 itojun * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 1.1 itojun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 1.1 itojun * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 1.1 itojun */
28 1.1 itojun
29 1.2 msaitoh /*-
30 1.2 msaitoh * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
31 1.2 msaitoh * All rights reserved.
32 1.2 msaitoh *
33 1.2 msaitoh * This code is derived from software contributed to The NetBSD Foundation
34 1.2 msaitoh * by Charles M. Hannum.
35 1.2 msaitoh *
36 1.2 msaitoh * Redistribution and use in source and binary forms, with or without
37 1.2 msaitoh * modification, are permitted provided that the following conditions
38 1.2 msaitoh * are met:
39 1.2 msaitoh * 1. Redistributions of source code must retain the above copyright
40 1.2 msaitoh * notice, this list of conditions and the following disclaimer.
41 1.2 msaitoh * 2. Redistributions in binary form must reproduce the above copyright
42 1.2 msaitoh * notice, this list of conditions and the following disclaimer in the
43 1.2 msaitoh * documentation and/or other materials provided with the distribution.
44 1.2 msaitoh * 3. All advertising materials mentioning features or use of this software
45 1.2 msaitoh * must display the following acknowledgement:
46 1.2 msaitoh * This product includes software developed by the NetBSD
47 1.2 msaitoh * Foundation, Inc. and its contributors.
48 1.2 msaitoh * 4. Neither the name of The NetBSD Foundation nor the names of its
49 1.2 msaitoh * contributors may be used to endorse or promote products derived
50 1.2 msaitoh * from this software without specific prior written permission.
51 1.2 msaitoh *
52 1.2 msaitoh * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
53 1.2 msaitoh * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
54 1.2 msaitoh * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
55 1.2 msaitoh * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
56 1.2 msaitoh * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
57 1.2 msaitoh * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
58 1.2 msaitoh * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
59 1.2 msaitoh * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
60 1.2 msaitoh * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
61 1.2 msaitoh * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
62 1.2 msaitoh * POSSIBILITY OF SUCH DAMAGE.
63 1.2 msaitoh */
64 1.2 msaitoh
65 1.2 msaitoh /*
66 1.2 msaitoh * Copyright (c) 1991 The Regents of the University of California.
67 1.2 msaitoh * All rights reserved.
68 1.2 msaitoh *
69 1.2 msaitoh * Redistribution and use in source and binary forms, with or without
70 1.2 msaitoh * modification, are permitted provided that the following conditions
71 1.2 msaitoh * are met:
72 1.2 msaitoh * 1. Redistributions of source code must retain the above copyright
73 1.2 msaitoh * notice, this list of conditions and the following disclaimer.
74 1.2 msaitoh * 2. Redistributions in binary form must reproduce the above copyright
75 1.2 msaitoh * notice, this list of conditions and the following disclaimer in the
76 1.2 msaitoh * documentation and/or other materials provided with the distribution.
77 1.2 msaitoh * 3. All advertising materials mentioning features or use of this software
78 1.2 msaitoh * must display the following acknowledgement:
79 1.2 msaitoh * This product includes software developed by the University of
80 1.2 msaitoh * California, Berkeley and its contributors.
81 1.2 msaitoh * 4. Neither the name of the University nor the names of its contributors
82 1.2 msaitoh * may be used to endorse or promote products derived from this software
83 1.2 msaitoh * without specific prior written permission.
84 1.2 msaitoh *
85 1.2 msaitoh * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
86 1.2 msaitoh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
87 1.2 msaitoh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
88 1.2 msaitoh * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
89 1.2 msaitoh * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
90 1.2 msaitoh * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
91 1.2 msaitoh * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
92 1.2 msaitoh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
93 1.2 msaitoh * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
94 1.2 msaitoh * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
95 1.2 msaitoh * SUCH DAMAGE.
96 1.2 msaitoh *
97 1.2 msaitoh * @(#)com.c 7.5 (Berkeley) 5/16/91
98 1.2 msaitoh */
99 1.2 msaitoh
100 1.2 msaitoh /*
101 1.2 msaitoh * SH internal serial driver
102 1.2 msaitoh *
103 1.2 msaitoh * This code is derived from both z8530tty.c and com.c
104 1.2 msaitoh */
105 1.2 msaitoh
106 1.17 lukem #include "opt_kgdb.h"
107 1.1 itojun #include "opt_scif.h"
108 1.1 itojun
109 1.1 itojun #include <sys/param.h>
110 1.1 itojun #include <sys/systm.h>
111 1.1 itojun #include <sys/tty.h>
112 1.1 itojun #include <sys/proc.h>
113 1.1 itojun #include <sys/conf.h>
114 1.1 itojun #include <sys/file.h>
115 1.1 itojun #include <sys/syslog.h>
116 1.1 itojun #include <sys/kernel.h>
117 1.1 itojun #include <sys/device.h>
118 1.1 itojun #include <sys/malloc.h>
119 1.22 uch #include <sys/kgdb.h>
120 1.1 itojun
121 1.1 itojun #include <dev/cons.h>
122 1.1 itojun
123 1.21 uch #include <sh3/clock.h>
124 1.24 uch #include <sh3/exception.h>
125 1.1 itojun #include <sh3/scifreg.h>
126 1.24 uch #include <machine/intr.h>
127 1.24 uch
128 1.22 uch #include <sh3/dev/scifvar.h>
129 1.1 itojun
130 1.24 uch #include "locators.h"
131 1.1 itojun
132 1.20 uch static void scifstart(struct tty *);
133 1.20 uch static int scifparam(struct tty *, struct termios *);
134 1.22 uch static int kgdb_attached;
135 1.1 itojun
136 1.20 uch void scifcnprobe(struct consdev *);
137 1.20 uch void scifcninit(struct consdev *);
138 1.20 uch void scifcnputc(dev_t, int);
139 1.20 uch int scifcngetc(dev_t);
140 1.20 uch void scifcnpoolc(dev_t, int);
141 1.20 uch void scif_intr_init(void);
142 1.20 uch int scifintr(void *);
143 1.1 itojun
144 1.1 itojun struct scif_softc {
145 1.1 itojun struct device sc_dev; /* boilerplate */
146 1.1 itojun struct tty *sc_tty;
147 1.24 uch void *sc_si;
148 1.1 itojun
149 1.8 thorpej struct callout sc_diag_ch;
150 1.8 thorpej
151 1.1 itojun #if 0
152 1.1 itojun bus_space_tag_t sc_iot; /* ISA i/o space identifier */
153 1.1 itojun bus_space_handle_t sc_ioh; /* ISA io handle */
154 1.1 itojun
155 1.1 itojun int sc_drq;
156 1.1 itojun
157 1.1 itojun int sc_frequency;
158 1.1 itojun #endif
159 1.1 itojun
160 1.1 itojun u_int sc_overflows,
161 1.1 itojun sc_floods,
162 1.1 itojun sc_errors; /* number of retries so far */
163 1.1 itojun u_char sc_status[7]; /* copy of registers */
164 1.1 itojun
165 1.1 itojun int sc_hwflags;
166 1.1 itojun int sc_swflags;
167 1.1 itojun u_int sc_fifolen;
168 1.1 itojun
169 1.1 itojun u_int sc_r_hiwat,
170 1.1 itojun sc_r_lowat;
171 1.1 itojun u_char *volatile sc_rbget,
172 1.1 itojun *volatile sc_rbput;
173 1.1 itojun volatile u_int sc_rbavail;
174 1.1 itojun u_char *sc_rbuf,
175 1.1 itojun *sc_ebuf;
176 1.1 itojun
177 1.1 itojun u_char *sc_tba; /* transmit buffer address */
178 1.1 itojun u_int sc_tbc, /* transmit byte count */
179 1.1 itojun sc_heldtbc;
180 1.1 itojun
181 1.1 itojun volatile u_char sc_rx_flags,
182 1.1 itojun #define RX_TTY_BLOCKED 0x01
183 1.1 itojun #define RX_TTY_OVERFLOWED 0x02
184 1.1 itojun #define RX_IBUF_BLOCKED 0x04
185 1.1 itojun #define RX_IBUF_OVERFLOWED 0x08
186 1.1 itojun #define RX_ANY_BLOCK 0x0f
187 1.3 msaitoh sc_tx_busy, /* working on an output chunk */
188 1.3 msaitoh sc_tx_done, /* done with one output chunk */
189 1.2 msaitoh sc_tx_stopped, /* H/W level stop (lost CTS) */
190 1.2 msaitoh sc_st_check, /* got a status interrupt */
191 1.1 itojun sc_rx_ready;
192 1.1 itojun
193 1.1 itojun volatile u_char sc_heldchange;
194 1.1 itojun };
195 1.1 itojun
196 1.1 itojun /* controller driver configuration */
197 1.20 uch static int scif_match(struct device *, struct cfdata *, void *);
198 1.20 uch static void scif_attach(struct device *, struct device *, void *);
199 1.1 itojun
200 1.20 uch void scif_break(struct scif_softc *, int);
201 1.20 uch void scif_iflush(struct scif_softc *);
202 1.1 itojun
203 1.1 itojun #define integrate static inline
204 1.15 thorpej #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
205 1.20 uch void scifsoft(void *);
206 1.1 itojun #else
207 1.1 itojun #ifndef __NO_SOFT_SERIAL_INTERRUPT
208 1.20 uch void scifsoft(void);
209 1.1 itojun #else
210 1.20 uch void scifsoft(void *);
211 1.1 itojun #endif
212 1.1 itojun #endif
213 1.20 uch integrate void scif_rxsoft(struct scif_softc *, struct tty *);
214 1.20 uch integrate void scif_txsoft(struct scif_softc *, struct tty *);
215 1.20 uch integrate void scif_stsoft(struct scif_softc *, struct tty *);
216 1.20 uch integrate void scif_schedrx(struct scif_softc *);
217 1.20 uch void scifdiag(void *);
218 1.1 itojun
219 1.1 itojun
220 1.1 itojun #define SCIFUNIT_MASK 0x7ffff
221 1.1 itojun #define SCIFDIALOUT_MASK 0x80000
222 1.1 itojun
223 1.1 itojun #define SCIFUNIT(x) (minor(x) & SCIFUNIT_MASK)
224 1.1 itojun #define SCIFDIALOUT(x) (minor(x) & SCIFDIALOUT_MASK)
225 1.1 itojun
226 1.1 itojun /* Macros to clear/set/test flags. */
227 1.25 uch #define SET(t, f) (t) |= (f)
228 1.25 uch #define CLR(t, f) (t) &= ~(f)
229 1.25 uch #define ISSET(t, f) ((t) & (f))
230 1.1 itojun
231 1.1 itojun /* Hardware flag masks */
232 1.1 itojun #define SCIF_HW_NOIEN 0x01
233 1.1 itojun #define SCIF_HW_FIFO 0x02
234 1.1 itojun #define SCIF_HW_FLOW 0x08
235 1.1 itojun #define SCIF_HW_DEV_OK 0x20
236 1.1 itojun #define SCIF_HW_CONSOLE 0x40
237 1.1 itojun #define SCIF_HW_KGDB 0x80
238 1.1 itojun
239 1.1 itojun /* Buffer size for character buffer */
240 1.1 itojun #define SCIF_RING_SIZE 2048
241 1.1 itojun
242 1.1 itojun /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */
243 1.1 itojun u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4;
244 1.1 itojun u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4;
245 1.1 itojun
246 1.25 uch #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
247 1.1 itojun int scifconscflag = CONMODE;
248 1.9 msaitoh int scifisconsole = 0;
249 1.1 itojun
250 1.7 msaitoh #ifdef SCIFCN_SPEED
251 1.7 msaitoh unsigned int scifcn_speed = SCIFCN_SPEED;
252 1.7 msaitoh #else
253 1.7 msaitoh unsigned int scifcn_speed = 9600;
254 1.7 msaitoh #endif
255 1.7 msaitoh
256 1.1 itojun #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */
257 1.1 itojun
258 1.15 thorpej #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
259 1.1 itojun #ifdef __NO_SOFT_SERIAL_INTERRUPT
260 1.1 itojun volatile int scif_softintr_scheduled;
261 1.8 thorpej struct callout scif_soft_ch = CALLOUT_INITIALIZER;
262 1.1 itojun #endif
263 1.1 itojun #endif
264 1.1 itojun
265 1.1 itojun u_int scif_rbuf_size = SCIF_RING_SIZE;
266 1.1 itojun
267 1.31 thorpej CFATTACH_DECL(scif, sizeof(struct scif_softc),
268 1.32 thorpej scif_match, scif_attach, NULL, NULL);
269 1.1 itojun
270 1.1 itojun extern struct cfdriver scif_cd;
271 1.1 itojun
272 1.28 gehenna dev_type_open(scifopen);
273 1.28 gehenna dev_type_close(scifclose);
274 1.28 gehenna dev_type_read(scifread);
275 1.28 gehenna dev_type_write(scifwrite);
276 1.28 gehenna dev_type_ioctl(scifioctl);
277 1.28 gehenna dev_type_stop(scifstop);
278 1.28 gehenna dev_type_tty(sciftty);
279 1.28 gehenna dev_type_poll(scifpoll);
280 1.28 gehenna
281 1.28 gehenna const struct cdevsw scif_cdevsw = {
282 1.28 gehenna scifopen, scifclose, scifread, scifwrite, scifioctl,
283 1.33 jdolecek scifstop, sciftty, scifpoll, nommap, ttykqfilter, D_TTY
284 1.28 gehenna };
285 1.1 itojun
286 1.20 uch void InitializeScif (unsigned int);
287 1.1 itojun
288 1.1 itojun /*
289 1.1 itojun * following functions are debugging prupose only
290 1.1 itojun */
291 1.25 uch #define CR 0x0D
292 1.25 uch #define USART_ON (unsigned int)~0x08
293 1.1 itojun
294 1.20 uch void scif_putc(unsigned char);
295 1.20 uch unsigned char scif_getc(void);
296 1.20 uch int ScifErrCheck(void);
297 1.1 itojun
298 1.1 itojun /*
299 1.1 itojun * InitializeScif
300 1.1 itojun * : unsigned int bps;
301 1.1 itojun * : SCIF(Serial Communication Interface)
302 1.1 itojun */
303 1.1 itojun
304 1.1 itojun void
305 1.20 uch InitializeScif(unsigned int bps)
306 1.1 itojun {
307 1.1 itojun
308 1.1 itojun /* Initialize SCR */
309 1.3 msaitoh SHREG_SCSCR2 = 0x00;
310 1.1 itojun
311 1.6 msaitoh #if 0
312 1.6 msaitoh SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE;
313 1.6 msaitoh #else
314 1.1 itojun SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST;
315 1.6 msaitoh #endif
316 1.7 msaitoh /* Serial Mode Register */
317 1.3 msaitoh SHREG_SCSMR2 = 0x00; /* 8bit,NonParity,Even,1Stop */
318 1.1 itojun
319 1.7 msaitoh /* Bit Rate Register */
320 1.21 uch SHREG_SCBRR2 = divrnd(sh_clock_get_pclock(), 32 * bps) - 1;
321 1.1 itojun
322 1.7 msaitoh /*
323 1.7 msaitoh * wait 1mSec, because Send/Recv must begin 1 bit period after
324 1.7 msaitoh * BRR is set.
325 1.7 msaitoh */
326 1.21 uch delay(1000);
327 1.1 itojun
328 1.6 msaitoh #if 0
329 1.6 msaitoh SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE;
330 1.6 msaitoh #else
331 1.1 itojun SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1;
332 1.6 msaitoh #endif
333 1.1 itojun
334 1.18 wiz /* Send permission, Receive permission ON */
335 1.3 msaitoh SHREG_SCSCR2 = SCSCR2_TE | SCSCR2_RE;
336 1.1 itojun
337 1.7 msaitoh /* Serial Status Register */
338 1.3 msaitoh SHREG_SCSSR2 &= SCSSR2_TDFE; /* Clear Status */
339 1.1 itojun }
340 1.1 itojun
341 1.1 itojun
342 1.1 itojun /*
343 1.14 msaitoh * scif_putc
344 1.1 itojun * : unsigned char c;
345 1.1 itojun */
346 1.1 itojun
347 1.1 itojun void
348 1.20 uch scif_putc(unsigned char c)
349 1.1 itojun {
350 1.14 msaitoh
351 1.1 itojun /* wait for ready */
352 1.1 itojun while ((SHREG_SCFDR2 & SCFDR2_TXCNT) == SCFDR2_TXF_FULL)
353 1.1 itojun ;
354 1.1 itojun
355 1.1 itojun /* write send data to send register */
356 1.1 itojun SHREG_SCFTDR2 = c;
357 1.1 itojun
358 1.1 itojun /* clear ready flag */
359 1.1 itojun SHREG_SCSSR2 &= ~(SCSSR2_TDFE | SCSSR2_TEND);
360 1.1 itojun }
361 1.1 itojun
362 1.1 itojun /*
363 1.1 itojun * : ScifErrCheck
364 1.1 itojun * 0x80 = error
365 1.1 itojun * 0x08 = frame error
366 1.1 itojun * 0x04 = parity error
367 1.1 itojun */
368 1.1 itojun int
369 1.1 itojun ScifErrCheck(void)
370 1.1 itojun {
371 1.1 itojun
372 1.1 itojun return(SHREG_SCSSR2 & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER));
373 1.1 itojun }
374 1.1 itojun
375 1.1 itojun /*
376 1.14 msaitoh * scif_getc
377 1.1 itojun */
378 1.1 itojun unsigned char
379 1.14 msaitoh scif_getc(void)
380 1.1 itojun {
381 1.1 itojun unsigned char c, err_c;
382 1.26 msaitoh #ifdef SH4
383 1.26 msaitoh unsigned short err_c2;
384 1.26 msaitoh #endif
385 1.1 itojun
386 1.12 msaitoh while (1) {
387 1.12 msaitoh /* wait for ready */
388 1.12 msaitoh while ((SHREG_SCFDR2 & SCFDR2_RECVCNT) == 0)
389 1.12 msaitoh ;
390 1.1 itojun
391 1.12 msaitoh c = SHREG_SCFRDR2;
392 1.12 msaitoh err_c = SHREG_SCSSR2;
393 1.12 msaitoh SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF
394 1.12 msaitoh | SCSSR2_DR);
395 1.26 msaitoh #ifdef SH4
396 1.26 msaitoh if (CPU_IS_SH4) {
397 1.26 msaitoh err_c2 = SHREG_SCLSR2;
398 1.26 msaitoh SHREG_SCLSR2 &= ~SCLSR2_ORER;
399 1.26 msaitoh }
400 1.26 msaitoh #endif
401 1.12 msaitoh if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER
402 1.12 msaitoh | SCSSR2_PER)) == 0) {
403 1.26 msaitoh #ifdef SH4
404 1.26 msaitoh if (CPU_IS_SH4 && ((err_c2 & SCLSR2_ORER) == 0))
405 1.26 msaitoh #endif
406 1.12 msaitoh return(c);
407 1.12 msaitoh }
408 1.12 msaitoh }
409 1.1 itojun
410 1.1 itojun }
411 1.1 itojun
412 1.1 itojun #if 0
413 1.25 uch #define SCIF_MAX_UNITS 2
414 1.1 itojun #else
415 1.25 uch #define SCIF_MAX_UNITS 1
416 1.1 itojun #endif
417 1.1 itojun
418 1.1 itojun
419 1.1 itojun static int
420 1.20 uch scif_match(struct device *parent, struct cfdata *cfp, void *aux)
421 1.1 itojun {
422 1.1 itojun
423 1.29 thorpej if (strcmp(cfp->cf_name, "scif")
424 1.1 itojun || cfp->cf_unit >= SCIF_MAX_UNITS)
425 1.1 itojun return 0;
426 1.1 itojun
427 1.1 itojun return 1;
428 1.1 itojun }
429 1.1 itojun
430 1.1 itojun static void
431 1.20 uch scif_attach(struct device *parent, struct device *self, void *aux)
432 1.1 itojun {
433 1.1 itojun struct scif_softc *sc = (struct scif_softc *)self;
434 1.1 itojun struct tty *tp;
435 1.1 itojun
436 1.1 itojun sc->sc_hwflags = 0; /* XXX */
437 1.1 itojun sc->sc_swflags = 0; /* XXX */
438 1.1 itojun sc->sc_fifolen = 16;
439 1.1 itojun
440 1.22 uch if (scifisconsole || kgdb_attached) {
441 1.9 msaitoh /* InitializeScif(scifcn_speed); */
442 1.9 msaitoh SET(sc->sc_hwflags, SCIF_HW_CONSOLE);
443 1.9 msaitoh SET(sc->sc_swflags, TIOCFLAG_SOFTCAR);
444 1.22 uch if (kgdb_attached) {
445 1.22 uch SET(sc->sc_hwflags, SCIF_HW_KGDB);
446 1.22 uch printf("\n%s: kgdb\n", sc->sc_dev.dv_xname);
447 1.22 uch } else {
448 1.22 uch printf("\n%s: console\n", sc->sc_dev.dv_xname);
449 1.22 uch }
450 1.9 msaitoh } else {
451 1.9 msaitoh InitializeScif(9600);
452 1.9 msaitoh printf("\n");
453 1.9 msaitoh }
454 1.1 itojun
455 1.8 thorpej callout_init(&sc->sc_diag_ch);
456 1.24 uch #ifdef SH4
457 1.24 uch intc_intr_establish(SH4_INTEVT_SCIF_ERI, IST_LEVEL, IPL_SERIAL,
458 1.24 uch scifintr, sc);
459 1.24 uch intc_intr_establish(SH4_INTEVT_SCIF_RXI, IST_LEVEL, IPL_SERIAL,
460 1.24 uch scifintr, sc);
461 1.24 uch intc_intr_establish(SH4_INTEVT_SCIF_BRI, IST_LEVEL, IPL_SERIAL,
462 1.24 uch scifintr, sc);
463 1.24 uch intc_intr_establish(SH4_INTEVT_SCIF_TXI, IST_LEVEL, IPL_SERIAL,
464 1.24 uch scifintr, sc);
465 1.24 uch #else
466 1.24 uch intc_intr_establish(SH7709_INTEVT2_SCIF_ERI, IST_LEVEL, IPL_SERIAL,
467 1.24 uch scifintr, sc);
468 1.24 uch intc_intr_establish(SH7709_INTEVT2_SCIF_RXI, IST_LEVEL, IPL_SERIAL,
469 1.24 uch scifintr, sc);
470 1.24 uch intc_intr_establish(SH7709_INTEVT2_SCIF_BRI, IST_LEVEL, IPL_SERIAL,
471 1.24 uch scifintr, sc);
472 1.24 uch intc_intr_establish(SH7709_INTEVT2_SCIF_TXI, IST_LEVEL, IPL_SERIAL,
473 1.24 uch scifintr, sc);
474 1.24 uch #endif
475 1.8 thorpej
476 1.24 uch #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
477 1.24 uch sc->sc_si = softintr_establish(IPL_SOFTSERIAL, scifsoft, sc);
478 1.24 uch #endif
479 1.9 msaitoh SET(sc->sc_hwflags, SCIF_HW_DEV_OK);
480 1.1 itojun
481 1.1 itojun tp = ttymalloc();
482 1.1 itojun tp->t_oproc = scifstart;
483 1.1 itojun tp->t_param = scifparam;
484 1.1 itojun tp->t_hwiflow = NULL;
485 1.1 itojun
486 1.1 itojun sc->sc_tty = tp;
487 1.1 itojun sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT);
488 1.1 itojun if (sc->sc_rbuf == NULL) {
489 1.1 itojun printf("%s: unable to allocate ring buffer\n",
490 1.1 itojun sc->sc_dev.dv_xname);
491 1.1 itojun return;
492 1.1 itojun }
493 1.1 itojun sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1);
494 1.1 itojun
495 1.1 itojun tty_attach(tp);
496 1.1 itojun }
497 1.1 itojun
498 1.1 itojun /*
499 1.1 itojun * Start or restart transmission.
500 1.1 itojun */
501 1.1 itojun static void
502 1.20 uch scifstart(struct tty *tp)
503 1.1 itojun {
504 1.1 itojun struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
505 1.1 itojun int s;
506 1.1 itojun
507 1.1 itojun s = spltty();
508 1.1 itojun if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP))
509 1.1 itojun goto out;
510 1.1 itojun if (sc->sc_tx_stopped)
511 1.1 itojun goto out;
512 1.1 itojun
513 1.1 itojun if (tp->t_outq.c_cc <= tp->t_lowat) {
514 1.1 itojun if (ISSET(tp->t_state, TS_ASLEEP)) {
515 1.1 itojun CLR(tp->t_state, TS_ASLEEP);
516 1.1 itojun wakeup(&tp->t_outq);
517 1.1 itojun }
518 1.1 itojun selwakeup(&tp->t_wsel);
519 1.1 itojun if (tp->t_outq.c_cc == 0)
520 1.1 itojun goto out;
521 1.1 itojun }
522 1.1 itojun
523 1.1 itojun /* Grab the first contiguous region of buffer space. */
524 1.1 itojun {
525 1.1 itojun u_char *tba;
526 1.1 itojun int tbc;
527 1.1 itojun
528 1.1 itojun tba = tp->t_outq.c_cf;
529 1.1 itojun tbc = ndqb(&tp->t_outq, 0);
530 1.1 itojun
531 1.1 itojun (void)splserial();
532 1.1 itojun
533 1.1 itojun sc->sc_tba = tba;
534 1.1 itojun sc->sc_tbc = tbc;
535 1.1 itojun }
536 1.1 itojun
537 1.1 itojun SET(tp->t_state, TS_BUSY);
538 1.1 itojun sc->sc_tx_busy = 1;
539 1.1 itojun
540 1.1 itojun /* Enable transmit completion interrupts if necessary. */
541 1.1 itojun SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE;
542 1.1 itojun
543 1.1 itojun /* Output the first chunk of the contiguous buffer. */
544 1.1 itojun {
545 1.1 itojun int n;
546 1.1 itojun int max;
547 1.1 itojun int i;
548 1.1 itojun
549 1.1 itojun n = sc->sc_tbc;
550 1.1 itojun max = sc->sc_fifolen - ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8);
551 1.1 itojun if (n > max)
552 1.1 itojun n = max;
553 1.1 itojun
554 1.1 itojun for (i = 0; i < n; i++) {
555 1.14 msaitoh scif_putc(*(sc->sc_tba));
556 1.1 itojun sc->sc_tba++;
557 1.1 itojun }
558 1.1 itojun sc->sc_tbc -= n;
559 1.1 itojun }
560 1.1 itojun out:
561 1.1 itojun splx(s);
562 1.1 itojun return;
563 1.1 itojun }
564 1.1 itojun
565 1.1 itojun /*
566 1.1 itojun * Set SCIF tty parameters from termios.
567 1.1 itojun * XXX - Should just copy the whole termios after
568 1.1 itojun * making sure all the changes could be done.
569 1.1 itojun */
570 1.1 itojun static int
571 1.20 uch scifparam(struct tty *tp, struct termios *t)
572 1.1 itojun {
573 1.1 itojun struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
574 1.1 itojun int ospeed = t->c_ospeed;
575 1.1 itojun int s;
576 1.1 itojun
577 1.1 itojun if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
578 1.1 itojun return (EIO);
579 1.1 itojun
580 1.1 itojun /* Check requested parameters. */
581 1.1 itojun if (ospeed < 0)
582 1.1 itojun return (EINVAL);
583 1.1 itojun if (t->c_ispeed && t->c_ispeed != t->c_ospeed)
584 1.1 itojun return (EINVAL);
585 1.1 itojun
586 1.1 itojun /*
587 1.1 itojun * For the console, always force CLOCAL and !HUPCL, so that the port
588 1.1 itojun * is always active.
589 1.1 itojun */
590 1.1 itojun if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
591 1.1 itojun ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
592 1.1 itojun SET(t->c_cflag, CLOCAL);
593 1.1 itojun CLR(t->c_cflag, HUPCL);
594 1.1 itojun }
595 1.1 itojun
596 1.1 itojun /*
597 1.1 itojun * If there were no changes, don't do anything. This avoids dropping
598 1.1 itojun * input and improves performance when all we did was frob things like
599 1.1 itojun * VMIN and VTIME.
600 1.1 itojun */
601 1.1 itojun if (tp->t_ospeed == t->c_ospeed &&
602 1.1 itojun tp->t_cflag == t->c_cflag)
603 1.1 itojun return (0);
604 1.1 itojun
605 1.1 itojun #if 0
606 1.1 itojun /* XXX (msaitoh) */
607 1.1 itojun lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag);
608 1.1 itojun #endif
609 1.1 itojun
610 1.1 itojun s = splserial();
611 1.1 itojun
612 1.1 itojun /*
613 1.1 itojun * Set the flow control pins depending on the current flow control
614 1.1 itojun * mode.
615 1.1 itojun */
616 1.1 itojun if (ISSET(t->c_cflag, CRTSCTS)) {
617 1.1 itojun SHREG_SCFCR2 |= SCFCR2_MCE;
618 1.1 itojun } else {
619 1.1 itojun SHREG_SCFCR2 &= ~SCFCR2_MCE;
620 1.1 itojun }
621 1.1 itojun
622 1.21 uch SHREG_SCBRR2 = divrnd(sh_clock_get_pclock(), 32 * ospeed) -1;
623 1.1 itojun
624 1.1 itojun /*
625 1.1 itojun * Set the FIFO threshold based on the receive speed.
626 1.1 itojun *
627 1.1 itojun * * If it's a low speed, it's probably a mouse or some other
628 1.1 itojun * interactive device, so set the threshold low.
629 1.1 itojun * * If it's a high speed, trim the trigger level down to prevent
630 1.1 itojun * overflows.
631 1.1 itojun * * Otherwise set it a bit higher.
632 1.1 itojun */
633 1.1 itojun #if 0
634 1.1 itojun /* XXX (msaitoh) */
635 1.1 itojun if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP))
636 1.1 itojun sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8;
637 1.1 itojun else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO))
638 1.1 itojun sc->sc_fifo = FIFO_ENABLE |
639 1.1 itojun (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 :
640 1.1 itojun t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4);
641 1.1 itojun else
642 1.1 itojun sc->sc_fifo = 0;
643 1.1 itojun #endif
644 1.1 itojun
645 1.1 itojun /* And copy to tty. */
646 1.1 itojun tp->t_ispeed = 0;
647 1.1 itojun tp->t_ospeed = t->c_ospeed;
648 1.1 itojun tp->t_cflag = t->c_cflag;
649 1.1 itojun
650 1.1 itojun if (!sc->sc_heldchange) {
651 1.1 itojun if (sc->sc_tx_busy) {
652 1.1 itojun sc->sc_heldtbc = sc->sc_tbc;
653 1.1 itojun sc->sc_tbc = 0;
654 1.1 itojun sc->sc_heldchange = 1;
655 1.1 itojun }
656 1.1 itojun #if 0
657 1.1 itojun /* XXX (msaitoh) */
658 1.1 itojun else
659 1.1 itojun scif_loadchannelregs(sc);
660 1.1 itojun #endif
661 1.1 itojun }
662 1.1 itojun
663 1.1 itojun if (!ISSET(t->c_cflag, CHWFLOW)) {
664 1.1 itojun /* Disable the high water mark. */
665 1.1 itojun sc->sc_r_hiwat = 0;
666 1.1 itojun sc->sc_r_lowat = 0;
667 1.1 itojun if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) {
668 1.1 itojun CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
669 1.1 itojun scif_schedrx(sc);
670 1.1 itojun }
671 1.1 itojun } else {
672 1.1 itojun sc->sc_r_hiwat = scif_rbuf_hiwat;
673 1.1 itojun sc->sc_r_lowat = scif_rbuf_lowat;
674 1.1 itojun }
675 1.1 itojun
676 1.1 itojun splx(s);
677 1.1 itojun
678 1.1 itojun #ifdef SCIF_DEBUG
679 1.1 itojun if (scif_debug)
680 1.1 itojun scifstatus(sc, "scifparam ");
681 1.1 itojun #endif
682 1.1 itojun
683 1.1 itojun if (!ISSET(t->c_cflag, CHWFLOW)) {
684 1.1 itojun if (sc->sc_tx_stopped) {
685 1.1 itojun sc->sc_tx_stopped = 0;
686 1.1 itojun scifstart(tp);
687 1.1 itojun }
688 1.1 itojun }
689 1.1 itojun
690 1.1 itojun return (0);
691 1.1 itojun }
692 1.1 itojun
693 1.1 itojun void
694 1.20 uch scif_iflush(struct scif_softc *sc)
695 1.1 itojun {
696 1.1 itojun int i;
697 1.1 itojun unsigned char c;
698 1.1 itojun
699 1.1 itojun i = SHREG_SCFDR2 & SCFDR2_RECVCNT;
700 1.1 itojun
701 1.1 itojun while (i > 0) {
702 1.1 itojun c = SHREG_SCFRDR2;
703 1.1 itojun SHREG_SCSSR2 &= ~(SCSSR2_RDF | SCSSR2_DR);
704 1.1 itojun i--;
705 1.1 itojun }
706 1.1 itojun }
707 1.1 itojun
708 1.1 itojun int
709 1.20 uch scifopen(dev_t dev, int flag, int mode, struct proc *p)
710 1.1 itojun {
711 1.1 itojun int unit = SCIFUNIT(dev);
712 1.1 itojun struct scif_softc *sc;
713 1.1 itojun struct tty *tp;
714 1.1 itojun int s, s2;
715 1.1 itojun int error;
716 1.1 itojun
717 1.1 itojun if (unit >= scif_cd.cd_ndevs)
718 1.1 itojun return (ENXIO);
719 1.1 itojun sc = scif_cd.cd_devs[unit];
720 1.1 itojun if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) ||
721 1.1 itojun sc->sc_rbuf == NULL)
722 1.1 itojun return (ENXIO);
723 1.1 itojun
724 1.1 itojun if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
725 1.1 itojun return (ENXIO);
726 1.1 itojun
727 1.1 itojun #ifdef KGDB
728 1.1 itojun /*
729 1.1 itojun * If this is the kgdb port, no other use is permitted.
730 1.1 itojun */
731 1.1 itojun if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB))
732 1.1 itojun return (EBUSY);
733 1.22 uch #endif /* KGDB */
734 1.1 itojun
735 1.1 itojun tp = sc->sc_tty;
736 1.1 itojun
737 1.1 itojun if (ISSET(tp->t_state, TS_ISOPEN) &&
738 1.1 itojun ISSET(tp->t_state, TS_XCLUDE) &&
739 1.1 itojun p->p_ucred->cr_uid != 0)
740 1.1 itojun return (EBUSY);
741 1.1 itojun
742 1.1 itojun s = spltty();
743 1.1 itojun
744 1.1 itojun /*
745 1.1 itojun * Do the following iff this is a first open.
746 1.1 itojun */
747 1.1 itojun if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
748 1.1 itojun struct termios t;
749 1.1 itojun
750 1.1 itojun tp->t_dev = dev;
751 1.1 itojun
752 1.1 itojun s2 = splserial();
753 1.1 itojun
754 1.1 itojun /* Turn on interrupts. */
755 1.1 itojun SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE;
756 1.1 itojun
757 1.1 itojun splx(s2);
758 1.1 itojun
759 1.1 itojun /*
760 1.1 itojun * Initialize the termios status to the defaults. Add in the
761 1.1 itojun * sticky bits from TIOCSFLAGS.
762 1.1 itojun */
763 1.1 itojun t.c_ispeed = 0;
764 1.1 itojun if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
765 1.7 msaitoh t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */
766 1.1 itojun t.c_cflag = scifconscflag;
767 1.1 itojun } else {
768 1.1 itojun t.c_ospeed = TTYDEF_SPEED;
769 1.1 itojun t.c_cflag = TTYDEF_CFLAG;
770 1.1 itojun }
771 1.1 itojun if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL))
772 1.1 itojun SET(t.c_cflag, CLOCAL);
773 1.1 itojun if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS))
774 1.1 itojun SET(t.c_cflag, CRTSCTS);
775 1.1 itojun if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF))
776 1.1 itojun SET(t.c_cflag, MDMBUF);
777 1.1 itojun /* Make sure scifparam() will do something. */
778 1.1 itojun tp->t_ospeed = 0;
779 1.1 itojun (void) scifparam(tp, &t);
780 1.1 itojun tp->t_iflag = TTYDEF_IFLAG;
781 1.1 itojun tp->t_oflag = TTYDEF_OFLAG;
782 1.1 itojun tp->t_lflag = TTYDEF_LFLAG;
783 1.1 itojun ttychars(tp);
784 1.1 itojun ttsetwater(tp);
785 1.1 itojun
786 1.1 itojun s2 = splserial();
787 1.1 itojun
788 1.1 itojun /* Clear the input ring, and unblock. */
789 1.1 itojun sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf;
790 1.1 itojun sc->sc_rbavail = scif_rbuf_size;
791 1.1 itojun scif_iflush(sc);
792 1.1 itojun CLR(sc->sc_rx_flags, RX_ANY_BLOCK);
793 1.1 itojun #if 0
794 1.1 itojun /* XXX (msaitoh) */
795 1.1 itojun scif_hwiflow(sc);
796 1.1 itojun #endif
797 1.1 itojun
798 1.1 itojun #ifdef SCIF_DEBUG
799 1.1 itojun if (scif_debug)
800 1.1 itojun scifstatus(sc, "scifopen ");
801 1.1 itojun #endif
802 1.1 itojun
803 1.1 itojun splx(s2);
804 1.1 itojun }
805 1.1 itojun
806 1.1 itojun splx(s);
807 1.1 itojun
808 1.1 itojun error = ttyopen(tp, SCIFDIALOUT(dev), ISSET(flag, O_NONBLOCK));
809 1.1 itojun if (error)
810 1.1 itojun goto bad;
811 1.1 itojun
812 1.13 eeh error = (*tp->t_linesw->l_open)(dev, tp);
813 1.1 itojun if (error)
814 1.1 itojun goto bad;
815 1.1 itojun
816 1.1 itojun return (0);
817 1.1 itojun
818 1.1 itojun bad:
819 1.1 itojun
820 1.1 itojun return (error);
821 1.1 itojun }
822 1.1 itojun
823 1.1 itojun int
824 1.20 uch scifclose(dev_t dev, int flag, int mode, struct proc *p)
825 1.1 itojun {
826 1.1 itojun struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
827 1.1 itojun struct tty *tp = sc->sc_tty;
828 1.1 itojun
829 1.1 itojun /* XXX This is for cons.c. */
830 1.1 itojun if (!ISSET(tp->t_state, TS_ISOPEN))
831 1.1 itojun return (0);
832 1.1 itojun
833 1.13 eeh (*tp->t_linesw->l_close)(tp, flag);
834 1.1 itojun ttyclose(tp);
835 1.1 itojun
836 1.1 itojun if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
837 1.1 itojun return (0);
838 1.1 itojun
839 1.1 itojun return (0);
840 1.1 itojun }
841 1.1 itojun
842 1.1 itojun int
843 1.20 uch scifread(dev_t dev, struct uio *uio, int flag)
844 1.1 itojun {
845 1.1 itojun struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
846 1.1 itojun struct tty *tp = sc->sc_tty;
847 1.1 itojun
848 1.13 eeh return ((*tp->t_linesw->l_read)(tp, uio, flag));
849 1.1 itojun }
850 1.1 itojun
851 1.1 itojun int
852 1.20 uch scifwrite(dev_t dev, struct uio *uio, int flag)
853 1.1 itojun {
854 1.1 itojun struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
855 1.1 itojun struct tty *tp = sc->sc_tty;
856 1.1 itojun
857 1.13 eeh return ((*tp->t_linesw->l_write)(tp, uio, flag));
858 1.16 scw }
859 1.16 scw
860 1.16 scw int
861 1.20 uch scifpoll(dev_t dev, int events, struct proc *p)
862 1.16 scw {
863 1.16 scw struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
864 1.16 scw struct tty *tp = sc->sc_tty;
865 1.25 uch
866 1.16 scw return ((*tp->t_linesw->l_poll)(tp, events, p));
867 1.1 itojun }
868 1.1 itojun
869 1.1 itojun struct tty *
870 1.20 uch sciftty(dev_t dev)
871 1.1 itojun {
872 1.1 itojun struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
873 1.1 itojun struct tty *tp = sc->sc_tty;
874 1.1 itojun
875 1.1 itojun return (tp);
876 1.1 itojun }
877 1.1 itojun
878 1.1 itojun int
879 1.20 uch scifioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
880 1.1 itojun {
881 1.1 itojun struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
882 1.1 itojun struct tty *tp = sc->sc_tty;
883 1.1 itojun int error;
884 1.1 itojun int s;
885 1.1 itojun
886 1.1 itojun if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
887 1.1 itojun return (EIO);
888 1.1 itojun
889 1.13 eeh error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p);
890 1.23 atatat if (error != EPASSTHROUGH)
891 1.1 itojun return (error);
892 1.1 itojun
893 1.1 itojun error = ttioctl(tp, cmd, data, flag, p);
894 1.23 atatat if (error != EPASSTHROUGH)
895 1.1 itojun return (error);
896 1.1 itojun
897 1.1 itojun error = 0;
898 1.1 itojun
899 1.1 itojun s = splserial();
900 1.1 itojun
901 1.1 itojun switch (cmd) {
902 1.1 itojun case TIOCSBRK:
903 1.1 itojun scif_break(sc, 1);
904 1.1 itojun break;
905 1.1 itojun
906 1.1 itojun case TIOCCBRK:
907 1.1 itojun scif_break(sc, 0);
908 1.1 itojun break;
909 1.6 msaitoh
910 1.1 itojun case TIOCGFLAGS:
911 1.1 itojun *(int *)data = sc->sc_swflags;
912 1.1 itojun break;
913 1.1 itojun
914 1.1 itojun case TIOCSFLAGS:
915 1.1 itojun error = suser(p->p_ucred, &p->p_acflag);
916 1.1 itojun if (error)
917 1.1 itojun break;
918 1.1 itojun sc->sc_swflags = *(int *)data;
919 1.1 itojun break;
920 1.1 itojun
921 1.1 itojun default:
922 1.23 atatat error = EPASSTHROUGH;
923 1.1 itojun break;
924 1.1 itojun }
925 1.1 itojun
926 1.1 itojun splx(s);
927 1.1 itojun
928 1.1 itojun return (error);
929 1.1 itojun }
930 1.1 itojun
931 1.1 itojun integrate void
932 1.20 uch scif_schedrx(struct scif_softc *sc)
933 1.1 itojun {
934 1.1 itojun
935 1.1 itojun sc->sc_rx_ready = 1;
936 1.1 itojun
937 1.1 itojun /* Wake up the poller. */
938 1.15 thorpej #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
939 1.1 itojun softintr_schedule(sc->sc_si);
940 1.1 itojun #else
941 1.1 itojun #ifndef __NO_SOFT_SERIAL_INTERRUPT
942 1.1 itojun setsoftserial();
943 1.1 itojun #else
944 1.1 itojun if (!scif_softintr_scheduled) {
945 1.1 itojun scif_softintr_scheduled = 1;
946 1.8 thorpej callout_reset(&scif_soft_ch, 1, scifsoft, NULL);
947 1.1 itojun }
948 1.1 itojun #endif
949 1.1 itojun #endif
950 1.1 itojun }
951 1.1 itojun
952 1.6 msaitoh void
953 1.20 uch scif_break(struct scif_softc *sc, int onoff)
954 1.6 msaitoh {
955 1.6 msaitoh
956 1.6 msaitoh if (onoff)
957 1.6 msaitoh SHREG_SCSSR2 &= ~SCSSR2_TDFE;
958 1.6 msaitoh else
959 1.6 msaitoh SHREG_SCSSR2 |= SCSSR2_TDFE;
960 1.6 msaitoh
961 1.6 msaitoh #if 0 /* XXX */
962 1.6 msaitoh if (!sc->sc_heldchange) {
963 1.6 msaitoh if (sc->sc_tx_busy) {
964 1.6 msaitoh sc->sc_heldtbc = sc->sc_tbc;
965 1.6 msaitoh sc->sc_tbc = 0;
966 1.6 msaitoh sc->sc_heldchange = 1;
967 1.6 msaitoh } else
968 1.6 msaitoh scif_loadchannelregs(sc);
969 1.6 msaitoh }
970 1.6 msaitoh #endif
971 1.6 msaitoh }
972 1.6 msaitoh
973 1.1 itojun /*
974 1.1 itojun * Stop output, e.g., for ^S or output flush.
975 1.1 itojun */
976 1.1 itojun void
977 1.20 uch scifstop(struct tty *tp, int flag)
978 1.1 itojun {
979 1.1 itojun struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
980 1.1 itojun int s;
981 1.1 itojun
982 1.1 itojun s = splserial();
983 1.1 itojun if (ISSET(tp->t_state, TS_BUSY)) {
984 1.1 itojun /* Stop transmitting at the next chunk. */
985 1.1 itojun sc->sc_tbc = 0;
986 1.1 itojun sc->sc_heldtbc = 0;
987 1.1 itojun if (!ISSET(tp->t_state, TS_TTSTOP))
988 1.1 itojun SET(tp->t_state, TS_FLUSH);
989 1.1 itojun }
990 1.1 itojun splx(s);
991 1.1 itojun }
992 1.1 itojun
993 1.1 itojun void
994 1.1 itojun scif_intr_init()
995 1.1 itojun {
996 1.1 itojun /* XXX */
997 1.1 itojun }
998 1.1 itojun
999 1.1 itojun void
1000 1.20 uch scifdiag(void *arg)
1001 1.1 itojun {
1002 1.1 itojun struct scif_softc *sc = arg;
1003 1.1 itojun int overflows, floods;
1004 1.1 itojun int s;
1005 1.1 itojun
1006 1.1 itojun s = splserial();
1007 1.1 itojun overflows = sc->sc_overflows;
1008 1.1 itojun sc->sc_overflows = 0;
1009 1.1 itojun floods = sc->sc_floods;
1010 1.1 itojun sc->sc_floods = 0;
1011 1.1 itojun sc->sc_errors = 0;
1012 1.1 itojun splx(s);
1013 1.1 itojun
1014 1.1 itojun log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n",
1015 1.1 itojun sc->sc_dev.dv_xname,
1016 1.1 itojun overflows, overflows == 1 ? "" : "s",
1017 1.1 itojun floods, floods == 1 ? "" : "s");
1018 1.1 itojun }
1019 1.1 itojun
1020 1.1 itojun integrate void
1021 1.20 uch scif_rxsoft(struct scif_softc *sc, struct tty *tp)
1022 1.1 itojun {
1023 1.20 uch int (*rint)(int c, struct tty *tp) = tp->t_linesw->l_rint;
1024 1.1 itojun u_char *get, *end;
1025 1.1 itojun u_int cc, scc;
1026 1.1 itojun u_char ssr2;
1027 1.1 itojun int code;
1028 1.1 itojun int s;
1029 1.1 itojun
1030 1.1 itojun end = sc->sc_ebuf;
1031 1.1 itojun get = sc->sc_rbget;
1032 1.1 itojun scc = cc = scif_rbuf_size - sc->sc_rbavail;
1033 1.1 itojun
1034 1.1 itojun if (cc == scif_rbuf_size) {
1035 1.1 itojun sc->sc_floods++;
1036 1.1 itojun if (sc->sc_errors++ == 0)
1037 1.11 msaitoh callout_reset(&sc->sc_diag_ch, 60 * hz, scifdiag, sc);
1038 1.1 itojun }
1039 1.1 itojun
1040 1.1 itojun while (cc) {
1041 1.1 itojun code = get[0];
1042 1.1 itojun ssr2 = get[1];
1043 1.6 msaitoh if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) {
1044 1.6 msaitoh if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER))
1045 1.1 itojun SET(code, TTY_FE);
1046 1.1 itojun if (ISSET(ssr2, SCSSR2_PER))
1047 1.1 itojun SET(code, TTY_PE);
1048 1.1 itojun }
1049 1.1 itojun if ((*rint)(code, tp) == -1) {
1050 1.1 itojun /*
1051 1.1 itojun * The line discipline's buffer is out of space.
1052 1.1 itojun */
1053 1.1 itojun if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
1054 1.1 itojun /*
1055 1.1 itojun * We're either not using flow control, or the
1056 1.1 itojun * line discipline didn't tell us to block for
1057 1.1 itojun * some reason. Either way, we have no way to
1058 1.1 itojun * know when there's more space available, so
1059 1.1 itojun * just drop the rest of the data.
1060 1.1 itojun */
1061 1.1 itojun get += cc << 1;
1062 1.1 itojun if (get >= end)
1063 1.1 itojun get -= scif_rbuf_size << 1;
1064 1.1 itojun cc = 0;
1065 1.1 itojun } else {
1066 1.1 itojun /*
1067 1.1 itojun * Don't schedule any more receive processing
1068 1.1 itojun * until the line discipline tells us there's
1069 1.1 itojun * space available (through scifhwiflow()).
1070 1.1 itojun * Leave the rest of the data in the input
1071 1.1 itojun * buffer.
1072 1.1 itojun */
1073 1.1 itojun SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
1074 1.1 itojun }
1075 1.1 itojun break;
1076 1.1 itojun }
1077 1.1 itojun get += 2;
1078 1.1 itojun if (get >= end)
1079 1.1 itojun get = sc->sc_rbuf;
1080 1.1 itojun cc--;
1081 1.1 itojun }
1082 1.1 itojun
1083 1.1 itojun if (cc != scc) {
1084 1.1 itojun sc->sc_rbget = get;
1085 1.1 itojun s = splserial();
1086 1.1 itojun cc = sc->sc_rbavail += scc - cc;
1087 1.1 itojun /* Buffers should be ok again, release possible block. */
1088 1.1 itojun if (cc >= sc->sc_r_lowat) {
1089 1.1 itojun if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
1090 1.1 itojun CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
1091 1.1 itojun SHREG_SCSCR2 |= SCSCR2_RIE;
1092 1.1 itojun }
1093 1.1 itojun #if 0
1094 1.1 itojun if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) {
1095 1.1 itojun CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED);
1096 1.1 itojun scif_hwiflow(sc);
1097 1.1 itojun }
1098 1.1 itojun #endif
1099 1.1 itojun }
1100 1.1 itojun splx(s);
1101 1.1 itojun }
1102 1.1 itojun }
1103 1.1 itojun
1104 1.1 itojun integrate void
1105 1.20 uch scif_txsoft(struct scif_softc *sc, struct tty *tp)
1106 1.1 itojun {
1107 1.1 itojun
1108 1.1 itojun CLR(tp->t_state, TS_BUSY);
1109 1.1 itojun if (ISSET(tp->t_state, TS_FLUSH))
1110 1.1 itojun CLR(tp->t_state, TS_FLUSH);
1111 1.1 itojun else
1112 1.1 itojun ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf));
1113 1.13 eeh (*tp->t_linesw->l_start)(tp);
1114 1.1 itojun }
1115 1.1 itojun
1116 1.1 itojun integrate void
1117 1.20 uch scif_stsoft(struct scif_softc *sc, struct tty *tp)
1118 1.1 itojun {
1119 1.1 itojun #if 0
1120 1.1 itojun /* XXX (msaitoh) */
1121 1.1 itojun u_char msr, delta;
1122 1.1 itojun int s;
1123 1.1 itojun
1124 1.1 itojun s = splserial();
1125 1.1 itojun msr = sc->sc_msr;
1126 1.1 itojun delta = sc->sc_msr_delta;
1127 1.1 itojun sc->sc_msr_delta = 0;
1128 1.1 itojun splx(s);
1129 1.1 itojun
1130 1.1 itojun if (ISSET(delta, sc->sc_msr_dcd)) {
1131 1.1 itojun /*
1132 1.1 itojun * Inform the tty layer that carrier detect changed.
1133 1.1 itojun */
1134 1.13 eeh (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD));
1135 1.1 itojun }
1136 1.1 itojun
1137 1.1 itojun if (ISSET(delta, sc->sc_msr_cts)) {
1138 1.1 itojun /* Block or unblock output according to flow control. */
1139 1.1 itojun if (ISSET(msr, sc->sc_msr_cts)) {
1140 1.1 itojun sc->sc_tx_stopped = 0;
1141 1.13 eeh (*tp->t_linesw->l_start)(tp);
1142 1.1 itojun } else {
1143 1.1 itojun sc->sc_tx_stopped = 1;
1144 1.1 itojun }
1145 1.1 itojun }
1146 1.1 itojun
1147 1.1 itojun #ifdef SCIF_DEBUG
1148 1.1 itojun if (scif_debug)
1149 1.1 itojun scifstatus(sc, "scif_stsoft");
1150 1.1 itojun #endif
1151 1.1 itojun #endif
1152 1.1 itojun }
1153 1.1 itojun
1154 1.15 thorpej #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
1155 1.1 itojun void
1156 1.20 uch scifsoft(void *arg)
1157 1.1 itojun {
1158 1.1 itojun struct scif_softc *sc = arg;
1159 1.1 itojun struct tty *tp;
1160 1.1 itojun
1161 1.1 itojun if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
1162 1.1 itojun return;
1163 1.1 itojun
1164 1.1 itojun {
1165 1.1 itojun #else
1166 1.1 itojun void
1167 1.1 itojun #ifndef __NO_SOFT_SERIAL_INTERRUPT
1168 1.1 itojun scifsoft()
1169 1.1 itojun #else
1170 1.20 uch scifsoft(void *arg)
1171 1.1 itojun #endif
1172 1.1 itojun {
1173 1.1 itojun struct scif_softc *sc;
1174 1.1 itojun struct tty *tp;
1175 1.1 itojun int unit;
1176 1.1 itojun #ifdef __NO_SOFT_SERIAL_INTERRUPT
1177 1.1 itojun int s;
1178 1.1 itojun
1179 1.1 itojun s = splsoftserial();
1180 1.1 itojun scif_softintr_scheduled = 0;
1181 1.1 itojun #endif
1182 1.1 itojun
1183 1.1 itojun for (unit = 0; unit < scif_cd.cd_ndevs; unit++) {
1184 1.1 itojun sc = scif_cd.cd_devs[unit];
1185 1.1 itojun if (sc == NULL || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK))
1186 1.1 itojun continue;
1187 1.1 itojun
1188 1.1 itojun if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
1189 1.1 itojun continue;
1190 1.1 itojun
1191 1.1 itojun tp = sc->sc_tty;
1192 1.1 itojun if (tp == NULL)
1193 1.1 itojun continue;
1194 1.1 itojun if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0)
1195 1.1 itojun continue;
1196 1.1 itojun #endif
1197 1.1 itojun tp = sc->sc_tty;
1198 1.1 itojun
1199 1.1 itojun if (sc->sc_rx_ready) {
1200 1.1 itojun sc->sc_rx_ready = 0;
1201 1.1 itojun scif_rxsoft(sc, tp);
1202 1.1 itojun }
1203 1.1 itojun
1204 1.1 itojun #if 0
1205 1.1 itojun if (sc->sc_st_check) {
1206 1.1 itojun sc->sc_st_check = 0;
1207 1.1 itojun scif_stsoft(sc, tp);
1208 1.1 itojun }
1209 1.1 itojun #endif
1210 1.1 itojun
1211 1.1 itojun if (sc->sc_tx_done) {
1212 1.1 itojun sc->sc_tx_done = 0;
1213 1.1 itojun scif_txsoft(sc, tp);
1214 1.1 itojun }
1215 1.1 itojun }
1216 1.1 itojun
1217 1.15 thorpej #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
1218 1.1 itojun #ifdef __NO_SOFT_SERIAL_INTERRUPT
1219 1.1 itojun splx(s);
1220 1.1 itojun #endif
1221 1.1 itojun #endif
1222 1.1 itojun }
1223 1.1 itojun
1224 1.1 itojun int
1225 1.20 uch scifintr(void *arg)
1226 1.1 itojun {
1227 1.1 itojun struct scif_softc *sc = arg;
1228 1.1 itojun u_char *put, *end;
1229 1.1 itojun u_int cc;
1230 1.1 itojun u_short ssr2;
1231 1.1 itojun int count;
1232 1.1 itojun
1233 1.1 itojun if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
1234 1.1 itojun return (0);
1235 1.1 itojun
1236 1.1 itojun end = sc->sc_ebuf;
1237 1.1 itojun put = sc->sc_rbput;
1238 1.1 itojun cc = sc->sc_rbavail;
1239 1.1 itojun
1240 1.26 msaitoh do {
1241 1.26 msaitoh ssr2 = SHREG_SCSSR2;
1242 1.26 msaitoh if (ISSET(ssr2, SCSSR2_BRK)) {
1243 1.26 msaitoh SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR);
1244 1.1 itojun #ifdef DDB
1245 1.26 msaitoh if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
1246 1.26 msaitoh console_debugger();
1247 1.26 msaitoh }
1248 1.22 uch #endif /* DDB */
1249 1.1 itojun #ifdef KGDB
1250 1.26 msaitoh if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) {
1251 1.26 msaitoh kgdb_connect(1);
1252 1.26 msaitoh }
1253 1.22 uch #endif /* KGDB */
1254 1.1 itojun }
1255 1.26 msaitoh count = SHREG_SCFDR2 & SCFDR2_RECVCNT;
1256 1.26 msaitoh if (count != 0) {
1257 1.26 msaitoh while (1) {
1258 1.26 msaitoh u_char c = SHREG_SCFRDR2;
1259 1.26 msaitoh u_char err = (u_char)(SHREG_SCSSR2 & 0x00ff);
1260 1.1 itojun
1261 1.26 msaitoh SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR);
1262 1.26 msaitoh #ifdef SH4
1263 1.26 msaitoh if (CPU_IS_SH4)
1264 1.26 msaitoh SHREG_SCLSR2 &= ~SCLSR2_ORER;
1265 1.26 msaitoh #endif
1266 1.26 msaitoh if ((cc > 0) && (count > 0)) {
1267 1.26 msaitoh put[0] = c;
1268 1.26 msaitoh put[1] = err;
1269 1.26 msaitoh put += 2;
1270 1.26 msaitoh if (put >= end)
1271 1.26 msaitoh put = sc->sc_rbuf;
1272 1.26 msaitoh cc--;
1273 1.26 msaitoh count--;
1274 1.26 msaitoh } else
1275 1.26 msaitoh break;
1276 1.26 msaitoh }
1277 1.26 msaitoh
1278 1.26 msaitoh /*
1279 1.26 msaitoh * Current string of incoming characters ended because
1280 1.26 msaitoh * no more data was available or we ran out of space.
1281 1.26 msaitoh * Schedule a receive event if any data was received.
1282 1.26 msaitoh * If we're out of space, turn off receive interrupts.
1283 1.26 msaitoh */
1284 1.26 msaitoh sc->sc_rbput = put;
1285 1.26 msaitoh sc->sc_rbavail = cc;
1286 1.26 msaitoh if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
1287 1.26 msaitoh sc->sc_rx_ready = 1;
1288 1.1 itojun
1289 1.26 msaitoh /*
1290 1.26 msaitoh * See if we are in danger of overflowing a buffer. If
1291 1.26 msaitoh * so, use hardware flow control to ease the pressure.
1292 1.26 msaitoh */
1293 1.26 msaitoh if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
1294 1.26 msaitoh cc < sc->sc_r_hiwat) {
1295 1.26 msaitoh SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
1296 1.1 itojun #if 0
1297 1.26 msaitoh scif_hwiflow(sc);
1298 1.1 itojun #endif
1299 1.26 msaitoh }
1300 1.1 itojun
1301 1.26 msaitoh /*
1302 1.26 msaitoh * If we're out of space, disable receive interrupts
1303 1.26 msaitoh * until the queue has drained a bit.
1304 1.26 msaitoh */
1305 1.26 msaitoh if (!cc) {
1306 1.26 msaitoh SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
1307 1.26 msaitoh SHREG_SCSCR2 &= ~SCSCR2_RIE;
1308 1.26 msaitoh }
1309 1.26 msaitoh } else {
1310 1.26 msaitoh if (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR)) {
1311 1.26 msaitoh SHREG_SCSCR2 &= ~(SCSCR2_TIE | SCSCR2_RIE);
1312 1.26 msaitoh delay(10);
1313 1.26 msaitoh SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE;
1314 1.26 msaitoh continue;
1315 1.26 msaitoh }
1316 1.7 msaitoh }
1317 1.26 msaitoh } while (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR));
1318 1.1 itojun
1319 1.1 itojun #if 0
1320 1.7 msaitoh msr = bus_space_read_1(iot, ioh, scif_msr);
1321 1.7 msaitoh delta = msr ^ sc->sc_msr;
1322 1.7 msaitoh sc->sc_msr = msr;
1323 1.7 msaitoh if (ISSET(delta, sc->sc_msr_mask)) {
1324 1.7 msaitoh SET(sc->sc_msr_delta, delta);
1325 1.1 itojun
1326 1.7 msaitoh /*
1327 1.7 msaitoh * Pulse-per-second clock signal on edge of DCD?
1328 1.7 msaitoh */
1329 1.7 msaitoh if (ISSET(delta, sc->sc_ppsmask)) {
1330 1.7 msaitoh struct timeval tv;
1331 1.7 msaitoh if (ISSET(msr, sc->sc_ppsmask) ==
1332 1.7 msaitoh sc->sc_ppsassert) {
1333 1.7 msaitoh /* XXX nanotime() */
1334 1.7 msaitoh microtime(&tv);
1335 1.7 msaitoh TIMEVAL_TO_TIMESPEC(&tv,
1336 1.7 msaitoh &sc->ppsinfo.assert_timestamp);
1337 1.7 msaitoh if (sc->ppsparam.mode & PPS_OFFSETASSERT) {
1338 1.7 msaitoh timespecadd(&sc->ppsinfo.assert_timestamp,
1339 1.1 itojun &sc->ppsparam.assert_offset,
1340 1.1 itojun &sc->ppsinfo.assert_timestamp);
1341 1.7 msaitoh TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp);
1342 1.7 msaitoh }
1343 1.1 itojun
1344 1.1 itojun #ifdef PPS_SYNC
1345 1.7 msaitoh if (sc->ppsparam.mode & PPS_HARDPPSONASSERT)
1346 1.7 msaitoh hardpps(&tv, tv.tv_usec);
1347 1.1 itojun #endif
1348 1.7 msaitoh sc->ppsinfo.assert_sequence++;
1349 1.7 msaitoh sc->ppsinfo.current_mode =
1350 1.7 msaitoh sc->ppsparam.mode;
1351 1.7 msaitoh
1352 1.7 msaitoh } else if (ISSET(msr, sc->sc_ppsmask) ==
1353 1.7 msaitoh sc->sc_ppsclear) {
1354 1.7 msaitoh /* XXX nanotime() */
1355 1.7 msaitoh microtime(&tv);
1356 1.7 msaitoh TIMEVAL_TO_TIMESPEC(&tv,
1357 1.7 msaitoh &sc->ppsinfo.clear_timestamp);
1358 1.7 msaitoh if (sc->ppsparam.mode & PPS_OFFSETCLEAR) {
1359 1.7 msaitoh timespecadd(&sc->ppsinfo.clear_timestamp,
1360 1.1 itojun &sc->ppsparam.clear_offset,
1361 1.1 itojun &sc->ppsinfo.clear_timestamp);
1362 1.7 msaitoh TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp);
1363 1.7 msaitoh }
1364 1.1 itojun
1365 1.1 itojun #ifdef PPS_SYNC
1366 1.7 msaitoh if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR)
1367 1.7 msaitoh hardpps(&tv, tv.tv_usec);
1368 1.1 itojun #endif
1369 1.7 msaitoh sc->ppsinfo.clear_sequence++;
1370 1.7 msaitoh sc->ppsinfo.current_mode =
1371 1.7 msaitoh sc->ppsparam.mode;
1372 1.1 itojun }
1373 1.7 msaitoh }
1374 1.1 itojun
1375 1.7 msaitoh /*
1376 1.7 msaitoh * Stop output immediately if we lose the output
1377 1.7 msaitoh * flow control signal or carrier detect.
1378 1.7 msaitoh */
1379 1.7 msaitoh if (ISSET(~msr, sc->sc_msr_mask)) {
1380 1.7 msaitoh sc->sc_tbc = 0;
1381 1.7 msaitoh sc->sc_heldtbc = 0;
1382 1.1 itojun #ifdef SCIF_DEBUG
1383 1.7 msaitoh if (scif_debug)
1384 1.7 msaitoh scifstatus(sc, "scifintr ");
1385 1.1 itojun #endif
1386 1.7 msaitoh }
1387 1.1 itojun
1388 1.7 msaitoh sc->sc_st_check = 1;
1389 1.7 msaitoh }
1390 1.1 itojun #endif
1391 1.1 itojun
1392 1.1 itojun /*
1393 1.1 itojun * Done handling any receive interrupts. See if data can be
1394 1.1 itojun * transmitted as well. Schedule tx done event if no data left
1395 1.1 itojun * and tty was marked busy.
1396 1.1 itojun */
1397 1.7 msaitoh if (((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */
1398 1.1 itojun /*
1399 1.1 itojun * If we've delayed a parameter change, do it now, and restart
1400 1.1 itojun * output.
1401 1.1 itojun */
1402 1.1 itojun if (sc->sc_heldchange) {
1403 1.1 itojun sc->sc_heldchange = 0;
1404 1.1 itojun sc->sc_tbc = sc->sc_heldtbc;
1405 1.1 itojun sc->sc_heldtbc = 0;
1406 1.1 itojun }
1407 1.1 itojun
1408 1.1 itojun /* Output the next chunk of the contiguous buffer, if any. */
1409 1.1 itojun if (sc->sc_tbc > 0) {
1410 1.1 itojun int n;
1411 1.1 itojun int max;
1412 1.1 itojun int i;
1413 1.1 itojun
1414 1.1 itojun n = sc->sc_tbc;
1415 1.1 itojun max = sc->sc_fifolen -
1416 1.1 itojun ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8);
1417 1.1 itojun if (n > max)
1418 1.1 itojun n = max;
1419 1.1 itojun
1420 1.1 itojun for (i = 0; i < n; i++) {
1421 1.14 msaitoh scif_putc(*(sc->sc_tba));
1422 1.1 itojun sc->sc_tba++;
1423 1.1 itojun }
1424 1.1 itojun sc->sc_tbc -= n;
1425 1.1 itojun } else {
1426 1.1 itojun /* Disable transmit completion interrupts if necessary. */
1427 1.1 itojun #if 0
1428 1.1 itojun if (ISSET(sc->sc_ier, IER_ETXRDY))
1429 1.1 itojun #endif
1430 1.1 itojun SHREG_SCSCR2 &= ~SCSCR2_TIE;
1431 1.1 itojun
1432 1.1 itojun if (sc->sc_tx_busy) {
1433 1.1 itojun sc->sc_tx_busy = 0;
1434 1.1 itojun sc->sc_tx_done = 1;
1435 1.1 itojun }
1436 1.1 itojun }
1437 1.1 itojun }
1438 1.1 itojun
1439 1.1 itojun /* Wake up the poller. */
1440 1.15 thorpej #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
1441 1.1 itojun softintr_schedule(sc->sc_si);
1442 1.1 itojun #else
1443 1.1 itojun #ifndef __NO_SOFT_SERIAL_INTERRUPT
1444 1.1 itojun setsoftserial();
1445 1.1 itojun #else
1446 1.1 itojun if (!scif_softintr_scheduled) {
1447 1.1 itojun scif_softintr_scheduled = 1;
1448 1.8 thorpej callout_reset(&scif_soft_ch, 1, scifsoft, NULL);
1449 1.1 itojun }
1450 1.1 itojun #endif
1451 1.1 itojun #endif
1452 1.1 itojun
1453 1.1 itojun #if NRND > 0 && defined(RND_SCIF)
1454 1.20 uch rnd_add_uint32(&sc->rnd_source, iir | lsr);
1455 1.1 itojun #endif
1456 1.1 itojun
1457 1.1 itojun return (1);
1458 1.1 itojun }
1459 1.1 itojun
1460 1.1 itojun void
1461 1.20 uch scifcnprobe(struct consdev *cp)
1462 1.1 itojun {
1463 1.1 itojun int maj;
1464 1.1 itojun
1465 1.1 itojun /* locate the major number */
1466 1.28 gehenna maj = cdevsw_lookup_major(&scif_cdevsw);
1467 1.1 itojun
1468 1.1 itojun /* Initialize required fields. */
1469 1.1 itojun cp->cn_dev = makedev(maj, 0);
1470 1.4 msaitoh #ifdef SCIFCONSOLE
1471 1.4 msaitoh cp->cn_pri = CN_REMOTE;
1472 1.4 msaitoh #else
1473 1.1 itojun cp->cn_pri = CN_NORMAL;
1474 1.1 itojun #endif
1475 1.1 itojun }
1476 1.1 itojun
1477 1.1 itojun void
1478 1.20 uch scifcninit(struct consdev *cp)
1479 1.1 itojun {
1480 1.1 itojun
1481 1.7 msaitoh InitializeScif(scifcn_speed);
1482 1.9 msaitoh scifisconsole = 1;
1483 1.1 itojun }
1484 1.1 itojun
1485 1.1 itojun int
1486 1.20 uch scifcngetc(dev_t dev)
1487 1.1 itojun {
1488 1.1 itojun int c;
1489 1.1 itojun int s;
1490 1.1 itojun
1491 1.1 itojun s = splserial();
1492 1.1 itojun c = scif_getc();
1493 1.1 itojun splx(s);
1494 1.1 itojun
1495 1.1 itojun return (c);
1496 1.1 itojun }
1497 1.1 itojun
1498 1.1 itojun void
1499 1.20 uch scifcnputc(dev_t dev, int c)
1500 1.1 itojun {
1501 1.1 itojun int s;
1502 1.1 itojun
1503 1.1 itojun s = splserial();
1504 1.14 msaitoh scif_putc((u_char)c);
1505 1.1 itojun splx(s);
1506 1.1 itojun }
1507 1.22 uch
1508 1.22 uch #ifdef KGDB
1509 1.22 uch int
1510 1.22 uch scif_kgdb_init()
1511 1.22 uch {
1512 1.22 uch
1513 1.22 uch if (strcmp(kgdb_devname, "scif") != 0)
1514 1.22 uch return (1);
1515 1.22 uch
1516 1.22 uch if (scifisconsole)
1517 1.22 uch return (1); /* can't share with console */
1518 1.22 uch
1519 1.22 uch InitializeScif(kgdb_rate);
1520 1.22 uch
1521 1.22 uch kgdb_attach((int (*)(void *))scifcngetc,
1522 1.22 uch (void (*)(void *, int))scifcnputc, NULL);
1523 1.22 uch kgdb_dev = 123; /* unneeded, only to satisfy some tests */
1524 1.22 uch kgdb_attached = 1;
1525 1.25 uch
1526 1.22 uch return (0);
1527 1.22 uch }
1528 1.22 uch #endif /* KGDB */
1529