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scif.c revision 1.37
      1  1.37       uwe /*	$NetBSD: scif.c,v 1.37 2004/10/19 02:12:21 uwe Exp $ */
      2   1.1    itojun 
      3   1.1    itojun /*-
      4   1.1    itojun  * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu.  All rights reserved.
      5   1.1    itojun  *
      6   1.1    itojun  * Redistribution and use in source and binary forms, with or without
      7   1.1    itojun  * modification, are permitted provided that the following conditions
      8   1.1    itojun  * are met:
      9   1.1    itojun  * 1. Redistributions of source code must retain the above copyright
     10   1.1    itojun  *    notice, this list of conditions and the following disclaimer.
     11   1.1    itojun  * 2. Redistributions in binary form must reproduce the above copyright
     12   1.1    itojun  *    notice, this list of conditions and the following disclaimer in the
     13   1.1    itojun  *    documentation and/or other materials provided with the distribution.
     14   1.1    itojun  * 3. The name of the author may not be used to endorse or promote products
     15   1.1    itojun  *    derived from this software without specific prior written permission.
     16   1.1    itojun  *
     17   1.1    itojun  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18   1.1    itojun  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19   1.1    itojun  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20   1.1    itojun  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21   1.1    itojun  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22   1.1    itojun  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23   1.1    itojun  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24   1.1    itojun  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25   1.1    itojun  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     26   1.1    itojun  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27   1.1    itojun  */
     28   1.1    itojun 
     29   1.2   msaitoh /*-
     30   1.2   msaitoh  * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
     31   1.2   msaitoh  * All rights reserved.
     32   1.2   msaitoh  *
     33   1.2   msaitoh  * This code is derived from software contributed to The NetBSD Foundation
     34   1.2   msaitoh  * by Charles M. Hannum.
     35   1.2   msaitoh  *
     36   1.2   msaitoh  * Redistribution and use in source and binary forms, with or without
     37   1.2   msaitoh  * modification, are permitted provided that the following conditions
     38   1.2   msaitoh  * are met:
     39   1.2   msaitoh  * 1. Redistributions of source code must retain the above copyright
     40   1.2   msaitoh  *    notice, this list of conditions and the following disclaimer.
     41   1.2   msaitoh  * 2. Redistributions in binary form must reproduce the above copyright
     42   1.2   msaitoh  *    notice, this list of conditions and the following disclaimer in the
     43   1.2   msaitoh  *    documentation and/or other materials provided with the distribution.
     44   1.2   msaitoh  * 3. All advertising materials mentioning features or use of this software
     45   1.2   msaitoh  *    must display the following acknowledgement:
     46   1.2   msaitoh  *        This product includes software developed by the NetBSD
     47   1.2   msaitoh  *        Foundation, Inc. and its contributors.
     48   1.2   msaitoh  * 4. Neither the name of The NetBSD Foundation nor the names of its
     49   1.2   msaitoh  *    contributors may be used to endorse or promote products derived
     50   1.2   msaitoh  *    from this software without specific prior written permission.
     51   1.2   msaitoh  *
     52   1.2   msaitoh  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     53   1.2   msaitoh  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     54   1.2   msaitoh  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     55   1.2   msaitoh  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     56   1.2   msaitoh  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     57   1.2   msaitoh  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     58   1.2   msaitoh  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     59   1.2   msaitoh  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     60   1.2   msaitoh  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     61   1.2   msaitoh  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     62   1.2   msaitoh  * POSSIBILITY OF SUCH DAMAGE.
     63   1.2   msaitoh  */
     64   1.2   msaitoh 
     65   1.2   msaitoh /*
     66   1.2   msaitoh  * Copyright (c) 1991 The Regents of the University of California.
     67   1.2   msaitoh  * All rights reserved.
     68   1.2   msaitoh  *
     69   1.2   msaitoh  * Redistribution and use in source and binary forms, with or without
     70   1.2   msaitoh  * modification, are permitted provided that the following conditions
     71   1.2   msaitoh  * are met:
     72   1.2   msaitoh  * 1. Redistributions of source code must retain the above copyright
     73   1.2   msaitoh  *    notice, this list of conditions and the following disclaimer.
     74   1.2   msaitoh  * 2. Redistributions in binary form must reproduce the above copyright
     75   1.2   msaitoh  *    notice, this list of conditions and the following disclaimer in the
     76   1.2   msaitoh  *    documentation and/or other materials provided with the distribution.
     77  1.35       agc  * 3. Neither the name of the University nor the names of its contributors
     78   1.2   msaitoh  *    may be used to endorse or promote products derived from this software
     79   1.2   msaitoh  *    without specific prior written permission.
     80   1.2   msaitoh  *
     81   1.2   msaitoh  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     82   1.2   msaitoh  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     83   1.2   msaitoh  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     84   1.2   msaitoh  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     85   1.2   msaitoh  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     86   1.2   msaitoh  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     87   1.2   msaitoh  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     88   1.2   msaitoh  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     89   1.2   msaitoh  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     90   1.2   msaitoh  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     91   1.2   msaitoh  * SUCH DAMAGE.
     92   1.2   msaitoh  *
     93   1.2   msaitoh  *	@(#)com.c	7.5 (Berkeley) 5/16/91
     94   1.2   msaitoh  */
     95   1.2   msaitoh 
     96   1.2   msaitoh /*
     97   1.2   msaitoh  * SH internal serial driver
     98   1.2   msaitoh  *
     99   1.2   msaitoh  * This code is derived from both z8530tty.c and com.c
    100   1.2   msaitoh  */
    101  1.34     lukem 
    102  1.34     lukem #include <sys/cdefs.h>
    103  1.37       uwe __KERNEL_RCSID(0, "$NetBSD: scif.c,v 1.37 2004/10/19 02:12:21 uwe Exp $");
    104   1.2   msaitoh 
    105  1.17     lukem #include "opt_kgdb.h"
    106   1.1    itojun #include "opt_scif.h"
    107   1.1    itojun 
    108   1.1    itojun #include <sys/param.h>
    109   1.1    itojun #include <sys/systm.h>
    110   1.1    itojun #include <sys/tty.h>
    111   1.1    itojun #include <sys/proc.h>
    112   1.1    itojun #include <sys/conf.h>
    113   1.1    itojun #include <sys/file.h>
    114   1.1    itojun #include <sys/syslog.h>
    115   1.1    itojun #include <sys/kernel.h>
    116   1.1    itojun #include <sys/device.h>
    117   1.1    itojun #include <sys/malloc.h>
    118  1.22       uch #include <sys/kgdb.h>
    119   1.1    itojun 
    120   1.1    itojun #include <dev/cons.h>
    121   1.1    itojun 
    122  1.21       uch #include <sh3/clock.h>
    123  1.24       uch #include <sh3/exception.h>
    124   1.1    itojun #include <sh3/scifreg.h>
    125  1.24       uch #include <machine/intr.h>
    126  1.24       uch 
    127  1.22       uch #include <sh3/dev/scifvar.h>
    128   1.1    itojun 
    129  1.24       uch #include "locators.h"
    130   1.1    itojun 
    131  1.20       uch static void	scifstart(struct tty *);
    132  1.20       uch static int	scifparam(struct tty *, struct termios *);
    133  1.22       uch static int kgdb_attached;
    134   1.1    itojun 
    135  1.20       uch void scifcnprobe(struct consdev *);
    136  1.20       uch void scifcninit(struct consdev *);
    137  1.20       uch void scifcnputc(dev_t, int);
    138  1.20       uch int scifcngetc(dev_t);
    139  1.20       uch void scifcnpoolc(dev_t, int);
    140  1.20       uch void scif_intr_init(void);
    141  1.20       uch int scifintr(void *);
    142   1.1    itojun 
    143   1.1    itojun struct scif_softc {
    144   1.1    itojun 	struct device sc_dev;		/* boilerplate */
    145   1.1    itojun 	struct tty *sc_tty;
    146  1.24       uch 	void *sc_si;
    147   1.1    itojun 
    148   1.8   thorpej 	struct callout sc_diag_ch;
    149   1.8   thorpej 
    150   1.1    itojun #if 0
    151   1.1    itojun 	bus_space_tag_t sc_iot;		/* ISA i/o space identifier */
    152   1.1    itojun 	bus_space_handle_t   sc_ioh;	/* ISA io handle */
    153   1.1    itojun 
    154   1.1    itojun 	int sc_drq;
    155   1.1    itojun 
    156   1.1    itojun 	int sc_frequency;
    157   1.1    itojun #endif
    158   1.1    itojun 
    159   1.1    itojun 	u_int sc_overflows,
    160   1.1    itojun 	      sc_floods,
    161   1.1    itojun 	      sc_errors;		/* number of retries so far */
    162   1.1    itojun 	u_char sc_status[7];		/* copy of registers */
    163   1.1    itojun 
    164   1.1    itojun 	int sc_hwflags;
    165   1.1    itojun 	int sc_swflags;
    166   1.1    itojun 	u_int sc_fifolen;
    167   1.1    itojun 
    168   1.1    itojun 	u_int sc_r_hiwat,
    169   1.1    itojun 	      sc_r_lowat;
    170   1.1    itojun 	u_char *volatile sc_rbget,
    171   1.1    itojun 	       *volatile sc_rbput;
    172   1.1    itojun  	volatile u_int sc_rbavail;
    173   1.1    itojun 	u_char *sc_rbuf,
    174   1.1    itojun 	       *sc_ebuf;
    175   1.1    itojun 
    176   1.1    itojun  	u_char *sc_tba;			/* transmit buffer address */
    177   1.1    itojun  	u_int sc_tbc,			/* transmit byte count */
    178   1.1    itojun 	      sc_heldtbc;
    179   1.1    itojun 
    180   1.1    itojun 	volatile u_char sc_rx_flags,
    181   1.1    itojun #define	RX_TTY_BLOCKED		0x01
    182   1.1    itojun #define	RX_TTY_OVERFLOWED	0x02
    183   1.1    itojun #define	RX_IBUF_BLOCKED		0x04
    184   1.1    itojun #define	RX_IBUF_OVERFLOWED	0x08
    185   1.1    itojun #define	RX_ANY_BLOCK		0x0f
    186   1.3   msaitoh 			sc_tx_busy,	/* working on an output chunk */
    187   1.3   msaitoh 			sc_tx_done,	/* done with one output chunk */
    188   1.2   msaitoh 			sc_tx_stopped,	/* H/W level stop (lost CTS) */
    189   1.2   msaitoh 			sc_st_check,	/* got a status interrupt */
    190   1.1    itojun 			sc_rx_ready;
    191   1.1    itojun 
    192   1.1    itojun 	volatile u_char sc_heldchange;
    193   1.1    itojun };
    194   1.1    itojun 
    195   1.1    itojun /* controller driver configuration */
    196  1.20       uch static int scif_match(struct device *, struct cfdata *, void *);
    197  1.20       uch static void scif_attach(struct device *, struct device *, void *);
    198   1.1    itojun 
    199  1.20       uch void	scif_break(struct scif_softc *, int);
    200  1.20       uch void	scif_iflush(struct scif_softc *);
    201   1.1    itojun 
    202   1.1    itojun #define	integrate	static inline
    203  1.15   thorpej #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
    204  1.20       uch void 	scifsoft(void *);
    205   1.1    itojun #else
    206   1.1    itojun #ifndef __NO_SOFT_SERIAL_INTERRUPT
    207  1.20       uch void 	scifsoft(void);
    208   1.1    itojun #else
    209  1.20       uch void 	scifsoft(void *);
    210   1.1    itojun #endif
    211   1.1    itojun #endif
    212  1.20       uch integrate void scif_rxsoft(struct scif_softc *, struct tty *);
    213  1.20       uch integrate void scif_txsoft(struct scif_softc *, struct tty *);
    214  1.20       uch integrate void scif_stsoft(struct scif_softc *, struct tty *);
    215  1.20       uch integrate void scif_schedrx(struct scif_softc *);
    216  1.20       uch void	scifdiag(void *);
    217   1.1    itojun 
    218   1.1    itojun 
    219   1.1    itojun #define	SCIFUNIT_MASK		0x7ffff
    220   1.1    itojun #define	SCIFDIALOUT_MASK	0x80000
    221   1.1    itojun 
    222   1.1    itojun #define	SCIFUNIT(x)	(minor(x) & SCIFUNIT_MASK)
    223   1.1    itojun #define	SCIFDIALOUT(x)	(minor(x) & SCIFDIALOUT_MASK)
    224   1.1    itojun 
    225   1.1    itojun /* Macros to clear/set/test flags. */
    226  1.25       uch #define	SET(t, f)	(t) |= (f)
    227  1.25       uch #define	CLR(t, f)	(t) &= ~(f)
    228  1.25       uch #define	ISSET(t, f)	((t) & (f))
    229   1.1    itojun 
    230   1.1    itojun /* Hardware flag masks */
    231   1.1    itojun #define	SCIF_HW_NOIEN	0x01
    232   1.1    itojun #define	SCIF_HW_FIFO	0x02
    233   1.1    itojun #define	SCIF_HW_FLOW	0x08
    234   1.1    itojun #define	SCIF_HW_DEV_OK	0x20
    235   1.1    itojun #define	SCIF_HW_CONSOLE	0x40
    236   1.1    itojun #define	SCIF_HW_KGDB	0x80
    237   1.1    itojun 
    238   1.1    itojun /* Buffer size for character buffer */
    239   1.1    itojun #define	SCIF_RING_SIZE	2048
    240   1.1    itojun 
    241   1.1    itojun /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */
    242   1.1    itojun u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4;
    243   1.1    itojun u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4;
    244   1.1    itojun 
    245  1.25       uch #define	CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
    246   1.1    itojun int scifconscflag = CONMODE;
    247   1.9   msaitoh int scifisconsole = 0;
    248   1.1    itojun 
    249   1.7   msaitoh #ifdef SCIFCN_SPEED
    250   1.7   msaitoh unsigned int scifcn_speed = SCIFCN_SPEED;
    251   1.7   msaitoh #else
    252   1.7   msaitoh unsigned int scifcn_speed = 9600;
    253   1.7   msaitoh #endif
    254   1.7   msaitoh 
    255   1.1    itojun #define	divrnd(n, q)	(((n)*2/(q)+1)/2)	/* divide and round off */
    256   1.1    itojun 
    257  1.15   thorpej #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
    258   1.1    itojun #ifdef __NO_SOFT_SERIAL_INTERRUPT
    259   1.1    itojun volatile int	scif_softintr_scheduled;
    260   1.8   thorpej struct callout scif_soft_ch = CALLOUT_INITIALIZER;
    261   1.1    itojun #endif
    262   1.1    itojun #endif
    263   1.1    itojun 
    264   1.1    itojun u_int scif_rbuf_size = SCIF_RING_SIZE;
    265   1.1    itojun 
    266  1.31   thorpej CFATTACH_DECL(scif, sizeof(struct scif_softc),
    267  1.32   thorpej     scif_match, scif_attach, NULL, NULL);
    268   1.1    itojun 
    269   1.1    itojun extern struct cfdriver scif_cd;
    270   1.1    itojun 
    271  1.28   gehenna dev_type_open(scifopen);
    272  1.28   gehenna dev_type_close(scifclose);
    273  1.28   gehenna dev_type_read(scifread);
    274  1.28   gehenna dev_type_write(scifwrite);
    275  1.28   gehenna dev_type_ioctl(scifioctl);
    276  1.28   gehenna dev_type_stop(scifstop);
    277  1.28   gehenna dev_type_tty(sciftty);
    278  1.28   gehenna dev_type_poll(scifpoll);
    279  1.28   gehenna 
    280  1.28   gehenna const struct cdevsw scif_cdevsw = {
    281  1.28   gehenna 	scifopen, scifclose, scifread, scifwrite, scifioctl,
    282  1.33  jdolecek 	scifstop, sciftty, scifpoll, nommap, ttykqfilter, D_TTY
    283  1.28   gehenna };
    284   1.1    itojun 
    285  1.20       uch void InitializeScif (unsigned int);
    286   1.1    itojun 
    287   1.1    itojun /*
    288   1.1    itojun  * following functions are debugging prupose only
    289   1.1    itojun  */
    290  1.25       uch #define	CR      0x0D
    291  1.25       uch #define	USART_ON (unsigned int)~0x08
    292   1.1    itojun 
    293  1.20       uch void scif_putc(unsigned char);
    294  1.20       uch unsigned char scif_getc(void);
    295  1.20       uch int ScifErrCheck(void);
    296   1.1    itojun 
    297  1.37       uwe 
    298  1.37       uwe /* XXX: uwe
    299  1.37       uwe  * Prepare for bus_spacification.  The difference in access widths is
    300  1.37       uwe  * still handled by the magic definitions in scifreg.h
    301  1.37       uwe  */
    302  1.37       uwe #define scif_smr_read()		SHREG_SCSMR2
    303  1.37       uwe #define scif_smr_write(v)	(SHREG_SCSMR2 = (v))
    304  1.37       uwe 
    305  1.37       uwe #define scif_brr_read()		SHREG_SCBRR2
    306  1.37       uwe #define scif_brr_write(v)	(SHREG_SCBRR2 = (v))
    307  1.37       uwe 
    308  1.37       uwe #define scif_scr_read()		SHREG_SCSCR2
    309  1.37       uwe #define scif_scr_write(v)	(SHREG_SCSCR2 = (v))
    310  1.37       uwe 
    311  1.37       uwe #define scif_ftdr_write(v)	(SHREG_SCFTDR2 = (v))
    312  1.37       uwe 
    313  1.37       uwe #define scif_ssr_read()		SHREG_SCSSR2
    314  1.37       uwe #define scif_ssr_write(v)	(SHREG_SCSSR2 = (v))
    315  1.37       uwe 
    316  1.37       uwe #define scif_frdr_read()	SHREG_SCFRDR2
    317  1.37       uwe 
    318  1.37       uwe #define scif_fcr_read()		SHREG_SCFCR2
    319  1.37       uwe #define scif_fcr_write(v)	(SHREG_SCFCR2 = (v))
    320  1.37       uwe 
    321  1.37       uwe #define scif_fdr_read()		SHREG_SCFDR2
    322  1.37       uwe 
    323  1.37       uwe #ifdef SH4 /* additional registers in sh4 */
    324  1.37       uwe 
    325  1.37       uwe #define scif_sptr_read()	SHREG_SCSPTR2
    326  1.37       uwe #define scif_sptr_write(v)	(SHREG_SCSPTR2 = (v))
    327  1.37       uwe 
    328  1.37       uwe #define scif_lsr_read()		SHREG_SCLSR2
    329  1.37       uwe #define scif_lsr_write(v)	(SHREG_SCLSR2 = (v))
    330  1.37       uwe 
    331  1.37       uwe #endif /* SH4 */
    332  1.37       uwe 
    333  1.37       uwe 
    334   1.1    itojun /*
    335   1.1    itojun  * InitializeScif
    336   1.1    itojun  * : unsigned int bps;
    337   1.1    itojun  * : SCIF(Serial Communication Interface)
    338   1.1    itojun  */
    339   1.1    itojun 
    340   1.1    itojun void
    341  1.20       uch InitializeScif(unsigned int bps)
    342   1.1    itojun {
    343   1.1    itojun 
    344   1.1    itojun 	/* Initialize SCR */
    345  1.37       uwe 	scif_scr_write(0x00);
    346   1.1    itojun 
    347   1.6   msaitoh #if 0
    348  1.37       uwe 	scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE);
    349   1.6   msaitoh #else
    350  1.37       uwe 	scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST);
    351   1.6   msaitoh #endif
    352   1.7   msaitoh 	/* Serial Mode Register */
    353  1.37       uwe 	scif_smr_write(0x00);	/* 8bit,NonParity,Even,1Stop */
    354   1.1    itojun 
    355   1.7   msaitoh 	/* Bit Rate Register */
    356  1.37       uwe 	scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * bps) - 1);
    357   1.1    itojun 
    358   1.7   msaitoh 	/*
    359   1.7   msaitoh 	 * wait 1mSec, because Send/Recv must begin 1 bit period after
    360   1.7   msaitoh 	 * BRR is set.
    361   1.7   msaitoh 	 */
    362  1.21       uch 	delay(1000);
    363   1.1    itojun 
    364   1.6   msaitoh #if 0
    365  1.37       uwe 	scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE);
    366   1.6   msaitoh #else
    367  1.37       uwe 	scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1);
    368   1.6   msaitoh #endif
    369   1.1    itojun 
    370  1.18       wiz 	/* Send permission, Receive permission ON */
    371  1.37       uwe 	scif_scr_write(SCSCR2_TE | SCSCR2_RE);
    372   1.1    itojun 
    373   1.7   msaitoh 	/* Serial Status Register */
    374  1.37       uwe 	scif_ssr_write(scif_ssr_read() & SCSSR2_TDFE); /* Clear Status */
    375   1.1    itojun }
    376   1.1    itojun 
    377   1.1    itojun 
    378   1.1    itojun /*
    379  1.14   msaitoh  * scif_putc
    380   1.1    itojun  *  : unsigned char c;
    381   1.1    itojun  */
    382   1.1    itojun 
    383   1.1    itojun void
    384  1.20       uch scif_putc(unsigned char c)
    385   1.1    itojun {
    386  1.14   msaitoh 
    387   1.1    itojun 	/* wait for ready */
    388  1.37       uwe 	while ((scif_fdr_read() & SCFDR2_TXCNT) == SCFDR2_TXF_FULL)
    389  1.36       uwe 		continue;
    390   1.1    itojun 
    391   1.1    itojun 	/* write send data to send register */
    392  1.37       uwe 	scif_ftdr_write(c);
    393   1.1    itojun 
    394   1.1    itojun 	/* clear ready flag */
    395  1.37       uwe 	scif_ssr_write(scif_ssr_read() & ~(SCSSR2_TDFE | SCSSR2_TEND));
    396   1.1    itojun }
    397   1.1    itojun 
    398   1.1    itojun /*
    399   1.1    itojun  * : ScifErrCheck
    400   1.1    itojun  *	0x80 = error
    401   1.1    itojun  *	0x08 = frame error
    402   1.1    itojun  *	0x04 = parity error
    403   1.1    itojun  */
    404   1.1    itojun int
    405   1.1    itojun ScifErrCheck(void)
    406   1.1    itojun {
    407   1.1    itojun 
    408  1.37       uwe 	return (scif_ssr_read() & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER));
    409   1.1    itojun }
    410   1.1    itojun 
    411   1.1    itojun /*
    412  1.14   msaitoh  * scif_getc
    413   1.1    itojun  */
    414   1.1    itojun unsigned char
    415  1.14   msaitoh scif_getc(void)
    416   1.1    itojun {
    417   1.1    itojun 	unsigned char c, err_c;
    418  1.26   msaitoh #ifdef SH4
    419  1.26   msaitoh 	unsigned short err_c2;
    420  1.26   msaitoh #endif
    421   1.1    itojun 
    422  1.36       uwe 	for (;;) {
    423  1.12   msaitoh 		/* wait for ready */
    424  1.37       uwe 		while ((scif_fdr_read() & SCFDR2_RECVCNT) == 0)
    425  1.36       uwe 			continue;
    426   1.1    itojun 
    427  1.37       uwe 		c = scif_frdr_read();
    428  1.37       uwe 		err_c = scif_ssr_read();
    429  1.37       uwe 		scif_ssr_write(scif_ssr_read()
    430  1.37       uwe 			& ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF | SCSSR2_DR));
    431  1.26   msaitoh #ifdef SH4
    432  1.26   msaitoh 		if (CPU_IS_SH4) {
    433  1.37       uwe 			err_c2 = scif_lsr_read();
    434  1.37       uwe 			scif_lsr_write(scif_lsr_read() & ~SCLSR2_ORER);
    435  1.26   msaitoh 		}
    436  1.26   msaitoh #endif
    437  1.12   msaitoh 		if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER
    438  1.12   msaitoh 		    | SCSSR2_PER)) == 0) {
    439  1.26   msaitoh #ifdef SH4
    440  1.26   msaitoh 			if (CPU_IS_SH4 && ((err_c2 & SCLSR2_ORER) == 0))
    441  1.26   msaitoh #endif
    442  1.12   msaitoh 			return(c);
    443  1.12   msaitoh 		}
    444  1.12   msaitoh 	}
    445   1.1    itojun 
    446   1.1    itojun }
    447   1.1    itojun 
    448   1.1    itojun #if 0
    449  1.25       uch #define	SCIF_MAX_UNITS 2
    450   1.1    itojun #else
    451  1.25       uch #define	SCIF_MAX_UNITS 1
    452   1.1    itojun #endif
    453   1.1    itojun 
    454   1.1    itojun 
    455   1.1    itojun static int
    456  1.20       uch scif_match(struct device *parent, struct cfdata *cfp, void *aux)
    457   1.1    itojun {
    458   1.1    itojun 
    459  1.29   thorpej 	if (strcmp(cfp->cf_name, "scif")
    460   1.1    itojun 	    || cfp->cf_unit >= SCIF_MAX_UNITS)
    461   1.1    itojun 		return 0;
    462   1.1    itojun 
    463   1.1    itojun 	return 1;
    464   1.1    itojun }
    465   1.1    itojun 
    466   1.1    itojun static void
    467  1.20       uch scif_attach(struct device *parent, struct device *self, void *aux)
    468   1.1    itojun {
    469   1.1    itojun 	struct scif_softc *sc = (struct scif_softc *)self;
    470   1.1    itojun 	struct tty *tp;
    471   1.1    itojun 
    472   1.1    itojun 	sc->sc_hwflags = 0;	/* XXX */
    473   1.1    itojun 	sc->sc_swflags = 0;	/* XXX */
    474   1.1    itojun 	sc->sc_fifolen = 16;
    475   1.1    itojun 
    476  1.22       uch 	if (scifisconsole || kgdb_attached) {
    477   1.9   msaitoh 		/* InitializeScif(scifcn_speed); */
    478   1.9   msaitoh 		SET(sc->sc_hwflags, SCIF_HW_CONSOLE);
    479   1.9   msaitoh 		SET(sc->sc_swflags, TIOCFLAG_SOFTCAR);
    480  1.22       uch 		if (kgdb_attached) {
    481  1.22       uch 			SET(sc->sc_hwflags, SCIF_HW_KGDB);
    482  1.22       uch 			printf("\n%s: kgdb\n", sc->sc_dev.dv_xname);
    483  1.22       uch 		} else {
    484  1.22       uch 			printf("\n%s: console\n", sc->sc_dev.dv_xname);
    485  1.22       uch 		}
    486   1.9   msaitoh 	} else {
    487   1.9   msaitoh 		InitializeScif(9600);
    488   1.9   msaitoh 		printf("\n");
    489   1.9   msaitoh 	}
    490   1.1    itojun 
    491   1.8   thorpej 	callout_init(&sc->sc_diag_ch);
    492  1.24       uch #ifdef SH4
    493  1.24       uch 	intc_intr_establish(SH4_INTEVT_SCIF_ERI, IST_LEVEL, IPL_SERIAL,
    494  1.24       uch 	    scifintr, sc);
    495  1.24       uch 	intc_intr_establish(SH4_INTEVT_SCIF_RXI, IST_LEVEL, IPL_SERIAL,
    496  1.24       uch 	    scifintr, sc);
    497  1.24       uch 	intc_intr_establish(SH4_INTEVT_SCIF_BRI, IST_LEVEL, IPL_SERIAL,
    498  1.24       uch 	    scifintr, sc);
    499  1.24       uch 	intc_intr_establish(SH4_INTEVT_SCIF_TXI, IST_LEVEL, IPL_SERIAL,
    500  1.24       uch 	    scifintr, sc);
    501  1.24       uch #else
    502  1.24       uch 	intc_intr_establish(SH7709_INTEVT2_SCIF_ERI, IST_LEVEL, IPL_SERIAL,
    503  1.24       uch 	    scifintr, sc);
    504  1.24       uch 	intc_intr_establish(SH7709_INTEVT2_SCIF_RXI, IST_LEVEL, IPL_SERIAL,
    505  1.24       uch 	    scifintr, sc);
    506  1.24       uch 	intc_intr_establish(SH7709_INTEVT2_SCIF_BRI, IST_LEVEL, IPL_SERIAL,
    507  1.24       uch 	    scifintr, sc);
    508  1.24       uch 	intc_intr_establish(SH7709_INTEVT2_SCIF_TXI, IST_LEVEL, IPL_SERIAL,
    509  1.24       uch 	    scifintr, sc);
    510  1.24       uch #endif
    511   1.8   thorpej 
    512  1.24       uch #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
    513  1.24       uch 	sc->sc_si = softintr_establish(IPL_SOFTSERIAL, scifsoft, sc);
    514  1.24       uch #endif
    515   1.9   msaitoh 	SET(sc->sc_hwflags, SCIF_HW_DEV_OK);
    516   1.1    itojun 
    517   1.1    itojun 	tp = ttymalloc();
    518   1.1    itojun 	tp->t_oproc = scifstart;
    519   1.1    itojun 	tp->t_param = scifparam;
    520   1.1    itojun 	tp->t_hwiflow = NULL;
    521   1.1    itojun 
    522   1.1    itojun 	sc->sc_tty = tp;
    523   1.1    itojun 	sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT);
    524   1.1    itojun 	if (sc->sc_rbuf == NULL) {
    525   1.1    itojun 		printf("%s: unable to allocate ring buffer\n",
    526   1.1    itojun 		    sc->sc_dev.dv_xname);
    527   1.1    itojun 		return;
    528   1.1    itojun 	}
    529   1.1    itojun 	sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1);
    530   1.1    itojun 
    531   1.1    itojun 	tty_attach(tp);
    532   1.1    itojun }
    533   1.1    itojun 
    534   1.1    itojun /*
    535   1.1    itojun  * Start or restart transmission.
    536   1.1    itojun  */
    537   1.1    itojun static void
    538  1.20       uch scifstart(struct tty *tp)
    539   1.1    itojun {
    540   1.1    itojun 	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
    541   1.1    itojun 	int s;
    542   1.1    itojun 
    543   1.1    itojun 	s = spltty();
    544   1.1    itojun 	if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP))
    545   1.1    itojun 		goto out;
    546   1.1    itojun 	if (sc->sc_tx_stopped)
    547   1.1    itojun 		goto out;
    548   1.1    itojun 
    549   1.1    itojun 	if (tp->t_outq.c_cc <= tp->t_lowat) {
    550   1.1    itojun 		if (ISSET(tp->t_state, TS_ASLEEP)) {
    551   1.1    itojun 			CLR(tp->t_state, TS_ASLEEP);
    552   1.1    itojun 			wakeup(&tp->t_outq);
    553   1.1    itojun 		}
    554   1.1    itojun 		selwakeup(&tp->t_wsel);
    555   1.1    itojun 		if (tp->t_outq.c_cc == 0)
    556   1.1    itojun 			goto out;
    557   1.1    itojun 	}
    558   1.1    itojun 
    559   1.1    itojun 	/* Grab the first contiguous region of buffer space. */
    560   1.1    itojun 	{
    561   1.1    itojun 		u_char *tba;
    562   1.1    itojun 		int tbc;
    563   1.1    itojun 
    564   1.1    itojun 		tba = tp->t_outq.c_cf;
    565   1.1    itojun 		tbc = ndqb(&tp->t_outq, 0);
    566   1.1    itojun 
    567   1.1    itojun 		(void)splserial();
    568   1.1    itojun 
    569   1.1    itojun 		sc->sc_tba = tba;
    570   1.1    itojun 		sc->sc_tbc = tbc;
    571   1.1    itojun 	}
    572   1.1    itojun 
    573   1.1    itojun 	SET(tp->t_state, TS_BUSY);
    574   1.1    itojun 	sc->sc_tx_busy = 1;
    575   1.1    itojun 
    576   1.1    itojun 	/* Enable transmit completion interrupts if necessary. */
    577  1.37       uwe 	scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE);
    578   1.1    itojun 
    579   1.1    itojun 	/* Output the first chunk of the contiguous buffer. */
    580   1.1    itojun 	{
    581   1.1    itojun 		int n;
    582   1.1    itojun 		int max;
    583   1.1    itojun 		int i;
    584   1.1    itojun 
    585   1.1    itojun 		n = sc->sc_tbc;
    586  1.37       uwe 		max = sc->sc_fifolen - ((scif_fdr_read() & SCFDR2_TXCNT) >> 8);
    587   1.1    itojun 		if (n > max)
    588   1.1    itojun 			n = max;
    589   1.1    itojun 
    590   1.1    itojun 		for (i = 0; i < n; i++) {
    591  1.14   msaitoh 			scif_putc(*(sc->sc_tba));
    592   1.1    itojun 			sc->sc_tba++;
    593   1.1    itojun 		}
    594   1.1    itojun 		sc->sc_tbc -= n;
    595   1.1    itojun 	}
    596   1.1    itojun out:
    597   1.1    itojun 	splx(s);
    598   1.1    itojun 	return;
    599   1.1    itojun }
    600   1.1    itojun 
    601   1.1    itojun /*
    602   1.1    itojun  * Set SCIF tty parameters from termios.
    603   1.1    itojun  * XXX - Should just copy the whole termios after
    604   1.1    itojun  * making sure all the changes could be done.
    605   1.1    itojun  */
    606   1.1    itojun static int
    607  1.20       uch scifparam(struct tty *tp, struct termios *t)
    608   1.1    itojun {
    609   1.1    itojun 	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
    610   1.1    itojun 	int ospeed = t->c_ospeed;
    611   1.1    itojun 	int s;
    612   1.1    itojun 
    613   1.1    itojun 	if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
    614   1.1    itojun 		return (EIO);
    615   1.1    itojun 
    616   1.1    itojun 	/* Check requested parameters. */
    617   1.1    itojun 	if (ospeed < 0)
    618   1.1    itojun 		return (EINVAL);
    619   1.1    itojun 	if (t->c_ispeed && t->c_ispeed != t->c_ospeed)
    620   1.1    itojun 		return (EINVAL);
    621   1.1    itojun 
    622   1.1    itojun 	/*
    623   1.1    itojun 	 * For the console, always force CLOCAL and !HUPCL, so that the port
    624   1.1    itojun 	 * is always active.
    625   1.1    itojun 	 */
    626   1.1    itojun 	if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
    627   1.1    itojun 	    ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
    628   1.1    itojun 		SET(t->c_cflag, CLOCAL);
    629   1.1    itojun 		CLR(t->c_cflag, HUPCL);
    630   1.1    itojun 	}
    631   1.1    itojun 
    632   1.1    itojun 	/*
    633   1.1    itojun 	 * If there were no changes, don't do anything.  This avoids dropping
    634   1.1    itojun 	 * input and improves performance when all we did was frob things like
    635   1.1    itojun 	 * VMIN and VTIME.
    636   1.1    itojun 	 */
    637   1.1    itojun 	if (tp->t_ospeed == t->c_ospeed &&
    638   1.1    itojun 	    tp->t_cflag == t->c_cflag)
    639   1.1    itojun 		return (0);
    640   1.1    itojun 
    641   1.1    itojun #if 0
    642   1.1    itojun /* XXX (msaitoh) */
    643   1.1    itojun 	lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag);
    644   1.1    itojun #endif
    645   1.1    itojun 
    646   1.1    itojun 	s = splserial();
    647   1.1    itojun 
    648   1.1    itojun 	/*
    649   1.1    itojun 	 * Set the flow control pins depending on the current flow control
    650   1.1    itojun 	 * mode.
    651   1.1    itojun 	 */
    652   1.1    itojun 	if (ISSET(t->c_cflag, CRTSCTS)) {
    653  1.37       uwe 		scif_fcr_write(scif_fcr_read() | SCFCR2_MCE);
    654   1.1    itojun 	} else {
    655  1.37       uwe 		scif_fcr_write(scif_fcr_read() & ~SCFCR2_MCE);
    656   1.1    itojun 	}
    657   1.1    itojun 
    658  1.37       uwe 	scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * ospeed) -1);
    659   1.1    itojun 
    660   1.1    itojun 	/*
    661   1.1    itojun 	 * Set the FIFO threshold based on the receive speed.
    662   1.1    itojun 	 *
    663   1.1    itojun 	 *  * If it's a low speed, it's probably a mouse or some other
    664   1.1    itojun 	 *    interactive device, so set the threshold low.
    665   1.1    itojun 	 *  * If it's a high speed, trim the trigger level down to prevent
    666   1.1    itojun 	 *    overflows.
    667   1.1    itojun 	 *  * Otherwise set it a bit higher.
    668   1.1    itojun 	 */
    669   1.1    itojun #if 0
    670   1.1    itojun /* XXX (msaitoh) */
    671   1.1    itojun 	if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP))
    672   1.1    itojun 		sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8;
    673   1.1    itojun 	else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO))
    674   1.1    itojun 		sc->sc_fifo = FIFO_ENABLE |
    675   1.1    itojun 		    (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 :
    676   1.1    itojun 		     t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4);
    677   1.1    itojun 	else
    678   1.1    itojun 		sc->sc_fifo = 0;
    679   1.1    itojun #endif
    680   1.1    itojun 
    681   1.1    itojun 	/* And copy to tty. */
    682   1.1    itojun 	tp->t_ispeed = 0;
    683   1.1    itojun 	tp->t_ospeed = t->c_ospeed;
    684   1.1    itojun 	tp->t_cflag = t->c_cflag;
    685   1.1    itojun 
    686   1.1    itojun 	if (!sc->sc_heldchange) {
    687   1.1    itojun 		if (sc->sc_tx_busy) {
    688   1.1    itojun 			sc->sc_heldtbc = sc->sc_tbc;
    689   1.1    itojun 			sc->sc_tbc = 0;
    690   1.1    itojun 			sc->sc_heldchange = 1;
    691   1.1    itojun 		}
    692   1.1    itojun #if 0
    693   1.1    itojun /* XXX (msaitoh) */
    694   1.1    itojun 		else
    695   1.1    itojun 			scif_loadchannelregs(sc);
    696   1.1    itojun #endif
    697   1.1    itojun 	}
    698   1.1    itojun 
    699   1.1    itojun 	if (!ISSET(t->c_cflag, CHWFLOW)) {
    700   1.1    itojun 		/* Disable the high water mark. */
    701   1.1    itojun 		sc->sc_r_hiwat = 0;
    702   1.1    itojun 		sc->sc_r_lowat = 0;
    703   1.1    itojun 		if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) {
    704   1.1    itojun 			CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
    705   1.1    itojun 			scif_schedrx(sc);
    706   1.1    itojun 		}
    707   1.1    itojun 	} else {
    708   1.1    itojun 		sc->sc_r_hiwat = scif_rbuf_hiwat;
    709   1.1    itojun 		sc->sc_r_lowat = scif_rbuf_lowat;
    710   1.1    itojun 	}
    711   1.1    itojun 
    712   1.1    itojun 	splx(s);
    713   1.1    itojun 
    714   1.1    itojun #ifdef SCIF_DEBUG
    715   1.1    itojun 	if (scif_debug)
    716   1.1    itojun 		scifstatus(sc, "scifparam ");
    717   1.1    itojun #endif
    718   1.1    itojun 
    719   1.1    itojun 	if (!ISSET(t->c_cflag, CHWFLOW)) {
    720   1.1    itojun 		if (sc->sc_tx_stopped) {
    721   1.1    itojun 			sc->sc_tx_stopped = 0;
    722   1.1    itojun 			scifstart(tp);
    723   1.1    itojun 		}
    724   1.1    itojun 	}
    725   1.1    itojun 
    726   1.1    itojun 	return (0);
    727   1.1    itojun }
    728   1.1    itojun 
    729   1.1    itojun void
    730  1.20       uch scif_iflush(struct scif_softc *sc)
    731   1.1    itojun {
    732   1.1    itojun 	int i;
    733   1.1    itojun 	unsigned char c;
    734   1.1    itojun 
    735  1.37       uwe 	i = scif_fdr_read() & SCFDR2_RECVCNT;
    736   1.1    itojun 
    737   1.1    itojun 	while (i > 0) {
    738  1.37       uwe 		c = scif_frdr_read();
    739  1.37       uwe 		scif_ssr_write(scif_ssr_read() & ~(SCSSR2_RDF | SCSSR2_DR));
    740   1.1    itojun 		i--;
    741   1.1    itojun 	}
    742   1.1    itojun }
    743   1.1    itojun 
    744   1.1    itojun int
    745  1.20       uch scifopen(dev_t dev, int flag, int mode, struct proc *p)
    746   1.1    itojun {
    747   1.1    itojun 	int unit = SCIFUNIT(dev);
    748   1.1    itojun 	struct scif_softc *sc;
    749   1.1    itojun 	struct tty *tp;
    750   1.1    itojun 	int s, s2;
    751   1.1    itojun 	int error;
    752   1.1    itojun 
    753   1.1    itojun 	if (unit >= scif_cd.cd_ndevs)
    754   1.1    itojun 		return (ENXIO);
    755   1.1    itojun 	sc = scif_cd.cd_devs[unit];
    756   1.1    itojun 	if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) ||
    757   1.1    itojun 	    sc->sc_rbuf == NULL)
    758   1.1    itojun 		return (ENXIO);
    759   1.1    itojun 
    760   1.1    itojun 	if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
    761   1.1    itojun 		return (ENXIO);
    762   1.1    itojun 
    763   1.1    itojun #ifdef KGDB
    764   1.1    itojun 	/*
    765   1.1    itojun 	 * If this is the kgdb port, no other use is permitted.
    766   1.1    itojun 	 */
    767   1.1    itojun 	if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB))
    768   1.1    itojun 		return (EBUSY);
    769  1.22       uch #endif /* KGDB */
    770   1.1    itojun 
    771   1.1    itojun 	tp = sc->sc_tty;
    772   1.1    itojun 
    773   1.1    itojun 	if (ISSET(tp->t_state, TS_ISOPEN) &&
    774   1.1    itojun 	    ISSET(tp->t_state, TS_XCLUDE) &&
    775   1.1    itojun 	    p->p_ucred->cr_uid != 0)
    776   1.1    itojun 		return (EBUSY);
    777   1.1    itojun 
    778   1.1    itojun 	s = spltty();
    779   1.1    itojun 
    780   1.1    itojun 	/*
    781   1.1    itojun 	 * Do the following iff this is a first open.
    782   1.1    itojun 	 */
    783   1.1    itojun 	if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
    784   1.1    itojun 		struct termios t;
    785   1.1    itojun 
    786   1.1    itojun 		tp->t_dev = dev;
    787   1.1    itojun 
    788   1.1    itojun 		s2 = splserial();
    789   1.1    itojun 
    790   1.1    itojun 		/* Turn on interrupts. */
    791  1.37       uwe 		scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE);
    792   1.1    itojun 
    793   1.1    itojun 		splx(s2);
    794   1.1    itojun 
    795   1.1    itojun 		/*
    796   1.1    itojun 		 * Initialize the termios status to the defaults.  Add in the
    797   1.1    itojun 		 * sticky bits from TIOCSFLAGS.
    798   1.1    itojun 		 */
    799   1.1    itojun 		t.c_ispeed = 0;
    800   1.1    itojun 		if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
    801   1.7   msaitoh 			t.c_ospeed = scifcn_speed;	/* XXX (msaitoh) */
    802   1.1    itojun 			t.c_cflag = scifconscflag;
    803   1.1    itojun 		} else {
    804   1.1    itojun 			t.c_ospeed = TTYDEF_SPEED;
    805   1.1    itojun 			t.c_cflag = TTYDEF_CFLAG;
    806   1.1    itojun 		}
    807   1.1    itojun 		if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL))
    808   1.1    itojun 			SET(t.c_cflag, CLOCAL);
    809   1.1    itojun 		if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS))
    810   1.1    itojun 			SET(t.c_cflag, CRTSCTS);
    811   1.1    itojun 		if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF))
    812   1.1    itojun 			SET(t.c_cflag, MDMBUF);
    813   1.1    itojun 		/* Make sure scifparam() will do something. */
    814   1.1    itojun 		tp->t_ospeed = 0;
    815   1.1    itojun 		(void) scifparam(tp, &t);
    816   1.1    itojun 		tp->t_iflag = TTYDEF_IFLAG;
    817   1.1    itojun 		tp->t_oflag = TTYDEF_OFLAG;
    818   1.1    itojun 		tp->t_lflag = TTYDEF_LFLAG;
    819   1.1    itojun 		ttychars(tp);
    820   1.1    itojun 		ttsetwater(tp);
    821   1.1    itojun 
    822   1.1    itojun 		s2 = splserial();
    823   1.1    itojun 
    824   1.1    itojun 		/* Clear the input ring, and unblock. */
    825   1.1    itojun 		sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf;
    826   1.1    itojun 		sc->sc_rbavail = scif_rbuf_size;
    827   1.1    itojun 		scif_iflush(sc);
    828   1.1    itojun 		CLR(sc->sc_rx_flags, RX_ANY_BLOCK);
    829   1.1    itojun #if 0
    830   1.1    itojun /* XXX (msaitoh) */
    831   1.1    itojun 		scif_hwiflow(sc);
    832   1.1    itojun #endif
    833   1.1    itojun 
    834   1.1    itojun #ifdef SCIF_DEBUG
    835   1.1    itojun 		if (scif_debug)
    836   1.1    itojun 			scifstatus(sc, "scifopen  ");
    837   1.1    itojun #endif
    838   1.1    itojun 
    839   1.1    itojun 		splx(s2);
    840   1.1    itojun 	}
    841   1.1    itojun 
    842   1.1    itojun 	splx(s);
    843   1.1    itojun 
    844   1.1    itojun 	error = ttyopen(tp, SCIFDIALOUT(dev), ISSET(flag, O_NONBLOCK));
    845   1.1    itojun 	if (error)
    846   1.1    itojun 		goto bad;
    847   1.1    itojun 
    848  1.13       eeh 	error = (*tp->t_linesw->l_open)(dev, tp);
    849   1.1    itojun 	if (error)
    850   1.1    itojun 		goto bad;
    851   1.1    itojun 
    852   1.1    itojun 	return (0);
    853   1.1    itojun 
    854   1.1    itojun bad:
    855   1.1    itojun 
    856   1.1    itojun 	return (error);
    857   1.1    itojun }
    858   1.1    itojun 
    859   1.1    itojun int
    860  1.20       uch scifclose(dev_t dev, int flag, int mode, struct proc *p)
    861   1.1    itojun {
    862   1.1    itojun 	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
    863   1.1    itojun 	struct tty *tp = sc->sc_tty;
    864   1.1    itojun 
    865   1.1    itojun 	/* XXX This is for cons.c. */
    866   1.1    itojun 	if (!ISSET(tp->t_state, TS_ISOPEN))
    867   1.1    itojun 		return (0);
    868   1.1    itojun 
    869  1.13       eeh 	(*tp->t_linesw->l_close)(tp, flag);
    870   1.1    itojun 	ttyclose(tp);
    871   1.1    itojun 
    872   1.1    itojun 	if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
    873   1.1    itojun 		return (0);
    874   1.1    itojun 
    875   1.1    itojun 	return (0);
    876   1.1    itojun }
    877   1.1    itojun 
    878   1.1    itojun int
    879  1.20       uch scifread(dev_t dev, struct uio *uio, int flag)
    880   1.1    itojun {
    881   1.1    itojun 	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
    882   1.1    itojun 	struct tty *tp = sc->sc_tty;
    883   1.1    itojun 
    884  1.13       eeh 	return ((*tp->t_linesw->l_read)(tp, uio, flag));
    885   1.1    itojun }
    886   1.1    itojun 
    887   1.1    itojun int
    888  1.20       uch scifwrite(dev_t dev, struct uio *uio, int flag)
    889   1.1    itojun {
    890   1.1    itojun 	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
    891   1.1    itojun 	struct tty *tp = sc->sc_tty;
    892   1.1    itojun 
    893  1.13       eeh 	return ((*tp->t_linesw->l_write)(tp, uio, flag));
    894  1.16       scw }
    895  1.16       scw 
    896  1.16       scw int
    897  1.20       uch scifpoll(dev_t dev, int events, struct proc *p)
    898  1.16       scw {
    899  1.16       scw 	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
    900  1.16       scw 	struct tty *tp = sc->sc_tty;
    901  1.25       uch 
    902  1.16       scw 	return ((*tp->t_linesw->l_poll)(tp, events, p));
    903   1.1    itojun }
    904   1.1    itojun 
    905   1.1    itojun struct tty *
    906  1.20       uch sciftty(dev_t dev)
    907   1.1    itojun {
    908   1.1    itojun 	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
    909   1.1    itojun 	struct tty *tp = sc->sc_tty;
    910   1.1    itojun 
    911   1.1    itojun 	return (tp);
    912   1.1    itojun }
    913   1.1    itojun 
    914   1.1    itojun int
    915  1.20       uch scifioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
    916   1.1    itojun {
    917   1.1    itojun 	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)];
    918   1.1    itojun 	struct tty *tp = sc->sc_tty;
    919   1.1    itojun 	int error;
    920   1.1    itojun 	int s;
    921   1.1    itojun 
    922   1.1    itojun 	if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
    923   1.1    itojun 		return (EIO);
    924   1.1    itojun 
    925  1.13       eeh 	error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p);
    926  1.23    atatat 	if (error != EPASSTHROUGH)
    927   1.1    itojun 		return (error);
    928   1.1    itojun 
    929   1.1    itojun 	error = ttioctl(tp, cmd, data, flag, p);
    930  1.23    atatat 	if (error != EPASSTHROUGH)
    931   1.1    itojun 		return (error);
    932   1.1    itojun 
    933   1.1    itojun 	error = 0;
    934   1.1    itojun 
    935   1.1    itojun 	s = splserial();
    936   1.1    itojun 
    937   1.1    itojun 	switch (cmd) {
    938   1.1    itojun 	case TIOCSBRK:
    939   1.1    itojun 		scif_break(sc, 1);
    940   1.1    itojun 		break;
    941   1.1    itojun 
    942   1.1    itojun 	case TIOCCBRK:
    943   1.1    itojun 		scif_break(sc, 0);
    944   1.1    itojun 		break;
    945   1.6   msaitoh 
    946   1.1    itojun 	case TIOCGFLAGS:
    947   1.1    itojun 		*(int *)data = sc->sc_swflags;
    948   1.1    itojun 		break;
    949   1.1    itojun 
    950   1.1    itojun 	case TIOCSFLAGS:
    951   1.1    itojun 		error = suser(p->p_ucred, &p->p_acflag);
    952   1.1    itojun 		if (error)
    953   1.1    itojun 			break;
    954   1.1    itojun 		sc->sc_swflags = *(int *)data;
    955   1.1    itojun 		break;
    956   1.1    itojun 
    957   1.1    itojun 	default:
    958  1.23    atatat 		error = EPASSTHROUGH;
    959   1.1    itojun 		break;
    960   1.1    itojun 	}
    961   1.1    itojun 
    962   1.1    itojun 	splx(s);
    963   1.1    itojun 
    964   1.1    itojun 	return (error);
    965   1.1    itojun }
    966   1.1    itojun 
    967   1.1    itojun integrate void
    968  1.20       uch scif_schedrx(struct scif_softc *sc)
    969   1.1    itojun {
    970   1.1    itojun 
    971   1.1    itojun 	sc->sc_rx_ready = 1;
    972   1.1    itojun 
    973   1.1    itojun 	/* Wake up the poller. */
    974  1.15   thorpej #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
    975   1.1    itojun 	softintr_schedule(sc->sc_si);
    976   1.1    itojun #else
    977   1.1    itojun #ifndef __NO_SOFT_SERIAL_INTERRUPT
    978   1.1    itojun 	setsoftserial();
    979   1.1    itojun #else
    980   1.1    itojun 	if (!scif_softintr_scheduled) {
    981   1.1    itojun 		scif_softintr_scheduled = 1;
    982   1.8   thorpej 		callout_reset(&scif_soft_ch, 1, scifsoft, NULL);
    983   1.1    itojun 	}
    984   1.1    itojun #endif
    985   1.1    itojun #endif
    986   1.1    itojun }
    987   1.1    itojun 
    988   1.6   msaitoh void
    989  1.20       uch scif_break(struct scif_softc *sc, int onoff)
    990   1.6   msaitoh {
    991   1.6   msaitoh 
    992   1.6   msaitoh 	if (onoff)
    993  1.37       uwe 		scif_ssr_write(scif_ssr_read() & ~SCSSR2_TDFE);
    994   1.6   msaitoh 	else
    995  1.37       uwe 		scif_ssr_write(scif_ssr_read() | SCSSR2_TDFE);
    996   1.6   msaitoh 
    997   1.6   msaitoh #if 0	/* XXX */
    998   1.6   msaitoh 	if (!sc->sc_heldchange) {
    999   1.6   msaitoh 		if (sc->sc_tx_busy) {
   1000   1.6   msaitoh 			sc->sc_heldtbc = sc->sc_tbc;
   1001   1.6   msaitoh 			sc->sc_tbc = 0;
   1002   1.6   msaitoh 			sc->sc_heldchange = 1;
   1003   1.6   msaitoh 		} else
   1004   1.6   msaitoh 			scif_loadchannelregs(sc);
   1005   1.6   msaitoh 	}
   1006   1.6   msaitoh #endif
   1007   1.6   msaitoh }
   1008   1.6   msaitoh 
   1009   1.1    itojun /*
   1010   1.1    itojun  * Stop output, e.g., for ^S or output flush.
   1011   1.1    itojun  */
   1012   1.1    itojun void
   1013  1.20       uch scifstop(struct tty *tp, int flag)
   1014   1.1    itojun {
   1015   1.1    itojun 	struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)];
   1016   1.1    itojun 	int s;
   1017   1.1    itojun 
   1018   1.1    itojun 	s = splserial();
   1019   1.1    itojun 	if (ISSET(tp->t_state, TS_BUSY)) {
   1020   1.1    itojun 		/* Stop transmitting at the next chunk. */
   1021   1.1    itojun 		sc->sc_tbc = 0;
   1022   1.1    itojun 		sc->sc_heldtbc = 0;
   1023   1.1    itojun 		if (!ISSET(tp->t_state, TS_TTSTOP))
   1024   1.1    itojun 			SET(tp->t_state, TS_FLUSH);
   1025   1.1    itojun 	}
   1026   1.1    itojun 	splx(s);
   1027   1.1    itojun }
   1028   1.1    itojun 
   1029   1.1    itojun void
   1030   1.1    itojun scif_intr_init()
   1031   1.1    itojun {
   1032   1.1    itojun 	/* XXX */
   1033   1.1    itojun }
   1034   1.1    itojun 
   1035   1.1    itojun void
   1036  1.20       uch scifdiag(void *arg)
   1037   1.1    itojun {
   1038   1.1    itojun 	struct scif_softc *sc = arg;
   1039   1.1    itojun 	int overflows, floods;
   1040   1.1    itojun 	int s;
   1041   1.1    itojun 
   1042   1.1    itojun 	s = splserial();
   1043   1.1    itojun 	overflows = sc->sc_overflows;
   1044   1.1    itojun 	sc->sc_overflows = 0;
   1045   1.1    itojun 	floods = sc->sc_floods;
   1046   1.1    itojun 	sc->sc_floods = 0;
   1047   1.1    itojun 	sc->sc_errors = 0;
   1048   1.1    itojun 	splx(s);
   1049   1.1    itojun 
   1050   1.1    itojun 	log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n",
   1051   1.1    itojun 	    sc->sc_dev.dv_xname,
   1052   1.1    itojun 	    overflows, overflows == 1 ? "" : "s",
   1053   1.1    itojun 	    floods, floods == 1 ? "" : "s");
   1054   1.1    itojun }
   1055   1.1    itojun 
   1056   1.1    itojun integrate void
   1057  1.20       uch scif_rxsoft(struct scif_softc *sc, struct tty *tp)
   1058   1.1    itojun {
   1059  1.20       uch 	int (*rint)(int c, struct tty *tp) = tp->t_linesw->l_rint;
   1060   1.1    itojun 	u_char *get, *end;
   1061   1.1    itojun 	u_int cc, scc;
   1062   1.1    itojun 	u_char ssr2;
   1063   1.1    itojun 	int code;
   1064   1.1    itojun 	int s;
   1065   1.1    itojun 
   1066   1.1    itojun 	end = sc->sc_ebuf;
   1067   1.1    itojun 	get = sc->sc_rbget;
   1068   1.1    itojun 	scc = cc = scif_rbuf_size - sc->sc_rbavail;
   1069   1.1    itojun 
   1070   1.1    itojun 	if (cc == scif_rbuf_size) {
   1071   1.1    itojun 		sc->sc_floods++;
   1072   1.1    itojun 		if (sc->sc_errors++ == 0)
   1073  1.11   msaitoh 			callout_reset(&sc->sc_diag_ch, 60 * hz, scifdiag, sc);
   1074   1.1    itojun 	}
   1075   1.1    itojun 
   1076   1.1    itojun 	while (cc) {
   1077   1.1    itojun 		code = get[0];
   1078   1.1    itojun 		ssr2 = get[1];
   1079   1.6   msaitoh 		if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) {
   1080   1.6   msaitoh 			if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER))
   1081   1.1    itojun 				SET(code, TTY_FE);
   1082   1.1    itojun 			if (ISSET(ssr2, SCSSR2_PER))
   1083   1.1    itojun 				SET(code, TTY_PE);
   1084   1.1    itojun 		}
   1085   1.1    itojun 		if ((*rint)(code, tp) == -1) {
   1086   1.1    itojun 			/*
   1087   1.1    itojun 			 * The line discipline's buffer is out of space.
   1088   1.1    itojun 			 */
   1089   1.1    itojun 			if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
   1090   1.1    itojun 				/*
   1091   1.1    itojun 				 * We're either not using flow control, or the
   1092   1.1    itojun 				 * line discipline didn't tell us to block for
   1093   1.1    itojun 				 * some reason.  Either way, we have no way to
   1094   1.1    itojun 				 * know when there's more space available, so
   1095   1.1    itojun 				 * just drop the rest of the data.
   1096   1.1    itojun 				 */
   1097   1.1    itojun 				get += cc << 1;
   1098   1.1    itojun 				if (get >= end)
   1099   1.1    itojun 					get -= scif_rbuf_size << 1;
   1100   1.1    itojun 				cc = 0;
   1101   1.1    itojun 			} else {
   1102   1.1    itojun 				/*
   1103   1.1    itojun 				 * Don't schedule any more receive processing
   1104   1.1    itojun 				 * until the line discipline tells us there's
   1105   1.1    itojun 				 * space available (through scifhwiflow()).
   1106   1.1    itojun 				 * Leave the rest of the data in the input
   1107   1.1    itojun 				 * buffer.
   1108   1.1    itojun 				 */
   1109   1.1    itojun 				SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
   1110   1.1    itojun 			}
   1111   1.1    itojun 			break;
   1112   1.1    itojun 		}
   1113   1.1    itojun 		get += 2;
   1114   1.1    itojun 		if (get >= end)
   1115   1.1    itojun 			get = sc->sc_rbuf;
   1116   1.1    itojun 		cc--;
   1117   1.1    itojun 	}
   1118   1.1    itojun 
   1119   1.1    itojun 	if (cc != scc) {
   1120   1.1    itojun 		sc->sc_rbget = get;
   1121   1.1    itojun 		s = splserial();
   1122   1.1    itojun 		cc = sc->sc_rbavail += scc - cc;
   1123   1.1    itojun 		/* Buffers should be ok again, release possible block. */
   1124   1.1    itojun 		if (cc >= sc->sc_r_lowat) {
   1125   1.1    itojun 			if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
   1126   1.1    itojun 				CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
   1127  1.37       uwe 				scif_scr_write(scif_scr_read() | SCSCR2_RIE);
   1128   1.1    itojun 			}
   1129   1.1    itojun #if 0
   1130   1.1    itojun 			if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) {
   1131   1.1    itojun 				CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED);
   1132   1.1    itojun 				scif_hwiflow(sc);
   1133   1.1    itojun 			}
   1134   1.1    itojun #endif
   1135   1.1    itojun 		}
   1136   1.1    itojun 		splx(s);
   1137   1.1    itojun 	}
   1138   1.1    itojun }
   1139   1.1    itojun 
   1140   1.1    itojun integrate void
   1141  1.20       uch scif_txsoft(struct scif_softc *sc, struct tty *tp)
   1142   1.1    itojun {
   1143   1.1    itojun 
   1144   1.1    itojun 	CLR(tp->t_state, TS_BUSY);
   1145   1.1    itojun 	if (ISSET(tp->t_state, TS_FLUSH))
   1146   1.1    itojun 		CLR(tp->t_state, TS_FLUSH);
   1147   1.1    itojun 	else
   1148   1.1    itojun 		ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf));
   1149  1.13       eeh 	(*tp->t_linesw->l_start)(tp);
   1150   1.1    itojun }
   1151   1.1    itojun 
   1152   1.1    itojun integrate void
   1153  1.20       uch scif_stsoft(struct scif_softc *sc, struct tty *tp)
   1154   1.1    itojun {
   1155   1.1    itojun #if 0
   1156   1.1    itojun /* XXX (msaitoh) */
   1157   1.1    itojun 	u_char msr, delta;
   1158   1.1    itojun 	int s;
   1159   1.1    itojun 
   1160   1.1    itojun 	s = splserial();
   1161   1.1    itojun 	msr = sc->sc_msr;
   1162   1.1    itojun 	delta = sc->sc_msr_delta;
   1163   1.1    itojun 	sc->sc_msr_delta = 0;
   1164   1.1    itojun 	splx(s);
   1165   1.1    itojun 
   1166   1.1    itojun 	if (ISSET(delta, sc->sc_msr_dcd)) {
   1167   1.1    itojun 		/*
   1168   1.1    itojun 		 * Inform the tty layer that carrier detect changed.
   1169   1.1    itojun 		 */
   1170  1.13       eeh 		(void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD));
   1171   1.1    itojun 	}
   1172   1.1    itojun 
   1173   1.1    itojun 	if (ISSET(delta, sc->sc_msr_cts)) {
   1174   1.1    itojun 		/* Block or unblock output according to flow control. */
   1175   1.1    itojun 		if (ISSET(msr, sc->sc_msr_cts)) {
   1176   1.1    itojun 			sc->sc_tx_stopped = 0;
   1177  1.13       eeh 			(*tp->t_linesw->l_start)(tp);
   1178   1.1    itojun 		} else {
   1179   1.1    itojun 			sc->sc_tx_stopped = 1;
   1180   1.1    itojun 		}
   1181   1.1    itojun 	}
   1182   1.1    itojun 
   1183   1.1    itojun #ifdef SCIF_DEBUG
   1184   1.1    itojun 	if (scif_debug)
   1185   1.1    itojun 		scifstatus(sc, "scif_stsoft");
   1186   1.1    itojun #endif
   1187   1.1    itojun #endif
   1188   1.1    itojun }
   1189   1.1    itojun 
   1190  1.15   thorpej #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
   1191   1.1    itojun void
   1192  1.20       uch scifsoft(void *arg)
   1193   1.1    itojun {
   1194   1.1    itojun 	struct scif_softc *sc = arg;
   1195   1.1    itojun 	struct tty *tp;
   1196   1.1    itojun 
   1197   1.1    itojun 	if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
   1198   1.1    itojun 		return;
   1199   1.1    itojun 
   1200   1.1    itojun 	{
   1201   1.1    itojun #else
   1202   1.1    itojun void
   1203   1.1    itojun #ifndef __NO_SOFT_SERIAL_INTERRUPT
   1204   1.1    itojun scifsoft()
   1205   1.1    itojun #else
   1206  1.20       uch scifsoft(void *arg)
   1207   1.1    itojun #endif
   1208   1.1    itojun {
   1209   1.1    itojun 	struct scif_softc	*sc;
   1210   1.1    itojun 	struct tty	*tp;
   1211   1.1    itojun 	int	unit;
   1212   1.1    itojun #ifdef __NO_SOFT_SERIAL_INTERRUPT
   1213   1.1    itojun 	int s;
   1214   1.1    itojun 
   1215   1.1    itojun 	s = splsoftserial();
   1216   1.1    itojun 	scif_softintr_scheduled = 0;
   1217   1.1    itojun #endif
   1218   1.1    itojun 
   1219   1.1    itojun 	for (unit = 0; unit < scif_cd.cd_ndevs; unit++) {
   1220   1.1    itojun 		sc = scif_cd.cd_devs[unit];
   1221   1.1    itojun 		if (sc == NULL || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK))
   1222   1.1    itojun 			continue;
   1223   1.1    itojun 
   1224   1.1    itojun 		if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
   1225   1.1    itojun 			continue;
   1226   1.1    itojun 
   1227   1.1    itojun 		tp = sc->sc_tty;
   1228   1.1    itojun 		if (tp == NULL)
   1229   1.1    itojun 			continue;
   1230   1.1    itojun 		if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0)
   1231   1.1    itojun 			continue;
   1232   1.1    itojun #endif
   1233   1.1    itojun 		tp = sc->sc_tty;
   1234   1.1    itojun 
   1235   1.1    itojun 		if (sc->sc_rx_ready) {
   1236   1.1    itojun 			sc->sc_rx_ready = 0;
   1237   1.1    itojun 			scif_rxsoft(sc, tp);
   1238   1.1    itojun 		}
   1239   1.1    itojun 
   1240   1.1    itojun #if 0
   1241   1.1    itojun 		if (sc->sc_st_check) {
   1242   1.1    itojun 			sc->sc_st_check = 0;
   1243   1.1    itojun 			scif_stsoft(sc, tp);
   1244   1.1    itojun 		}
   1245   1.1    itojun #endif
   1246   1.1    itojun 
   1247   1.1    itojun 		if (sc->sc_tx_done) {
   1248   1.1    itojun 			sc->sc_tx_done = 0;
   1249   1.1    itojun 			scif_txsoft(sc, tp);
   1250   1.1    itojun 		}
   1251   1.1    itojun 	}
   1252   1.1    itojun 
   1253  1.15   thorpej #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
   1254   1.1    itojun #ifdef __NO_SOFT_SERIAL_INTERRUPT
   1255   1.1    itojun 	splx(s);
   1256   1.1    itojun #endif
   1257   1.1    itojun #endif
   1258   1.1    itojun }
   1259   1.1    itojun 
   1260   1.1    itojun int
   1261  1.20       uch scifintr(void *arg)
   1262   1.1    itojun {
   1263   1.1    itojun 	struct scif_softc *sc = arg;
   1264   1.1    itojun 	u_char *put, *end;
   1265   1.1    itojun 	u_int cc;
   1266   1.1    itojun 	u_short ssr2;
   1267   1.1    itojun 	int count;
   1268   1.1    itojun 
   1269   1.1    itojun 	if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0)
   1270   1.1    itojun 		return (0);
   1271   1.1    itojun 
   1272   1.1    itojun 	end = sc->sc_ebuf;
   1273   1.1    itojun 	put = sc->sc_rbput;
   1274   1.1    itojun 	cc = sc->sc_rbavail;
   1275   1.1    itojun 
   1276  1.26   msaitoh 	do {
   1277  1.37       uwe 		ssr2 = scif_ssr_read();
   1278  1.26   msaitoh 		if (ISSET(ssr2, SCSSR2_BRK)) {
   1279  1.37       uwe 			scif_ssr_write(scif_ssr_read()
   1280  1.37       uwe 				& ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR));
   1281   1.1    itojun #ifdef DDB
   1282  1.26   msaitoh 			if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) {
   1283  1.26   msaitoh 				console_debugger();
   1284  1.26   msaitoh 			}
   1285  1.22       uch #endif /* DDB */
   1286   1.1    itojun #ifdef KGDB
   1287  1.26   msaitoh 			if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) {
   1288  1.26   msaitoh 				kgdb_connect(1);
   1289  1.26   msaitoh 			}
   1290  1.22       uch #endif /* KGDB */
   1291   1.1    itojun 		}
   1292  1.37       uwe 		count = scif_fdr_read() & SCFDR2_RECVCNT;
   1293  1.26   msaitoh 		if (count != 0) {
   1294  1.36       uwe 			for (;;) {
   1295  1.37       uwe 				u_char c = scif_frdr_read();
   1296  1.37       uwe 				u_char err = (u_char)(scif_ssr_read() & 0x00ff);
   1297   1.1    itojun 
   1298  1.37       uwe 				scif_ssr_write(scif_ssr_read()
   1299  1.37       uwe 				    & ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR));
   1300  1.26   msaitoh #ifdef SH4
   1301  1.26   msaitoh 				if (CPU_IS_SH4)
   1302  1.37       uwe 					scif_lsr_write(scif_lsr_read()
   1303  1.37       uwe 						       & ~SCLSR2_ORER);
   1304  1.26   msaitoh #endif
   1305  1.26   msaitoh 				if ((cc > 0) && (count > 0)) {
   1306  1.26   msaitoh 					put[0] = c;
   1307  1.26   msaitoh 					put[1] = err;
   1308  1.26   msaitoh 					put += 2;
   1309  1.26   msaitoh 					if (put >= end)
   1310  1.26   msaitoh 						put = sc->sc_rbuf;
   1311  1.26   msaitoh 					cc--;
   1312  1.26   msaitoh 					count--;
   1313  1.26   msaitoh 				} else
   1314  1.26   msaitoh 					break;
   1315  1.26   msaitoh 			}
   1316  1.26   msaitoh 
   1317  1.26   msaitoh 			/*
   1318  1.26   msaitoh 			 * Current string of incoming characters ended because
   1319  1.26   msaitoh 			 * no more data was available or we ran out of space.
   1320  1.26   msaitoh 			 * Schedule a receive event if any data was received.
   1321  1.26   msaitoh 			 * If we're out of space, turn off receive interrupts.
   1322  1.26   msaitoh 			 */
   1323  1.26   msaitoh 			sc->sc_rbput = put;
   1324  1.26   msaitoh 			sc->sc_rbavail = cc;
   1325  1.26   msaitoh 			if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
   1326  1.26   msaitoh 				sc->sc_rx_ready = 1;
   1327   1.1    itojun 
   1328  1.26   msaitoh 			/*
   1329  1.26   msaitoh 			 * See if we are in danger of overflowing a buffer. If
   1330  1.26   msaitoh 			 * so, use hardware flow control to ease the pressure.
   1331  1.26   msaitoh 			 */
   1332  1.26   msaitoh 			if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
   1333  1.26   msaitoh 			    cc < sc->sc_r_hiwat) {
   1334  1.26   msaitoh 				SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
   1335   1.1    itojun #if 0
   1336  1.26   msaitoh 				scif_hwiflow(sc);
   1337   1.1    itojun #endif
   1338  1.26   msaitoh 			}
   1339   1.1    itojun 
   1340  1.26   msaitoh 			/*
   1341  1.26   msaitoh 			 * If we're out of space, disable receive interrupts
   1342  1.26   msaitoh 			 * until the queue has drained a bit.
   1343  1.26   msaitoh 			 */
   1344  1.26   msaitoh 			if (!cc) {
   1345  1.26   msaitoh 				SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
   1346  1.37       uwe 				scif_scr_write(scif_scr_read() & ~SCSCR2_RIE);
   1347  1.26   msaitoh 			}
   1348  1.26   msaitoh 		} else {
   1349  1.37       uwe 			if (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR)) {
   1350  1.37       uwe 				scif_scr_write(scif_scr_read()
   1351  1.37       uwe 					       & ~(SCSCR2_TIE | SCSCR2_RIE));
   1352  1.26   msaitoh 				delay(10);
   1353  1.37       uwe 				scif_scr_write(scif_scr_read()
   1354  1.37       uwe 					       | SCSCR2_TIE | SCSCR2_RIE);
   1355  1.26   msaitoh 				continue;
   1356  1.26   msaitoh 			}
   1357   1.7   msaitoh 		}
   1358  1.37       uwe 	} while (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR));
   1359   1.1    itojun 
   1360   1.1    itojun #if 0
   1361   1.7   msaitoh 	msr = bus_space_read_1(iot, ioh, scif_msr);
   1362   1.7   msaitoh 	delta = msr ^ sc->sc_msr;
   1363   1.7   msaitoh 	sc->sc_msr = msr;
   1364   1.7   msaitoh 	if (ISSET(delta, sc->sc_msr_mask)) {
   1365   1.7   msaitoh 		SET(sc->sc_msr_delta, delta);
   1366   1.1    itojun 
   1367   1.7   msaitoh 		/*
   1368   1.7   msaitoh 		 * Pulse-per-second clock signal on edge of DCD?
   1369   1.7   msaitoh 		 */
   1370   1.7   msaitoh 		if (ISSET(delta, sc->sc_ppsmask)) {
   1371   1.7   msaitoh 			struct timeval tv;
   1372   1.7   msaitoh 			if (ISSET(msr, sc->sc_ppsmask) ==
   1373   1.7   msaitoh 			    sc->sc_ppsassert) {
   1374   1.7   msaitoh 				/* XXX nanotime() */
   1375   1.7   msaitoh 				microtime(&tv);
   1376   1.7   msaitoh 				TIMEVAL_TO_TIMESPEC(&tv,
   1377   1.7   msaitoh 						    &sc->ppsinfo.assert_timestamp);
   1378   1.7   msaitoh 				if (sc->ppsparam.mode & PPS_OFFSETASSERT) {
   1379   1.7   msaitoh 					timespecadd(&sc->ppsinfo.assert_timestamp,
   1380   1.1    itojun 						    &sc->ppsparam.assert_offset,
   1381   1.1    itojun 						    &sc->ppsinfo.assert_timestamp);
   1382   1.7   msaitoh 					TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp);
   1383   1.7   msaitoh 				}
   1384   1.1    itojun 
   1385   1.1    itojun #ifdef PPS_SYNC
   1386   1.7   msaitoh 				if (sc->ppsparam.mode & PPS_HARDPPSONASSERT)
   1387   1.7   msaitoh 					hardpps(&tv, tv.tv_usec);
   1388   1.1    itojun #endif
   1389   1.7   msaitoh 				sc->ppsinfo.assert_sequence++;
   1390   1.7   msaitoh 				sc->ppsinfo.current_mode =
   1391   1.7   msaitoh 					sc->ppsparam.mode;
   1392   1.7   msaitoh 
   1393   1.7   msaitoh 			} else if (ISSET(msr, sc->sc_ppsmask) ==
   1394   1.7   msaitoh 				   sc->sc_ppsclear) {
   1395   1.7   msaitoh 				/* XXX nanotime() */
   1396   1.7   msaitoh 				microtime(&tv);
   1397   1.7   msaitoh 				TIMEVAL_TO_TIMESPEC(&tv,
   1398   1.7   msaitoh 						    &sc->ppsinfo.clear_timestamp);
   1399   1.7   msaitoh 				if (sc->ppsparam.mode & PPS_OFFSETCLEAR) {
   1400   1.7   msaitoh 					timespecadd(&sc->ppsinfo.clear_timestamp,
   1401   1.1    itojun 						    &sc->ppsparam.clear_offset,
   1402   1.1    itojun 						    &sc->ppsinfo.clear_timestamp);
   1403   1.7   msaitoh 					TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp);
   1404   1.7   msaitoh 				}
   1405   1.1    itojun 
   1406   1.1    itojun #ifdef PPS_SYNC
   1407   1.7   msaitoh 				if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR)
   1408   1.7   msaitoh 					hardpps(&tv, tv.tv_usec);
   1409   1.1    itojun #endif
   1410   1.7   msaitoh 				sc->ppsinfo.clear_sequence++;
   1411   1.7   msaitoh 				sc->ppsinfo.current_mode =
   1412   1.7   msaitoh 					sc->ppsparam.mode;
   1413   1.1    itojun 			}
   1414   1.7   msaitoh 		}
   1415   1.1    itojun 
   1416   1.7   msaitoh 		/*
   1417   1.7   msaitoh 		 * Stop output immediately if we lose the output
   1418   1.7   msaitoh 		 * flow control signal or carrier detect.
   1419   1.7   msaitoh 		 */
   1420   1.7   msaitoh 		if (ISSET(~msr, sc->sc_msr_mask)) {
   1421   1.7   msaitoh 			sc->sc_tbc = 0;
   1422   1.7   msaitoh 			sc->sc_heldtbc = 0;
   1423   1.1    itojun #ifdef SCIF_DEBUG
   1424   1.7   msaitoh 			if (scif_debug)
   1425   1.7   msaitoh 				scifstatus(sc, "scifintr  ");
   1426   1.1    itojun #endif
   1427   1.7   msaitoh 		}
   1428   1.1    itojun 
   1429   1.7   msaitoh 		sc->sc_st_check = 1;
   1430   1.7   msaitoh 	}
   1431   1.1    itojun #endif
   1432   1.1    itojun 
   1433   1.1    itojun 	/*
   1434   1.1    itojun 	 * Done handling any receive interrupts. See if data can be
   1435   1.1    itojun 	 * transmitted as well. Schedule tx done event if no data left
   1436   1.1    itojun 	 * and tty was marked busy.
   1437   1.1    itojun 	 */
   1438  1.37       uwe 	if (((scif_fdr_read() & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */
   1439   1.1    itojun 		/*
   1440   1.1    itojun 		 * If we've delayed a parameter change, do it now, and restart
   1441   1.1    itojun 		 * output.
   1442   1.1    itojun 		 */
   1443   1.1    itojun 		if (sc->sc_heldchange) {
   1444   1.1    itojun 			sc->sc_heldchange = 0;
   1445   1.1    itojun 			sc->sc_tbc = sc->sc_heldtbc;
   1446   1.1    itojun 			sc->sc_heldtbc = 0;
   1447   1.1    itojun 		}
   1448   1.1    itojun 
   1449   1.1    itojun 		/* Output the next chunk of the contiguous buffer, if any. */
   1450   1.1    itojun 		if (sc->sc_tbc > 0) {
   1451   1.1    itojun 			int n;
   1452   1.1    itojun 			int max;
   1453   1.1    itojun 			int i;
   1454   1.1    itojun 
   1455   1.1    itojun 			n = sc->sc_tbc;
   1456   1.1    itojun 			max = sc->sc_fifolen -
   1457  1.37       uwe 				((scif_fdr_read() & SCFDR2_TXCNT) >> 8);
   1458   1.1    itojun 			if (n > max)
   1459   1.1    itojun 				n = max;
   1460   1.1    itojun 
   1461   1.1    itojun 			for (i = 0; i < n; i++) {
   1462  1.14   msaitoh 				scif_putc(*(sc->sc_tba));
   1463   1.1    itojun 				sc->sc_tba++;
   1464   1.1    itojun 			}
   1465   1.1    itojun 			sc->sc_tbc -= n;
   1466   1.1    itojun 		} else {
   1467   1.1    itojun 			/* Disable transmit completion interrupts if necessary. */
   1468   1.1    itojun #if 0
   1469   1.1    itojun 			if (ISSET(sc->sc_ier, IER_ETXRDY))
   1470   1.1    itojun #endif
   1471  1.37       uwe 				scif_scr_write(scif_scr_read() & ~SCSCR2_TIE);
   1472   1.1    itojun 
   1473   1.1    itojun 			if (sc->sc_tx_busy) {
   1474   1.1    itojun 				sc->sc_tx_busy = 0;
   1475   1.1    itojun 				sc->sc_tx_done = 1;
   1476   1.1    itojun 			}
   1477   1.1    itojun 		}
   1478   1.1    itojun 	}
   1479   1.1    itojun 
   1480   1.1    itojun 	/* Wake up the poller. */
   1481  1.15   thorpej #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS
   1482   1.1    itojun 	softintr_schedule(sc->sc_si);
   1483   1.1    itojun #else
   1484   1.1    itojun #ifndef __NO_SOFT_SERIAL_INTERRUPT
   1485   1.1    itojun 	setsoftserial();
   1486   1.1    itojun #else
   1487   1.1    itojun 	if (!scif_softintr_scheduled) {
   1488   1.1    itojun 		scif_softintr_scheduled = 1;
   1489   1.8   thorpej 		callout_reset(&scif_soft_ch, 1, scifsoft, NULL);
   1490   1.1    itojun 	}
   1491   1.1    itojun #endif
   1492   1.1    itojun #endif
   1493   1.1    itojun 
   1494   1.1    itojun #if NRND > 0 && defined(RND_SCIF)
   1495  1.36       uwe 	rnd_add_uint32(&sc->rnd_source, iir | lsr);
   1496   1.1    itojun #endif
   1497   1.1    itojun 
   1498   1.1    itojun 	return (1);
   1499   1.1    itojun }
   1500   1.1    itojun 
   1501   1.1    itojun void
   1502  1.20       uch scifcnprobe(struct consdev *cp)
   1503   1.1    itojun {
   1504   1.1    itojun 	int maj;
   1505   1.1    itojun 
   1506   1.1    itojun 	/* locate the major number */
   1507  1.28   gehenna 	maj = cdevsw_lookup_major(&scif_cdevsw);
   1508   1.1    itojun 
   1509   1.1    itojun 	/* Initialize required fields. */
   1510   1.1    itojun 	cp->cn_dev = makedev(maj, 0);
   1511   1.4   msaitoh #ifdef SCIFCONSOLE
   1512   1.4   msaitoh 	cp->cn_pri = CN_REMOTE;
   1513   1.4   msaitoh #else
   1514   1.1    itojun 	cp->cn_pri = CN_NORMAL;
   1515   1.1    itojun #endif
   1516   1.1    itojun }
   1517   1.1    itojun 
   1518   1.1    itojun void
   1519  1.20       uch scifcninit(struct consdev *cp)
   1520   1.1    itojun {
   1521   1.1    itojun 
   1522   1.7   msaitoh 	InitializeScif(scifcn_speed);
   1523   1.9   msaitoh 	scifisconsole = 1;
   1524   1.1    itojun }
   1525   1.1    itojun 
   1526   1.1    itojun int
   1527  1.20       uch scifcngetc(dev_t dev)
   1528   1.1    itojun {
   1529   1.1    itojun 	int c;
   1530   1.1    itojun 	int s;
   1531   1.1    itojun 
   1532   1.1    itojun 	s = splserial();
   1533   1.1    itojun 	c = scif_getc();
   1534   1.1    itojun 	splx(s);
   1535   1.1    itojun 
   1536   1.1    itojun 	return (c);
   1537   1.1    itojun }
   1538   1.1    itojun 
   1539   1.1    itojun void
   1540  1.20       uch scifcnputc(dev_t dev, int c)
   1541   1.1    itojun {
   1542   1.1    itojun 	int s;
   1543   1.1    itojun 
   1544   1.1    itojun 	s = splserial();
   1545  1.14   msaitoh 	scif_putc((u_char)c);
   1546   1.1    itojun 	splx(s);
   1547   1.1    itojun }
   1548  1.22       uch 
   1549  1.22       uch #ifdef KGDB
   1550  1.22       uch int
   1551  1.22       uch scif_kgdb_init()
   1552  1.22       uch {
   1553  1.22       uch 
   1554  1.22       uch 	if (strcmp(kgdb_devname, "scif") != 0)
   1555  1.22       uch 		return (1);
   1556  1.22       uch 
   1557  1.22       uch 	if (scifisconsole)
   1558  1.22       uch 		return (1);	/* can't share with console */
   1559  1.22       uch 
   1560  1.22       uch 	InitializeScif(kgdb_rate);
   1561  1.22       uch 
   1562  1.22       uch 	kgdb_attach((int (*)(void *))scifcngetc,
   1563  1.22       uch 	    (void (*)(void *, int))scifcnputc, NULL);
   1564  1.22       uch 	kgdb_dev = 123; /* unneeded, only to satisfy some tests */
   1565  1.22       uch 	kgdb_attached = 1;
   1566  1.25       uch 
   1567  1.22       uch 	return (0);
   1568  1.22       uch }
   1569  1.22       uch #endif /* KGDB */
   1570