scif.c revision 1.10
1 /* $NetBSD: scif.c,v 1.10 2000/06/19 09:30:35 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Charles M. Hannum. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the NetBSD 47 * Foundation, Inc. and its contributors. 48 * 4. Neither the name of The NetBSD Foundation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 53 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 54 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * Copyright (c) 1991 The Regents of the University of California. 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. All advertising materials mentioning features or use of this software 78 * must display the following acknowledgement: 79 * This product includes software developed by the University of 80 * California, Berkeley and its contributors. 81 * 4. Neither the name of the University nor the names of its contributors 82 * may be used to endorse or promote products derived from this software 83 * without specific prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 86 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 88 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 89 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 90 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 91 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 92 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 93 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 94 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 95 * SUCH DAMAGE. 96 * 97 * @(#)com.c 7.5 (Berkeley) 5/16/91 98 */ 99 100 /* 101 * SH internal serial driver 102 * 103 * This code is derived from both z8530tty.c and com.c 104 */ 105 106 #include "opt_pclock.h" 107 #include "opt_scif.h" 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/tty.h> 112 #include <sys/proc.h> 113 #include <sys/conf.h> 114 #include <sys/file.h> 115 #include <sys/syslog.h> 116 #include <sys/kernel.h> 117 #include <sys/device.h> 118 #include <sys/malloc.h> 119 120 #include <dev/cons.h> 121 122 #include <machine/cpu.h> 123 #include <sh3/scifreg.h> 124 #include <sh3/tmureg.h> 125 126 #include <machine/shbvar.h> 127 128 static void scifstart __P((struct tty *)); 129 static int scifparam __P((struct tty *, struct termios *)); 130 131 void scifcnprobe __P((struct consdev *)); 132 void scifcninit __P((struct consdev *)); 133 void scifcnputc __P((dev_t, int)); 134 int scifcngetc __P((dev_t)); 135 void scifcnpoolc __P((dev_t, int)); 136 void scif_intr_init __P((void)); 137 int scifintr __P((void *)); 138 139 struct scif_softc { 140 struct device sc_dev; /* boilerplate */ 141 struct tty *sc_tty; 142 void *sc_ih; 143 144 struct callout sc_diag_ch; 145 146 #if 0 147 bus_space_tag_t sc_iot; /* ISA i/o space identifier */ 148 bus_space_handle_t sc_ioh; /* ISA io handle */ 149 150 int sc_drq; 151 152 int sc_frequency; 153 #endif 154 155 u_int sc_overflows, 156 sc_floods, 157 sc_errors; /* number of retries so far */ 158 u_char sc_status[7]; /* copy of registers */ 159 160 int sc_hwflags; 161 int sc_swflags; 162 u_int sc_fifolen; 163 164 u_int sc_r_hiwat, 165 sc_r_lowat; 166 u_char *volatile sc_rbget, 167 *volatile sc_rbput; 168 volatile u_int sc_rbavail; 169 u_char *sc_rbuf, 170 *sc_ebuf; 171 172 u_char *sc_tba; /* transmit buffer address */ 173 u_int sc_tbc, /* transmit byte count */ 174 sc_heldtbc; 175 176 volatile u_char sc_rx_flags, 177 #define RX_TTY_BLOCKED 0x01 178 #define RX_TTY_OVERFLOWED 0x02 179 #define RX_IBUF_BLOCKED 0x04 180 #define RX_IBUF_OVERFLOWED 0x08 181 #define RX_ANY_BLOCK 0x0f 182 sc_tx_busy, /* working on an output chunk */ 183 sc_tx_done, /* done with one output chunk */ 184 sc_tx_stopped, /* H/W level stop (lost CTS) */ 185 sc_st_check, /* got a status interrupt */ 186 sc_rx_ready; 187 188 volatile u_char sc_heldchange; 189 }; 190 191 /* controller driver configuration */ 192 static int scif_match __P((struct device *, struct cfdata *, void *)); 193 static void scif_attach __P((struct device *, struct device *, void *)); 194 195 void scif_break __P((struct scif_softc *, int)); 196 void scif_iflush __P((struct scif_softc *)); 197 198 #define integrate static inline 199 #ifdef __GENERIC_SOFT_INTERRUPTS 200 void scifsoft __P((void *)); 201 #else 202 #ifndef __NO_SOFT_SERIAL_INTERRUPT 203 void scifsoft __P((void)); 204 #else 205 void scifsoft __P((void *)); 206 #endif 207 #endif 208 integrate void scif_rxsoft __P((struct scif_softc *, struct tty *)); 209 integrate void scif_txsoft __P((struct scif_softc *, struct tty *)); 210 integrate void scif_stsoft __P((struct scif_softc *, struct tty *)); 211 integrate void scif_schedrx __P((struct scif_softc *)); 212 void scifdiag __P((void *)); 213 214 215 #define SCIFUNIT_MASK 0x7ffff 216 #define SCIFDIALOUT_MASK 0x80000 217 218 #define SCIFUNIT(x) (minor(x) & SCIFUNIT_MASK) 219 #define SCIFDIALOUT(x) (minor(x) & SCIFDIALOUT_MASK) 220 221 /* Macros to clear/set/test flags. */ 222 #define SET(t, f) (t) |= (f) 223 #define CLR(t, f) (t) &= ~(f) 224 #define ISSET(t, f) ((t) & (f)) 225 226 /* Hardware flag masks */ 227 #define SCIF_HW_NOIEN 0x01 228 #define SCIF_HW_FIFO 0x02 229 #define SCIF_HW_FLOW 0x08 230 #define SCIF_HW_DEV_OK 0x20 231 #define SCIF_HW_CONSOLE 0x40 232 #define SCIF_HW_KGDB 0x80 233 234 /* Buffer size for character buffer */ 235 #define SCIF_RING_SIZE 2048 236 237 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 238 u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4; 239 u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4; 240 241 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 242 int scifconscflag = CONMODE; 243 int scifisconsole = 0; 244 245 #ifdef SCIFCN_SPEED 246 unsigned int scifcn_speed = SCIFCN_SPEED; 247 #else 248 unsigned int scifcn_speed = 9600; 249 #endif 250 251 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 252 253 #ifndef __GENERIC_SOFT_INTERRUPTS 254 #ifdef __NO_SOFT_SERIAL_INTERRUPT 255 volatile int scif_softintr_scheduled; 256 struct callout scif_soft_ch = CALLOUT_INITIALIZER; 257 #endif 258 #endif 259 260 u_int scif_rbuf_size = SCIF_RING_SIZE; 261 262 struct cfattach scif_ca = { 263 sizeof(struct scif_softc), scif_match, scif_attach 264 }; 265 266 extern struct cfdriver scif_cd; 267 268 cdev_decl(scif); 269 270 void InitializeScif __P((unsigned int)); 271 272 /* 273 * following functions are debugging prupose only 274 */ 275 #define CR 0x0D 276 #define USART_ON (unsigned int)~0x08 277 278 static void WaitFor __P((int)); 279 void PutcScif __P((unsigned char)); 280 void PutStrScif __P((unsigned char *)); 281 int ScifErrCheck __P((void)); 282 unsigned char GetcScif __P((void)); 283 int GetStrScif __P((unsigned char *, int)); 284 285 /* 286 * WaitFor 287 * : int mSec; 288 */ 289 static void 290 WaitFor(mSec) 291 int mSec; 292 { 293 294 /* Disable Under Flow interrupt, rising edge, 1/4 */ 295 SHREG_TCR2 = 0x0000; 296 297 /* Set counter value (count down with 4 KHz) */ 298 SHREG_TCNT2 = mSec * 4; 299 300 /* start Channel2 */ 301 SHREG_TSTR |= TSTR_STR2; 302 303 /* wait for under flag ON of channel2 */ 304 while ((SHREG_TCR2 & TCR_UNF) == 0) 305 ; 306 307 /* stop channel2 */ 308 SHREG_TSTR &= ~TSTR_STR2; 309 } 310 311 /* 312 * InitializeScif 313 * : unsigned int bps; 314 * : SCIF(Serial Communication Interface) 315 */ 316 317 void 318 InitializeScif(bps) 319 unsigned int bps; 320 { 321 322 /* Initialize SCR */ 323 SHREG_SCSCR2 = 0x00; 324 325 #if 0 326 SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE; 327 #else 328 SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST; 329 #endif 330 /* Serial Mode Register */ 331 SHREG_SCSMR2 = 0x00; /* 8bit,NonParity,Even,1Stop */ 332 333 /* Bit Rate Register */ 334 SHREG_SCBRR2 = divrnd(PCLOCK, 32 * bps) - 1; 335 336 /* 337 * wait 1mSec, because Send/Recv must begin 1 bit period after 338 * BRR is set. 339 */ 340 WaitFor(1); 341 342 #if 0 343 SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE; 344 #else 345 SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1; 346 #endif 347 348 /* Send permission, Recieve permission ON */ 349 SHREG_SCSCR2 = SCSCR2_TE | SCSCR2_RE; 350 351 /* Serial Status Register */ 352 SHREG_SCSSR2 &= SCSSR2_TDFE; /* Clear Status */ 353 } 354 355 356 /* 357 * PutcScif 358 * : unsigned char c; 359 */ 360 361 void 362 PutcScif(c) 363 unsigned char c; 364 { 365 366 /* wait for ready */ 367 while ((SHREG_SCFDR2 & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) 368 ; 369 370 /* write send data to send register */ 371 SHREG_SCFTDR2 = c; 372 373 /* clear ready flag */ 374 SHREG_SCSSR2 &= ~(SCSSR2_TDFE | SCSSR2_TEND); 375 376 if (c == '\n') { 377 while ((SHREG_SCFDR2 & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) 378 ; 379 380 SHREG_SCFTDR2 = '\r'; 381 382 SHREG_SCSSR2 &= ~(SCSSR2_TDFE | SCSSR2_TEND); 383 } 384 } 385 386 /* 387 * PutStrScif 388 * : unsigned char *s; 389 */ 390 void 391 PutStrScif(s) 392 unsigned char *s; 393 { 394 395 while (*s) 396 PutcScif(*s++); 397 } 398 399 /* 400 * : ScifErrCheck 401 * 0x80 = error 402 * 0x08 = frame error 403 * 0x04 = parity error 404 */ 405 int 406 ScifErrCheck(void) 407 { 408 409 return(SHREG_SCSSR2 & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)); 410 } 411 412 /* 413 * GetcScif 414 */ 415 #if 0 416 /* Old code */ 417 unsigned char 418 GetcScif(void) 419 { 420 unsigned char c, err_c; 421 422 while (((err_c = SHREG_SCSSR2) 423 & (SCSSR2_RDF | SCSSR2_ER | SCSSR2_FER | SCSSR2_PER | SCSSR2_DR)) == 0) 424 ; 425 if ((err_c & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)) != 0) { 426 SHREG_SCSSR2 &= ~SCSSR2_ER; 427 return(err_c |= 0x80); 428 } 429 430 c = SHREG_SCFRDR2; 431 432 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR); 433 434 return(c); 435 } 436 #else 437 unsigned char 438 GetcScif(void) 439 { 440 unsigned char c, err_c; 441 442 /* wait for ready */ 443 while ((SHREG_SCFDR2 & SCFDR2_RECVCNT) == 0) 444 ; 445 err_c = SHREG_SCSSR2; 446 if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) != 0) 447 return(err_c |= 0x80); 448 449 c = SHREG_SCFRDR2; 450 451 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF | SCSSR2_DR); 452 453 return(c); 454 } 455 #endif 456 457 /* 458 * GetStrScif 459 * : unsigned char *s; 460 * : int size; 461 */ 462 int 463 GetStrScif(s, size) 464 unsigned char *s; 465 int size; 466 { 467 468 for (; size ; size--) { 469 *s = GetcScif(); 470 if (*s & 0x80) 471 return -1; 472 if (*s == CR) { 473 *s = 0; 474 break; 475 } 476 s++; 477 } 478 if (size == 0) 479 *s = 0; 480 return 0; 481 } 482 483 #if 0 484 #define SCIF_MAX_UNITS 2 485 #else 486 #define SCIF_MAX_UNITS 1 487 #endif 488 489 490 static int 491 scif_match(parent, cfp, aux) 492 struct device *parent; 493 struct cfdata *cfp; 494 void *aux; 495 { 496 struct shb_attach_args *sa = aux; 497 498 if (strcmp(cfp->cf_driver->cd_name, "scif") 499 || cfp->cf_unit >= SCIF_MAX_UNITS) 500 return 0; 501 502 sa->ia_iosize = 0x10; 503 return 1; 504 } 505 506 static void 507 scif_attach(parent, self, aux) 508 struct device *parent, *self; 509 void *aux; 510 { 511 struct scif_softc *sc = (struct scif_softc *)self; 512 struct tty *tp; 513 int irq; 514 struct shb_attach_args *ia = aux; 515 516 sc->sc_hwflags = 0; /* XXX */ 517 sc->sc_swflags = 0; /* XXX */ 518 sc->sc_fifolen = 16; 519 520 irq = ia->ia_irq; 521 522 if (scifisconsole) { 523 /* InitializeScif(scifcn_speed); */ 524 SET(sc->sc_hwflags, SCIF_HW_CONSOLE); 525 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 526 printf("\n%s: console\n", sc->sc_dev.dv_xname); 527 } else { 528 InitializeScif(9600); 529 printf("\n"); 530 } 531 532 callout_init(&sc->sc_diag_ch); 533 534 #if 0 535 if (irq != IRQUNK) { 536 sc->sc_ih = shb_intr_establish(irq, 537 IST_EDGE, IPL_SERIAL, scifintr, sc); 538 } 539 #else 540 if (irq != IRQUNK) { 541 sc->sc_ih = shb_intr_establish(SCIF_IRQ, 542 IST_EDGE, IPL_SERIAL, scifintr, sc); 543 } 544 #endif 545 546 SET(sc->sc_hwflags, SCIF_HW_DEV_OK); 547 548 tp = ttymalloc(); 549 tp->t_oproc = scifstart; 550 tp->t_param = scifparam; 551 tp->t_hwiflow = NULL; 552 553 sc->sc_tty = tp; 554 sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 555 if (sc->sc_rbuf == NULL) { 556 printf("%s: unable to allocate ring buffer\n", 557 sc->sc_dev.dv_xname); 558 return; 559 } 560 sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1); 561 562 tty_attach(tp); 563 } 564 565 /* 566 * Start or restart transmission. 567 */ 568 static void 569 scifstart(tp) 570 struct tty *tp; 571 { 572 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 573 int s; 574 575 s = spltty(); 576 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 577 goto out; 578 if (sc->sc_tx_stopped) 579 goto out; 580 581 if (tp->t_outq.c_cc <= tp->t_lowat) { 582 if (ISSET(tp->t_state, TS_ASLEEP)) { 583 CLR(tp->t_state, TS_ASLEEP); 584 wakeup(&tp->t_outq); 585 } 586 selwakeup(&tp->t_wsel); 587 if (tp->t_outq.c_cc == 0) 588 goto out; 589 } 590 591 /* Grab the first contiguous region of buffer space. */ 592 { 593 u_char *tba; 594 int tbc; 595 596 tba = tp->t_outq.c_cf; 597 tbc = ndqb(&tp->t_outq, 0); 598 599 (void)splserial(); 600 601 sc->sc_tba = tba; 602 sc->sc_tbc = tbc; 603 } 604 605 SET(tp->t_state, TS_BUSY); 606 sc->sc_tx_busy = 1; 607 608 /* Enable transmit completion interrupts if necessary. */ 609 SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE; 610 611 /* Output the first chunk of the contiguous buffer. */ 612 { 613 int n; 614 int max; 615 int i; 616 617 n = sc->sc_tbc; 618 max = sc->sc_fifolen - ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8); 619 if (n > max) 620 n = max; 621 622 for (i = 0; i < n; i++) { 623 PutcScif(*(sc->sc_tba)); 624 sc->sc_tba++; 625 } 626 sc->sc_tbc -= n; 627 } 628 out: 629 splx(s); 630 return; 631 } 632 633 /* 634 * Set SCIF tty parameters from termios. 635 * XXX - Should just copy the whole termios after 636 * making sure all the changes could be done. 637 */ 638 static int 639 scifparam(tp, t) 640 struct tty *tp; 641 struct termios *t; 642 { 643 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 644 int ospeed = t->c_ospeed; 645 int s; 646 647 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 648 return (EIO); 649 650 /* Check requested parameters. */ 651 if (ospeed < 0) 652 return (EINVAL); 653 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 654 return (EINVAL); 655 656 /* 657 * For the console, always force CLOCAL and !HUPCL, so that the port 658 * is always active. 659 */ 660 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 661 ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 662 SET(t->c_cflag, CLOCAL); 663 CLR(t->c_cflag, HUPCL); 664 } 665 666 /* 667 * If there were no changes, don't do anything. This avoids dropping 668 * input and improves performance when all we did was frob things like 669 * VMIN and VTIME. 670 */ 671 if (tp->t_ospeed == t->c_ospeed && 672 tp->t_cflag == t->c_cflag) 673 return (0); 674 675 #if 0 676 /* XXX (msaitoh) */ 677 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 678 #endif 679 680 s = splserial(); 681 682 /* 683 * Set the flow control pins depending on the current flow control 684 * mode. 685 */ 686 if (ISSET(t->c_cflag, CRTSCTS)) { 687 SHREG_SCFCR2 |= SCFCR2_MCE; 688 } else { 689 SHREG_SCFCR2 &= ~SCFCR2_MCE; 690 } 691 692 SHREG_SCBRR2 = divrnd(PCLOCK, 32 * ospeed) -1; 693 694 /* 695 * Set the FIFO threshold based on the receive speed. 696 * 697 * * If it's a low speed, it's probably a mouse or some other 698 * interactive device, so set the threshold low. 699 * * If it's a high speed, trim the trigger level down to prevent 700 * overflows. 701 * * Otherwise set it a bit higher. 702 */ 703 #if 0 704 /* XXX (msaitoh) */ 705 if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP)) 706 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 707 else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO)) 708 sc->sc_fifo = FIFO_ENABLE | 709 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : 710 t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4); 711 else 712 sc->sc_fifo = 0; 713 #endif 714 715 /* And copy to tty. */ 716 tp->t_ispeed = 0; 717 tp->t_ospeed = t->c_ospeed; 718 tp->t_cflag = t->c_cflag; 719 720 if (!sc->sc_heldchange) { 721 if (sc->sc_tx_busy) { 722 sc->sc_heldtbc = sc->sc_tbc; 723 sc->sc_tbc = 0; 724 sc->sc_heldchange = 1; 725 } 726 #if 0 727 /* XXX (msaitoh) */ 728 else 729 scif_loadchannelregs(sc); 730 #endif 731 } 732 733 if (!ISSET(t->c_cflag, CHWFLOW)) { 734 /* Disable the high water mark. */ 735 sc->sc_r_hiwat = 0; 736 sc->sc_r_lowat = 0; 737 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 738 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 739 scif_schedrx(sc); 740 } 741 } else { 742 sc->sc_r_hiwat = scif_rbuf_hiwat; 743 sc->sc_r_lowat = scif_rbuf_lowat; 744 } 745 746 splx(s); 747 748 #ifdef SCIF_DEBUG 749 if (scif_debug) 750 scifstatus(sc, "scifparam "); 751 #endif 752 753 if (!ISSET(t->c_cflag, CHWFLOW)) { 754 if (sc->sc_tx_stopped) { 755 sc->sc_tx_stopped = 0; 756 scifstart(tp); 757 } 758 } 759 760 return (0); 761 } 762 763 void 764 scif_iflush(sc) 765 struct scif_softc *sc; 766 { 767 int i; 768 unsigned char c; 769 770 i = SHREG_SCFDR2 & SCFDR2_RECVCNT; 771 772 while (i > 0) { 773 c = SHREG_SCFRDR2; 774 SHREG_SCSSR2 &= ~(SCSSR2_RDF | SCSSR2_DR); 775 i--; 776 } 777 } 778 779 int scif_getc __P((void)); 780 void scif_putc __P((int)); 781 782 int 783 scif_getc() 784 { 785 786 return (GetcScif()); 787 } 788 789 void 790 scif_putc(int c) 791 { 792 793 PutcScif(c); 794 } 795 796 int 797 scifopen(dev, flag, mode, p) 798 dev_t dev; 799 int flag, mode; 800 struct proc *p; 801 { 802 int unit = SCIFUNIT(dev); 803 struct scif_softc *sc; 804 struct tty *tp; 805 int s, s2; 806 int error; 807 808 if (unit >= scif_cd.cd_ndevs) 809 return (ENXIO); 810 sc = scif_cd.cd_devs[unit]; 811 if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) || 812 sc->sc_rbuf == NULL) 813 return (ENXIO); 814 815 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 816 return (ENXIO); 817 818 #ifdef KGDB 819 /* 820 * If this is the kgdb port, no other use is permitted. 821 */ 822 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) 823 return (EBUSY); 824 #endif 825 826 tp = sc->sc_tty; 827 828 if (ISSET(tp->t_state, TS_ISOPEN) && 829 ISSET(tp->t_state, TS_XCLUDE) && 830 p->p_ucred->cr_uid != 0) 831 return (EBUSY); 832 833 s = spltty(); 834 835 /* 836 * Do the following iff this is a first open. 837 */ 838 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 839 struct termios t; 840 841 tp->t_dev = dev; 842 843 s2 = splserial(); 844 845 /* Turn on interrupts. */ 846 SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE; 847 848 splx(s2); 849 850 /* 851 * Initialize the termios status to the defaults. Add in the 852 * sticky bits from TIOCSFLAGS. 853 */ 854 t.c_ispeed = 0; 855 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 856 t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */ 857 t.c_cflag = scifconscflag; 858 } else { 859 t.c_ospeed = TTYDEF_SPEED; 860 t.c_cflag = TTYDEF_CFLAG; 861 } 862 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 863 SET(t.c_cflag, CLOCAL); 864 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 865 SET(t.c_cflag, CRTSCTS); 866 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 867 SET(t.c_cflag, MDMBUF); 868 /* Make sure scifparam() will do something. */ 869 tp->t_ospeed = 0; 870 (void) scifparam(tp, &t); 871 tp->t_iflag = TTYDEF_IFLAG; 872 tp->t_oflag = TTYDEF_OFLAG; 873 tp->t_lflag = TTYDEF_LFLAG; 874 ttychars(tp); 875 ttsetwater(tp); 876 877 s2 = splserial(); 878 879 /* Clear the input ring, and unblock. */ 880 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 881 sc->sc_rbavail = scif_rbuf_size; 882 scif_iflush(sc); 883 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 884 #if 0 885 /* XXX (msaitoh) */ 886 scif_hwiflow(sc); 887 #endif 888 889 #ifdef SCIF_DEBUG 890 if (scif_debug) 891 scifstatus(sc, "scifopen "); 892 #endif 893 894 splx(s2); 895 } 896 897 splx(s); 898 899 error = ttyopen(tp, SCIFDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 900 if (error) 901 goto bad; 902 903 error = (*linesw[tp->t_line].l_open)(dev, tp); 904 if (error) 905 goto bad; 906 907 return (0); 908 909 bad: 910 911 return (error); 912 } 913 914 int 915 scifclose(dev, flag, mode, p) 916 dev_t dev; 917 int flag, mode; 918 struct proc *p; 919 { 920 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 921 struct tty *tp = sc->sc_tty; 922 923 /* XXX This is for cons.c. */ 924 if (!ISSET(tp->t_state, TS_ISOPEN)) 925 return (0); 926 927 (*linesw[tp->t_line].l_close)(tp, flag); 928 ttyclose(tp); 929 930 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 931 return (0); 932 933 return (0); 934 } 935 936 int 937 scifread(dev, uio, flag) 938 dev_t dev; 939 struct uio *uio; 940 int flag; 941 { 942 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 943 struct tty *tp = sc->sc_tty; 944 945 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 946 } 947 948 int 949 scifwrite(dev, uio, flag) 950 dev_t dev; 951 struct uio *uio; 952 int flag; 953 { 954 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 955 struct tty *tp = sc->sc_tty; 956 957 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 958 } 959 960 struct tty * 961 sciftty(dev) 962 dev_t dev; 963 { 964 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 965 struct tty *tp = sc->sc_tty; 966 967 return (tp); 968 } 969 970 int 971 scifioctl(dev, cmd, data, flag, p) 972 dev_t dev; 973 u_long cmd; 974 caddr_t data; 975 int flag; 976 struct proc *p; 977 { 978 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 979 struct tty *tp = sc->sc_tty; 980 int error; 981 int s; 982 983 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 984 return (EIO); 985 986 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 987 if (error >= 0) 988 return (error); 989 990 error = ttioctl(tp, cmd, data, flag, p); 991 if (error >= 0) 992 return (error); 993 994 error = 0; 995 996 s = splserial(); 997 998 switch (cmd) { 999 case TIOCSBRK: 1000 scif_break(sc, 1); 1001 break; 1002 1003 case TIOCCBRK: 1004 scif_break(sc, 0); 1005 break; 1006 1007 case TIOCGFLAGS: 1008 *(int *)data = sc->sc_swflags; 1009 break; 1010 1011 case TIOCSFLAGS: 1012 error = suser(p->p_ucred, &p->p_acflag); 1013 if (error) 1014 break; 1015 sc->sc_swflags = *(int *)data; 1016 break; 1017 1018 default: 1019 error = ENOTTY; 1020 break; 1021 } 1022 1023 splx(s); 1024 1025 return (error); 1026 } 1027 1028 integrate void 1029 scif_schedrx(sc) 1030 struct scif_softc *sc; 1031 { 1032 1033 sc->sc_rx_ready = 1; 1034 1035 /* Wake up the poller. */ 1036 #ifdef __GENERIC_SOFT_INTERRUPTS 1037 softintr_schedule(sc->sc_si); 1038 #else 1039 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1040 setsoftserial(); 1041 #else 1042 if (!scif_softintr_scheduled) { 1043 scif_softintr_scheduled = 1; 1044 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 1045 } 1046 #endif 1047 #endif 1048 } 1049 1050 void 1051 scif_break(sc, onoff) 1052 struct scif_softc *sc; 1053 int onoff; 1054 { 1055 1056 if (onoff) 1057 SHREG_SCSSR2 &= ~SCSSR2_TDFE; 1058 else 1059 SHREG_SCSSR2 |= SCSSR2_TDFE; 1060 1061 #if 0 /* XXX */ 1062 if (!sc->sc_heldchange) { 1063 if (sc->sc_tx_busy) { 1064 sc->sc_heldtbc = sc->sc_tbc; 1065 sc->sc_tbc = 0; 1066 sc->sc_heldchange = 1; 1067 } else 1068 scif_loadchannelregs(sc); 1069 } 1070 #endif 1071 } 1072 1073 /* 1074 * Stop output, e.g., for ^S or output flush. 1075 */ 1076 void 1077 scifstop(tp, flag) 1078 struct tty *tp; 1079 int flag; 1080 { 1081 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 1082 int s; 1083 1084 s = splserial(); 1085 if (ISSET(tp->t_state, TS_BUSY)) { 1086 /* Stop transmitting at the next chunk. */ 1087 sc->sc_tbc = 0; 1088 sc->sc_heldtbc = 0; 1089 if (!ISSET(tp->t_state, TS_TTSTOP)) 1090 SET(tp->t_state, TS_FLUSH); 1091 } 1092 splx(s); 1093 } 1094 1095 void 1096 scif_intr_init() 1097 { 1098 /* XXX */ 1099 } 1100 1101 void 1102 scifdiag(arg) 1103 void *arg; 1104 { 1105 struct scif_softc *sc = arg; 1106 int overflows, floods; 1107 int s; 1108 1109 s = splserial(); 1110 overflows = sc->sc_overflows; 1111 sc->sc_overflows = 0; 1112 floods = sc->sc_floods; 1113 sc->sc_floods = 0; 1114 sc->sc_errors = 0; 1115 splx(s); 1116 1117 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1118 sc->sc_dev.dv_xname, 1119 overflows, overflows == 1 ? "" : "s", 1120 floods, floods == 1 ? "" : "s"); 1121 } 1122 1123 integrate void 1124 scif_rxsoft(sc, tp) 1125 struct scif_softc *sc; 1126 struct tty *tp; 1127 { 1128 int (*rint) __P((int c, struct tty *tp)) = linesw[tp->t_line].l_rint; 1129 u_char *get, *end; 1130 u_int cc, scc; 1131 u_char ssr2; 1132 int code; 1133 int s; 1134 1135 end = sc->sc_ebuf; 1136 get = sc->sc_rbget; 1137 scc = cc = scif_rbuf_size - sc->sc_rbavail; 1138 1139 if (cc == scif_rbuf_size) { 1140 sc->sc_floods++; 1141 if (sc->sc_errors++ == 0) 1142 callout(&sc->sc_diag_ch, 60 * hz, scifdiag, sc); 1143 } 1144 1145 while (cc) { 1146 code = get[0]; 1147 ssr2 = get[1]; 1148 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) { 1149 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER)) 1150 SET(code, TTY_FE); 1151 if (ISSET(ssr2, SCSSR2_PER)) 1152 SET(code, TTY_PE); 1153 } 1154 if ((*rint)(code, tp) == -1) { 1155 /* 1156 * The line discipline's buffer is out of space. 1157 */ 1158 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1159 /* 1160 * We're either not using flow control, or the 1161 * line discipline didn't tell us to block for 1162 * some reason. Either way, we have no way to 1163 * know when there's more space available, so 1164 * just drop the rest of the data. 1165 */ 1166 get += cc << 1; 1167 if (get >= end) 1168 get -= scif_rbuf_size << 1; 1169 cc = 0; 1170 } else { 1171 /* 1172 * Don't schedule any more receive processing 1173 * until the line discipline tells us there's 1174 * space available (through scifhwiflow()). 1175 * Leave the rest of the data in the input 1176 * buffer. 1177 */ 1178 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1179 } 1180 break; 1181 } 1182 get += 2; 1183 if (get >= end) 1184 get = sc->sc_rbuf; 1185 cc--; 1186 } 1187 1188 if (cc != scc) { 1189 sc->sc_rbget = get; 1190 s = splserial(); 1191 cc = sc->sc_rbavail += scc - cc; 1192 /* Buffers should be ok again, release possible block. */ 1193 if (cc >= sc->sc_r_lowat) { 1194 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1195 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1196 SHREG_SCSCR2 |= SCSCR2_RIE; 1197 } 1198 #if 0 1199 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1200 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1201 scif_hwiflow(sc); 1202 } 1203 #endif 1204 } 1205 splx(s); 1206 } 1207 } 1208 1209 integrate void 1210 scif_txsoft(sc, tp) 1211 struct scif_softc *sc; 1212 struct tty *tp; 1213 { 1214 1215 CLR(tp->t_state, TS_BUSY); 1216 if (ISSET(tp->t_state, TS_FLUSH)) 1217 CLR(tp->t_state, TS_FLUSH); 1218 else 1219 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1220 (*linesw[tp->t_line].l_start)(tp); 1221 } 1222 1223 integrate void 1224 scif_stsoft(sc, tp) 1225 struct scif_softc *sc; 1226 struct tty *tp; 1227 { 1228 #if 0 1229 /* XXX (msaitoh) */ 1230 u_char msr, delta; 1231 int s; 1232 1233 s = splserial(); 1234 msr = sc->sc_msr; 1235 delta = sc->sc_msr_delta; 1236 sc->sc_msr_delta = 0; 1237 splx(s); 1238 1239 if (ISSET(delta, sc->sc_msr_dcd)) { 1240 /* 1241 * Inform the tty layer that carrier detect changed. 1242 */ 1243 (void) (*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)); 1244 } 1245 1246 if (ISSET(delta, sc->sc_msr_cts)) { 1247 /* Block or unblock output according to flow control. */ 1248 if (ISSET(msr, sc->sc_msr_cts)) { 1249 sc->sc_tx_stopped = 0; 1250 (*linesw[tp->t_line].l_start)(tp); 1251 } else { 1252 sc->sc_tx_stopped = 1; 1253 } 1254 } 1255 1256 #ifdef SCIF_DEBUG 1257 if (scif_debug) 1258 scifstatus(sc, "scif_stsoft"); 1259 #endif 1260 #endif 1261 } 1262 1263 #ifdef __GENERIC_SOFT_INTERRUPTS 1264 void 1265 scifsoft(arg) 1266 void *arg; 1267 { 1268 struct scif_softc *sc = arg; 1269 struct tty *tp; 1270 1271 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1272 return; 1273 1274 { 1275 #else 1276 void 1277 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1278 scifsoft() 1279 #else 1280 scifsoft(arg) 1281 void *arg; 1282 #endif 1283 { 1284 struct scif_softc *sc; 1285 struct tty *tp; 1286 int unit; 1287 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1288 int s; 1289 1290 s = splsoftserial(); 1291 scif_softintr_scheduled = 0; 1292 #endif 1293 1294 for (unit = 0; unit < scif_cd.cd_ndevs; unit++) { 1295 sc = scif_cd.cd_devs[unit]; 1296 if (sc == NULL || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK)) 1297 continue; 1298 1299 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1300 continue; 1301 1302 tp = sc->sc_tty; 1303 if (tp == NULL) 1304 continue; 1305 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 1306 continue; 1307 #endif 1308 tp = sc->sc_tty; 1309 1310 if (sc->sc_rx_ready) { 1311 sc->sc_rx_ready = 0; 1312 scif_rxsoft(sc, tp); 1313 } 1314 1315 #if 0 1316 if (sc->sc_st_check) { 1317 sc->sc_st_check = 0; 1318 scif_stsoft(sc, tp); 1319 } 1320 #endif 1321 1322 if (sc->sc_tx_done) { 1323 sc->sc_tx_done = 0; 1324 scif_txsoft(sc, tp); 1325 } 1326 } 1327 1328 #ifndef __GENERIC_SOFT_INTERRUPTS 1329 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1330 splx(s); 1331 #endif 1332 #endif 1333 } 1334 1335 int 1336 scifintr(arg) 1337 void *arg; 1338 { 1339 struct scif_softc *sc = arg; 1340 u_char *put, *end; 1341 u_int cc; 1342 u_short ssr2; 1343 int count; 1344 1345 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1346 return (0); 1347 1348 end = sc->sc_ebuf; 1349 put = sc->sc_rbput; 1350 cc = sc->sc_rbavail; 1351 1352 ssr2 = SHREG_SCSSR2; 1353 if (ISSET(ssr2, SCSSR2_BRK)) { 1354 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR); 1355 #if defined(DDB) || defined(KGDB) 1356 #ifdef DDB 1357 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 1358 console_debugger(); 1359 } 1360 #endif 1361 #ifdef KGDB 1362 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) { 1363 kgdb_connect(1); 1364 } 1365 #endif 1366 #endif /* DDB || KGDB */ 1367 } 1368 count = SHREG_SCFDR2 & SCFDR2_RECVCNT; 1369 if (count != 0) { 1370 while ((cc > 0) && (count > 0)) { 1371 put[0] = SHREG_SCFRDR2; 1372 put[1] = (u_char)(SHREG_SCSSR2 & 0x00ff); 1373 1374 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR); 1375 1376 put += 2; 1377 if (put >= end) 1378 put = sc->sc_rbuf; 1379 cc--; 1380 count--; 1381 } 1382 1383 /* 1384 * Current string of incoming characters ended because 1385 * no more data was available or we ran out of space. 1386 * Schedule a receive event if any data was received. 1387 * If we're out of space, turn off receive interrupts. 1388 */ 1389 sc->sc_rbput = put; 1390 sc->sc_rbavail = cc; 1391 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1392 sc->sc_rx_ready = 1; 1393 1394 /* 1395 * See if we are in danger of overflowing a buffer. If 1396 * so, use hardware flow control to ease the pressure. 1397 */ 1398 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1399 cc < sc->sc_r_hiwat) { 1400 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1401 #if 0 1402 scif_hwiflow(sc); 1403 #endif 1404 } 1405 1406 /* 1407 * If we're out of space, disable receive interrupts 1408 * until the queue has drained a bit. 1409 */ 1410 if (!cc) { 1411 SHREG_SCSCR2 &= ~SCSCR2_RIE; 1412 } 1413 } else { 1414 if (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR)) { 1415 SHREG_SCSCR2 &= ~(SCSCR2_TIE | SCSCR2_RIE); 1416 } 1417 } 1418 1419 #if 0 1420 msr = bus_space_read_1(iot, ioh, scif_msr); 1421 delta = msr ^ sc->sc_msr; 1422 sc->sc_msr = msr; 1423 if (ISSET(delta, sc->sc_msr_mask)) { 1424 SET(sc->sc_msr_delta, delta); 1425 1426 /* 1427 * Pulse-per-second clock signal on edge of DCD? 1428 */ 1429 if (ISSET(delta, sc->sc_ppsmask)) { 1430 struct timeval tv; 1431 if (ISSET(msr, sc->sc_ppsmask) == 1432 sc->sc_ppsassert) { 1433 /* XXX nanotime() */ 1434 microtime(&tv); 1435 TIMEVAL_TO_TIMESPEC(&tv, 1436 &sc->ppsinfo.assert_timestamp); 1437 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 1438 timespecadd(&sc->ppsinfo.assert_timestamp, 1439 &sc->ppsparam.assert_offset, 1440 &sc->ppsinfo.assert_timestamp); 1441 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp); 1442 } 1443 1444 #ifdef PPS_SYNC 1445 if (sc->ppsparam.mode & PPS_HARDPPSONASSERT) 1446 hardpps(&tv, tv.tv_usec); 1447 #endif 1448 sc->ppsinfo.assert_sequence++; 1449 sc->ppsinfo.current_mode = 1450 sc->ppsparam.mode; 1451 1452 } else if (ISSET(msr, sc->sc_ppsmask) == 1453 sc->sc_ppsclear) { 1454 /* XXX nanotime() */ 1455 microtime(&tv); 1456 TIMEVAL_TO_TIMESPEC(&tv, 1457 &sc->ppsinfo.clear_timestamp); 1458 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 1459 timespecadd(&sc->ppsinfo.clear_timestamp, 1460 &sc->ppsparam.clear_offset, 1461 &sc->ppsinfo.clear_timestamp); 1462 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp); 1463 } 1464 1465 #ifdef PPS_SYNC 1466 if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR) 1467 hardpps(&tv, tv.tv_usec); 1468 #endif 1469 sc->ppsinfo.clear_sequence++; 1470 sc->ppsinfo.current_mode = 1471 sc->ppsparam.mode; 1472 } 1473 } 1474 1475 /* 1476 * Stop output immediately if we lose the output 1477 * flow control signal or carrier detect. 1478 */ 1479 if (ISSET(~msr, sc->sc_msr_mask)) { 1480 sc->sc_tbc = 0; 1481 sc->sc_heldtbc = 0; 1482 #ifdef SCIF_DEBUG 1483 if (scif_debug) 1484 scifstatus(sc, "scifintr "); 1485 #endif 1486 } 1487 1488 sc->sc_st_check = 1; 1489 } 1490 #endif 1491 1492 /* 1493 * Done handling any receive interrupts. See if data can be 1494 * transmitted as well. Schedule tx done event if no data left 1495 * and tty was marked busy. 1496 */ 1497 if (((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */ 1498 /* 1499 * If we've delayed a parameter change, do it now, and restart 1500 * output. 1501 */ 1502 if (sc->sc_heldchange) { 1503 sc->sc_heldchange = 0; 1504 sc->sc_tbc = sc->sc_heldtbc; 1505 sc->sc_heldtbc = 0; 1506 } 1507 1508 /* Output the next chunk of the contiguous buffer, if any. */ 1509 if (sc->sc_tbc > 0) { 1510 int n; 1511 int max; 1512 int i; 1513 1514 n = sc->sc_tbc; 1515 max = sc->sc_fifolen - 1516 ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8); 1517 if (n > max) 1518 n = max; 1519 1520 for (i = 0; i < n; i++) { 1521 PutcScif(*(sc->sc_tba)); 1522 sc->sc_tba++; 1523 } 1524 sc->sc_tbc -= n; 1525 } else { 1526 /* Disable transmit completion interrupts if necessary. */ 1527 #if 0 1528 if (ISSET(sc->sc_ier, IER_ETXRDY)) 1529 #endif 1530 SHREG_SCSCR2 &= ~SCSCR2_TIE; 1531 1532 if (sc->sc_tx_busy) { 1533 sc->sc_tx_busy = 0; 1534 sc->sc_tx_done = 1; 1535 } 1536 } 1537 } 1538 1539 /* Wake up the poller. */ 1540 #ifdef __GENERIC_SOFT_INTERRUPTS 1541 softintr_schedule(sc->sc_si); 1542 #else 1543 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1544 setsoftserial(); 1545 #else 1546 if (!scif_softintr_scheduled) { 1547 scif_softintr_scheduled = 1; 1548 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 1549 } 1550 #endif 1551 #endif 1552 1553 #if NRND > 0 && defined(RND_SCIF) 1554 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1555 #endif 1556 1557 return (1); 1558 } 1559 1560 void 1561 scifcnprobe(cp) 1562 struct consdev *cp; 1563 { 1564 int maj; 1565 1566 /* locate the major number */ 1567 for (maj = 0; maj < nchrdev; maj++) 1568 if (cdevsw[maj].d_open == scifopen) 1569 break; 1570 1571 /* Initialize required fields. */ 1572 cp->cn_dev = makedev(maj, 0); 1573 #ifdef SCIFCONSOLE 1574 cp->cn_pri = CN_REMOTE; 1575 #else 1576 cp->cn_pri = CN_NORMAL; 1577 #endif 1578 } 1579 1580 #define scif_gets GetStrScif 1581 #define scif_puts PutStrScif 1582 1583 void 1584 scifcninit(cp) 1585 struct consdev *cp; 1586 { 1587 1588 InitializeScif(scifcn_speed); 1589 scifisconsole = 1; 1590 } 1591 1592 #define scif_getc GetcScif 1593 #define scif_putc PutcScif 1594 1595 int 1596 scifcngetc(dev) 1597 dev_t dev; 1598 { 1599 int c; 1600 int s; 1601 1602 s = splserial(); 1603 c = scif_getc(); 1604 splx(s); 1605 1606 return (c); 1607 } 1608 1609 void 1610 scifcnputc(dev, c) 1611 dev_t dev; 1612 int c; 1613 { 1614 int s; 1615 1616 s = splserial(); 1617 scif_putc(c); 1618 splx(s); 1619 } 1620
Indexes created Tue Sep 23 07:09:52 GMT 2025