scif.c revision 1.12
1 /* $NetBSD: scif.c,v 1.12 2000/10/31 01:08:41 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Charles M. Hannum. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the NetBSD 47 * Foundation, Inc. and its contributors. 48 * 4. Neither the name of The NetBSD Foundation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 53 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 54 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * Copyright (c) 1991 The Regents of the University of California. 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. All advertising materials mentioning features or use of this software 78 * must display the following acknowledgement: 79 * This product includes software developed by the University of 80 * California, Berkeley and its contributors. 81 * 4. Neither the name of the University nor the names of its contributors 82 * may be used to endorse or promote products derived from this software 83 * without specific prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 86 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 88 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 89 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 90 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 91 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 92 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 93 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 94 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 95 * SUCH DAMAGE. 96 * 97 * @(#)com.c 7.5 (Berkeley) 5/16/91 98 */ 99 100 /* 101 * SH internal serial driver 102 * 103 * This code is derived from both z8530tty.c and com.c 104 */ 105 106 #include "opt_pclock.h" 107 #include "opt_scif.h" 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/tty.h> 112 #include <sys/proc.h> 113 #include <sys/conf.h> 114 #include <sys/file.h> 115 #include <sys/syslog.h> 116 #include <sys/kernel.h> 117 #include <sys/device.h> 118 #include <sys/malloc.h> 119 120 #include <dev/cons.h> 121 122 #include <machine/cpu.h> 123 #include <sh3/scifreg.h> 124 #include <sh3/tmureg.h> 125 126 #include <machine/shbvar.h> 127 128 static void scifstart __P((struct tty *)); 129 static int scifparam __P((struct tty *, struct termios *)); 130 131 void scifcnprobe __P((struct consdev *)); 132 void scifcninit __P((struct consdev *)); 133 void scifcnputc __P((dev_t, int)); 134 int scifcngetc __P((dev_t)); 135 void scifcnpoolc __P((dev_t, int)); 136 void scif_intr_init __P((void)); 137 int scifintr __P((void *)); 138 139 struct scif_softc { 140 struct device sc_dev; /* boilerplate */ 141 struct tty *sc_tty; 142 void *sc_ih; 143 144 struct callout sc_diag_ch; 145 146 #if 0 147 bus_space_tag_t sc_iot; /* ISA i/o space identifier */ 148 bus_space_handle_t sc_ioh; /* ISA io handle */ 149 150 int sc_drq; 151 152 int sc_frequency; 153 #endif 154 155 u_int sc_overflows, 156 sc_floods, 157 sc_errors; /* number of retries so far */ 158 u_char sc_status[7]; /* copy of registers */ 159 160 int sc_hwflags; 161 int sc_swflags; 162 u_int sc_fifolen; 163 164 u_int sc_r_hiwat, 165 sc_r_lowat; 166 u_char *volatile sc_rbget, 167 *volatile sc_rbput; 168 volatile u_int sc_rbavail; 169 u_char *sc_rbuf, 170 *sc_ebuf; 171 172 u_char *sc_tba; /* transmit buffer address */ 173 u_int sc_tbc, /* transmit byte count */ 174 sc_heldtbc; 175 176 volatile u_char sc_rx_flags, 177 #define RX_TTY_BLOCKED 0x01 178 #define RX_TTY_OVERFLOWED 0x02 179 #define RX_IBUF_BLOCKED 0x04 180 #define RX_IBUF_OVERFLOWED 0x08 181 #define RX_ANY_BLOCK 0x0f 182 sc_tx_busy, /* working on an output chunk */ 183 sc_tx_done, /* done with one output chunk */ 184 sc_tx_stopped, /* H/W level stop (lost CTS) */ 185 sc_st_check, /* got a status interrupt */ 186 sc_rx_ready; 187 188 volatile u_char sc_heldchange; 189 }; 190 191 /* controller driver configuration */ 192 static int scif_match __P((struct device *, struct cfdata *, void *)); 193 static void scif_attach __P((struct device *, struct device *, void *)); 194 195 void scif_break __P((struct scif_softc *, int)); 196 void scif_iflush __P((struct scif_softc *)); 197 198 #define integrate static inline 199 #ifdef __GENERIC_SOFT_INTERRUPTS 200 void scifsoft __P((void *)); 201 #else 202 #ifndef __NO_SOFT_SERIAL_INTERRUPT 203 void scifsoft __P((void)); 204 #else 205 void scifsoft __P((void *)); 206 #endif 207 #endif 208 integrate void scif_rxsoft __P((struct scif_softc *, struct tty *)); 209 integrate void scif_txsoft __P((struct scif_softc *, struct tty *)); 210 integrate void scif_stsoft __P((struct scif_softc *, struct tty *)); 211 integrate void scif_schedrx __P((struct scif_softc *)); 212 void scifdiag __P((void *)); 213 214 215 #define SCIFUNIT_MASK 0x7ffff 216 #define SCIFDIALOUT_MASK 0x80000 217 218 #define SCIFUNIT(x) (minor(x) & SCIFUNIT_MASK) 219 #define SCIFDIALOUT(x) (minor(x) & SCIFDIALOUT_MASK) 220 221 /* Macros to clear/set/test flags. */ 222 #define SET(t, f) (t) |= (f) 223 #define CLR(t, f) (t) &= ~(f) 224 #define ISSET(t, f) ((t) & (f)) 225 226 /* Hardware flag masks */ 227 #define SCIF_HW_NOIEN 0x01 228 #define SCIF_HW_FIFO 0x02 229 #define SCIF_HW_FLOW 0x08 230 #define SCIF_HW_DEV_OK 0x20 231 #define SCIF_HW_CONSOLE 0x40 232 #define SCIF_HW_KGDB 0x80 233 234 /* Buffer size for character buffer */ 235 #define SCIF_RING_SIZE 2048 236 237 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 238 u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4; 239 u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4; 240 241 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 242 int scifconscflag = CONMODE; 243 int scifisconsole = 0; 244 245 #ifdef SCIFCN_SPEED 246 unsigned int scifcn_speed = SCIFCN_SPEED; 247 #else 248 unsigned int scifcn_speed = 9600; 249 #endif 250 251 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 252 253 #ifndef __GENERIC_SOFT_INTERRUPTS 254 #ifdef __NO_SOFT_SERIAL_INTERRUPT 255 volatile int scif_softintr_scheduled; 256 struct callout scif_soft_ch = CALLOUT_INITIALIZER; 257 #endif 258 #endif 259 260 u_int scif_rbuf_size = SCIF_RING_SIZE; 261 262 struct cfattach scif_ca = { 263 sizeof(struct scif_softc), scif_match, scif_attach 264 }; 265 266 extern struct cfdriver scif_cd; 267 268 cdev_decl(scif); 269 270 void InitializeScif __P((unsigned int)); 271 272 /* 273 * following functions are debugging prupose only 274 */ 275 #define CR 0x0D 276 #define USART_ON (unsigned int)~0x08 277 278 static void WaitFor __P((int)); 279 void PutcScif __P((unsigned char)); 280 int ScifErrCheck __P((void)); 281 unsigned char GetcScif __P((void)); 282 283 /* 284 * WaitFor 285 * : int mSec; 286 */ 287 static void 288 WaitFor(mSec) 289 int mSec; 290 { 291 292 /* Disable Under Flow interrupt, rising edge, 1/4 */ 293 SHREG_TCR2 = 0x0000; 294 295 /* Set counter value (count down with 4 KHz) */ 296 SHREG_TCNT2 = mSec * 4; 297 298 /* start Channel2 */ 299 SHREG_TSTR |= TSTR_STR2; 300 301 /* wait for under flag ON of channel2 */ 302 while ((SHREG_TCR2 & TCR_UNF) == 0) 303 ; 304 305 /* stop channel2 */ 306 SHREG_TSTR &= ~TSTR_STR2; 307 } 308 309 /* 310 * InitializeScif 311 * : unsigned int bps; 312 * : SCIF(Serial Communication Interface) 313 */ 314 315 void 316 InitializeScif(bps) 317 unsigned int bps; 318 { 319 320 /* Initialize SCR */ 321 SHREG_SCSCR2 = 0x00; 322 323 #if 0 324 SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE; 325 #else 326 SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST; 327 #endif 328 /* Serial Mode Register */ 329 SHREG_SCSMR2 = 0x00; /* 8bit,NonParity,Even,1Stop */ 330 331 /* Bit Rate Register */ 332 SHREG_SCBRR2 = divrnd(PCLOCK, 32 * bps) - 1; 333 334 /* 335 * wait 1mSec, because Send/Recv must begin 1 bit period after 336 * BRR is set. 337 */ 338 WaitFor(1); 339 340 #if 0 341 SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE; 342 #else 343 SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1; 344 #endif 345 346 /* Send permission, Recieve permission ON */ 347 SHREG_SCSCR2 = SCSCR2_TE | SCSCR2_RE; 348 349 /* Serial Status Register */ 350 SHREG_SCSSR2 &= SCSSR2_TDFE; /* Clear Status */ 351 } 352 353 354 /* 355 * PutcScif 356 * : unsigned char c; 357 */ 358 359 void 360 PutcScif(c) 361 unsigned char c; 362 { 363 364 /* wait for ready */ 365 while ((SHREG_SCFDR2 & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) 366 ; 367 368 /* write send data to send register */ 369 SHREG_SCFTDR2 = c; 370 371 /* clear ready flag */ 372 SHREG_SCSSR2 &= ~(SCSSR2_TDFE | SCSSR2_TEND); 373 374 if (c == '\n') { 375 while ((SHREG_SCFDR2 & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) 376 ; 377 378 SHREG_SCFTDR2 = '\r'; 379 380 SHREG_SCSSR2 &= ~(SCSSR2_TDFE | SCSSR2_TEND); 381 } 382 } 383 384 /* 385 * : ScifErrCheck 386 * 0x80 = error 387 * 0x08 = frame error 388 * 0x04 = parity error 389 */ 390 int 391 ScifErrCheck(void) 392 { 393 394 return(SHREG_SCSSR2 & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)); 395 } 396 397 /* 398 * GetcScif 399 */ 400 #if 0 401 /* Old code */ 402 unsigned char 403 GetcScif(void) 404 { 405 unsigned char c, err_c; 406 407 while (((err_c = SHREG_SCSSR2) 408 & (SCSSR2_RDF | SCSSR2_ER | SCSSR2_FER | SCSSR2_PER | SCSSR2_DR)) == 0) 409 ; 410 if ((err_c & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)) != 0) { 411 SHREG_SCSSR2 &= ~SCSSR2_ER; 412 return(err_c |= 0x80); 413 } 414 415 c = SHREG_SCFRDR2; 416 417 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR); 418 419 return(c); 420 } 421 #else 422 unsigned char 423 GetcScif(void) 424 { 425 unsigned char c, err_c; 426 427 while (1) { 428 /* wait for ready */ 429 while ((SHREG_SCFDR2 & SCFDR2_RECVCNT) == 0) 430 ; 431 432 c = SHREG_SCFRDR2; 433 err_c = SHREG_SCSSR2; 434 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF 435 | SCSSR2_DR); 436 if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER 437 | SCSSR2_PER)) == 0) { 438 return(c); 439 } 440 } 441 442 } 443 #endif 444 445 #if 0 446 #define SCIF_MAX_UNITS 2 447 #else 448 #define SCIF_MAX_UNITS 1 449 #endif 450 451 452 static int 453 scif_match(parent, cfp, aux) 454 struct device *parent; 455 struct cfdata *cfp; 456 void *aux; 457 { 458 struct shb_attach_args *sa = aux; 459 460 if (strcmp(cfp->cf_driver->cd_name, "scif") 461 || cfp->cf_unit >= SCIF_MAX_UNITS) 462 return 0; 463 464 sa->ia_iosize = 0x10; 465 return 1; 466 } 467 468 static void 469 scif_attach(parent, self, aux) 470 struct device *parent, *self; 471 void *aux; 472 { 473 struct scif_softc *sc = (struct scif_softc *)self; 474 struct tty *tp; 475 int irq; 476 struct shb_attach_args *ia = aux; 477 478 sc->sc_hwflags = 0; /* XXX */ 479 sc->sc_swflags = 0; /* XXX */ 480 sc->sc_fifolen = 16; 481 482 irq = ia->ia_irq; 483 484 if (scifisconsole) { 485 /* InitializeScif(scifcn_speed); */ 486 SET(sc->sc_hwflags, SCIF_HW_CONSOLE); 487 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 488 printf("\n%s: console\n", sc->sc_dev.dv_xname); 489 } else { 490 InitializeScif(9600); 491 printf("\n"); 492 } 493 494 callout_init(&sc->sc_diag_ch); 495 496 #if 0 497 if (irq != IRQUNK) { 498 sc->sc_ih = shb_intr_establish(irq, 499 IST_EDGE, IPL_SERIAL, scifintr, sc); 500 } 501 #else 502 if (irq != IRQUNK) { 503 sc->sc_ih = shb_intr_establish(SCIF_IRQ, 504 IST_EDGE, IPL_SERIAL, scifintr, sc); 505 } 506 #endif 507 508 SET(sc->sc_hwflags, SCIF_HW_DEV_OK); 509 510 tp = ttymalloc(); 511 tp->t_oproc = scifstart; 512 tp->t_param = scifparam; 513 tp->t_hwiflow = NULL; 514 515 sc->sc_tty = tp; 516 sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 517 if (sc->sc_rbuf == NULL) { 518 printf("%s: unable to allocate ring buffer\n", 519 sc->sc_dev.dv_xname); 520 return; 521 } 522 sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1); 523 524 tty_attach(tp); 525 } 526 527 /* 528 * Start or restart transmission. 529 */ 530 static void 531 scifstart(tp) 532 struct tty *tp; 533 { 534 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 535 int s; 536 537 s = spltty(); 538 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 539 goto out; 540 if (sc->sc_tx_stopped) 541 goto out; 542 543 if (tp->t_outq.c_cc <= tp->t_lowat) { 544 if (ISSET(tp->t_state, TS_ASLEEP)) { 545 CLR(tp->t_state, TS_ASLEEP); 546 wakeup(&tp->t_outq); 547 } 548 selwakeup(&tp->t_wsel); 549 if (tp->t_outq.c_cc == 0) 550 goto out; 551 } 552 553 /* Grab the first contiguous region of buffer space. */ 554 { 555 u_char *tba; 556 int tbc; 557 558 tba = tp->t_outq.c_cf; 559 tbc = ndqb(&tp->t_outq, 0); 560 561 (void)splserial(); 562 563 sc->sc_tba = tba; 564 sc->sc_tbc = tbc; 565 } 566 567 SET(tp->t_state, TS_BUSY); 568 sc->sc_tx_busy = 1; 569 570 /* Enable transmit completion interrupts if necessary. */ 571 SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE; 572 573 /* Output the first chunk of the contiguous buffer. */ 574 { 575 int n; 576 int max; 577 int i; 578 579 n = sc->sc_tbc; 580 max = sc->sc_fifolen - ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8); 581 if (n > max) 582 n = max; 583 584 for (i = 0; i < n; i++) { 585 PutcScif(*(sc->sc_tba)); 586 sc->sc_tba++; 587 } 588 sc->sc_tbc -= n; 589 } 590 out: 591 splx(s); 592 return; 593 } 594 595 /* 596 * Set SCIF tty parameters from termios. 597 * XXX - Should just copy the whole termios after 598 * making sure all the changes could be done. 599 */ 600 static int 601 scifparam(tp, t) 602 struct tty *tp; 603 struct termios *t; 604 { 605 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 606 int ospeed = t->c_ospeed; 607 int s; 608 609 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 610 return (EIO); 611 612 /* Check requested parameters. */ 613 if (ospeed < 0) 614 return (EINVAL); 615 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 616 return (EINVAL); 617 618 /* 619 * For the console, always force CLOCAL and !HUPCL, so that the port 620 * is always active. 621 */ 622 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 623 ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 624 SET(t->c_cflag, CLOCAL); 625 CLR(t->c_cflag, HUPCL); 626 } 627 628 /* 629 * If there were no changes, don't do anything. This avoids dropping 630 * input and improves performance when all we did was frob things like 631 * VMIN and VTIME. 632 */ 633 if (tp->t_ospeed == t->c_ospeed && 634 tp->t_cflag == t->c_cflag) 635 return (0); 636 637 #if 0 638 /* XXX (msaitoh) */ 639 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 640 #endif 641 642 s = splserial(); 643 644 /* 645 * Set the flow control pins depending on the current flow control 646 * mode. 647 */ 648 if (ISSET(t->c_cflag, CRTSCTS)) { 649 SHREG_SCFCR2 |= SCFCR2_MCE; 650 } else { 651 SHREG_SCFCR2 &= ~SCFCR2_MCE; 652 } 653 654 SHREG_SCBRR2 = divrnd(PCLOCK, 32 * ospeed) -1; 655 656 /* 657 * Set the FIFO threshold based on the receive speed. 658 * 659 * * If it's a low speed, it's probably a mouse or some other 660 * interactive device, so set the threshold low. 661 * * If it's a high speed, trim the trigger level down to prevent 662 * overflows. 663 * * Otherwise set it a bit higher. 664 */ 665 #if 0 666 /* XXX (msaitoh) */ 667 if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP)) 668 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 669 else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO)) 670 sc->sc_fifo = FIFO_ENABLE | 671 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : 672 t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4); 673 else 674 sc->sc_fifo = 0; 675 #endif 676 677 /* And copy to tty. */ 678 tp->t_ispeed = 0; 679 tp->t_ospeed = t->c_ospeed; 680 tp->t_cflag = t->c_cflag; 681 682 if (!sc->sc_heldchange) { 683 if (sc->sc_tx_busy) { 684 sc->sc_heldtbc = sc->sc_tbc; 685 sc->sc_tbc = 0; 686 sc->sc_heldchange = 1; 687 } 688 #if 0 689 /* XXX (msaitoh) */ 690 else 691 scif_loadchannelregs(sc); 692 #endif 693 } 694 695 if (!ISSET(t->c_cflag, CHWFLOW)) { 696 /* Disable the high water mark. */ 697 sc->sc_r_hiwat = 0; 698 sc->sc_r_lowat = 0; 699 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 700 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 701 scif_schedrx(sc); 702 } 703 } else { 704 sc->sc_r_hiwat = scif_rbuf_hiwat; 705 sc->sc_r_lowat = scif_rbuf_lowat; 706 } 707 708 splx(s); 709 710 #ifdef SCIF_DEBUG 711 if (scif_debug) 712 scifstatus(sc, "scifparam "); 713 #endif 714 715 if (!ISSET(t->c_cflag, CHWFLOW)) { 716 if (sc->sc_tx_stopped) { 717 sc->sc_tx_stopped = 0; 718 scifstart(tp); 719 } 720 } 721 722 return (0); 723 } 724 725 void 726 scif_iflush(sc) 727 struct scif_softc *sc; 728 { 729 int i; 730 unsigned char c; 731 732 i = SHREG_SCFDR2 & SCFDR2_RECVCNT; 733 734 while (i > 0) { 735 c = SHREG_SCFRDR2; 736 SHREG_SCSSR2 &= ~(SCSSR2_RDF | SCSSR2_DR); 737 i--; 738 } 739 } 740 741 int scif_getc __P((void)); 742 void scif_putc __P((int)); 743 744 int 745 scif_getc() 746 { 747 748 return (GetcScif()); 749 } 750 751 void 752 scif_putc(int c) 753 { 754 755 PutcScif(c); 756 } 757 758 int 759 scifopen(dev, flag, mode, p) 760 dev_t dev; 761 int flag, mode; 762 struct proc *p; 763 { 764 int unit = SCIFUNIT(dev); 765 struct scif_softc *sc; 766 struct tty *tp; 767 int s, s2; 768 int error; 769 770 if (unit >= scif_cd.cd_ndevs) 771 return (ENXIO); 772 sc = scif_cd.cd_devs[unit]; 773 if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) || 774 sc->sc_rbuf == NULL) 775 return (ENXIO); 776 777 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 778 return (ENXIO); 779 780 #ifdef KGDB 781 /* 782 * If this is the kgdb port, no other use is permitted. 783 */ 784 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) 785 return (EBUSY); 786 #endif 787 788 tp = sc->sc_tty; 789 790 if (ISSET(tp->t_state, TS_ISOPEN) && 791 ISSET(tp->t_state, TS_XCLUDE) && 792 p->p_ucred->cr_uid != 0) 793 return (EBUSY); 794 795 s = spltty(); 796 797 /* 798 * Do the following iff this is a first open. 799 */ 800 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 801 struct termios t; 802 803 tp->t_dev = dev; 804 805 s2 = splserial(); 806 807 /* Turn on interrupts. */ 808 SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE; 809 810 splx(s2); 811 812 /* 813 * Initialize the termios status to the defaults. Add in the 814 * sticky bits from TIOCSFLAGS. 815 */ 816 t.c_ispeed = 0; 817 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 818 t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */ 819 t.c_cflag = scifconscflag; 820 } else { 821 t.c_ospeed = TTYDEF_SPEED; 822 t.c_cflag = TTYDEF_CFLAG; 823 } 824 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 825 SET(t.c_cflag, CLOCAL); 826 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 827 SET(t.c_cflag, CRTSCTS); 828 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 829 SET(t.c_cflag, MDMBUF); 830 /* Make sure scifparam() will do something. */ 831 tp->t_ospeed = 0; 832 (void) scifparam(tp, &t); 833 tp->t_iflag = TTYDEF_IFLAG; 834 tp->t_oflag = TTYDEF_OFLAG; 835 tp->t_lflag = TTYDEF_LFLAG; 836 ttychars(tp); 837 ttsetwater(tp); 838 839 s2 = splserial(); 840 841 /* Clear the input ring, and unblock. */ 842 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 843 sc->sc_rbavail = scif_rbuf_size; 844 scif_iflush(sc); 845 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 846 #if 0 847 /* XXX (msaitoh) */ 848 scif_hwiflow(sc); 849 #endif 850 851 #ifdef SCIF_DEBUG 852 if (scif_debug) 853 scifstatus(sc, "scifopen "); 854 #endif 855 856 splx(s2); 857 } 858 859 splx(s); 860 861 error = ttyopen(tp, SCIFDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 862 if (error) 863 goto bad; 864 865 error = (*linesw[tp->t_line].l_open)(dev, tp); 866 if (error) 867 goto bad; 868 869 return (0); 870 871 bad: 872 873 return (error); 874 } 875 876 int 877 scifclose(dev, flag, mode, p) 878 dev_t dev; 879 int flag, mode; 880 struct proc *p; 881 { 882 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 883 struct tty *tp = sc->sc_tty; 884 885 /* XXX This is for cons.c. */ 886 if (!ISSET(tp->t_state, TS_ISOPEN)) 887 return (0); 888 889 (*linesw[tp->t_line].l_close)(tp, flag); 890 ttyclose(tp); 891 892 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 893 return (0); 894 895 return (0); 896 } 897 898 int 899 scifread(dev, uio, flag) 900 dev_t dev; 901 struct uio *uio; 902 int flag; 903 { 904 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 905 struct tty *tp = sc->sc_tty; 906 907 return ((*linesw[tp->t_line].l_read)(tp, uio, flag)); 908 } 909 910 int 911 scifwrite(dev, uio, flag) 912 dev_t dev; 913 struct uio *uio; 914 int flag; 915 { 916 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 917 struct tty *tp = sc->sc_tty; 918 919 return ((*linesw[tp->t_line].l_write)(tp, uio, flag)); 920 } 921 922 struct tty * 923 sciftty(dev) 924 dev_t dev; 925 { 926 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 927 struct tty *tp = sc->sc_tty; 928 929 return (tp); 930 } 931 932 int 933 scifioctl(dev, cmd, data, flag, p) 934 dev_t dev; 935 u_long cmd; 936 caddr_t data; 937 int flag; 938 struct proc *p; 939 { 940 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 941 struct tty *tp = sc->sc_tty; 942 int error; 943 int s; 944 945 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 946 return (EIO); 947 948 error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p); 949 if (error >= 0) 950 return (error); 951 952 error = ttioctl(tp, cmd, data, flag, p); 953 if (error >= 0) 954 return (error); 955 956 error = 0; 957 958 s = splserial(); 959 960 switch (cmd) { 961 case TIOCSBRK: 962 scif_break(sc, 1); 963 break; 964 965 case TIOCCBRK: 966 scif_break(sc, 0); 967 break; 968 969 case TIOCGFLAGS: 970 *(int *)data = sc->sc_swflags; 971 break; 972 973 case TIOCSFLAGS: 974 error = suser(p->p_ucred, &p->p_acflag); 975 if (error) 976 break; 977 sc->sc_swflags = *(int *)data; 978 break; 979 980 default: 981 error = ENOTTY; 982 break; 983 } 984 985 splx(s); 986 987 return (error); 988 } 989 990 integrate void 991 scif_schedrx(sc) 992 struct scif_softc *sc; 993 { 994 995 sc->sc_rx_ready = 1; 996 997 /* Wake up the poller. */ 998 #ifdef __GENERIC_SOFT_INTERRUPTS 999 softintr_schedule(sc->sc_si); 1000 #else 1001 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1002 setsoftserial(); 1003 #else 1004 if (!scif_softintr_scheduled) { 1005 scif_softintr_scheduled = 1; 1006 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 1007 } 1008 #endif 1009 #endif 1010 } 1011 1012 void 1013 scif_break(sc, onoff) 1014 struct scif_softc *sc; 1015 int onoff; 1016 { 1017 1018 if (onoff) 1019 SHREG_SCSSR2 &= ~SCSSR2_TDFE; 1020 else 1021 SHREG_SCSSR2 |= SCSSR2_TDFE; 1022 1023 #if 0 /* XXX */ 1024 if (!sc->sc_heldchange) { 1025 if (sc->sc_tx_busy) { 1026 sc->sc_heldtbc = sc->sc_tbc; 1027 sc->sc_tbc = 0; 1028 sc->sc_heldchange = 1; 1029 } else 1030 scif_loadchannelregs(sc); 1031 } 1032 #endif 1033 } 1034 1035 /* 1036 * Stop output, e.g., for ^S or output flush. 1037 */ 1038 void 1039 scifstop(tp, flag) 1040 struct tty *tp; 1041 int flag; 1042 { 1043 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 1044 int s; 1045 1046 s = splserial(); 1047 if (ISSET(tp->t_state, TS_BUSY)) { 1048 /* Stop transmitting at the next chunk. */ 1049 sc->sc_tbc = 0; 1050 sc->sc_heldtbc = 0; 1051 if (!ISSET(tp->t_state, TS_TTSTOP)) 1052 SET(tp->t_state, TS_FLUSH); 1053 } 1054 splx(s); 1055 } 1056 1057 void 1058 scif_intr_init() 1059 { 1060 /* XXX */ 1061 } 1062 1063 void 1064 scifdiag(arg) 1065 void *arg; 1066 { 1067 struct scif_softc *sc = arg; 1068 int overflows, floods; 1069 int s; 1070 1071 s = splserial(); 1072 overflows = sc->sc_overflows; 1073 sc->sc_overflows = 0; 1074 floods = sc->sc_floods; 1075 sc->sc_floods = 0; 1076 sc->sc_errors = 0; 1077 splx(s); 1078 1079 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1080 sc->sc_dev.dv_xname, 1081 overflows, overflows == 1 ? "" : "s", 1082 floods, floods == 1 ? "" : "s"); 1083 } 1084 1085 integrate void 1086 scif_rxsoft(sc, tp) 1087 struct scif_softc *sc; 1088 struct tty *tp; 1089 { 1090 int (*rint) __P((int c, struct tty *tp)) = linesw[tp->t_line].l_rint; 1091 u_char *get, *end; 1092 u_int cc, scc; 1093 u_char ssr2; 1094 int code; 1095 int s; 1096 1097 end = sc->sc_ebuf; 1098 get = sc->sc_rbget; 1099 scc = cc = scif_rbuf_size - sc->sc_rbavail; 1100 1101 if (cc == scif_rbuf_size) { 1102 sc->sc_floods++; 1103 if (sc->sc_errors++ == 0) 1104 callout_reset(&sc->sc_diag_ch, 60 * hz, scifdiag, sc); 1105 } 1106 1107 while (cc) { 1108 code = get[0]; 1109 ssr2 = get[1]; 1110 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) { 1111 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER)) 1112 SET(code, TTY_FE); 1113 if (ISSET(ssr2, SCSSR2_PER)) 1114 SET(code, TTY_PE); 1115 } 1116 if ((*rint)(code, tp) == -1) { 1117 /* 1118 * The line discipline's buffer is out of space. 1119 */ 1120 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1121 /* 1122 * We're either not using flow control, or the 1123 * line discipline didn't tell us to block for 1124 * some reason. Either way, we have no way to 1125 * know when there's more space available, so 1126 * just drop the rest of the data. 1127 */ 1128 get += cc << 1; 1129 if (get >= end) 1130 get -= scif_rbuf_size << 1; 1131 cc = 0; 1132 } else { 1133 /* 1134 * Don't schedule any more receive processing 1135 * until the line discipline tells us there's 1136 * space available (through scifhwiflow()). 1137 * Leave the rest of the data in the input 1138 * buffer. 1139 */ 1140 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1141 } 1142 break; 1143 } 1144 get += 2; 1145 if (get >= end) 1146 get = sc->sc_rbuf; 1147 cc--; 1148 } 1149 1150 if (cc != scc) { 1151 sc->sc_rbget = get; 1152 s = splserial(); 1153 cc = sc->sc_rbavail += scc - cc; 1154 /* Buffers should be ok again, release possible block. */ 1155 if (cc >= sc->sc_r_lowat) { 1156 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1157 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1158 SHREG_SCSCR2 |= SCSCR2_RIE; 1159 } 1160 #if 0 1161 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1162 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1163 scif_hwiflow(sc); 1164 } 1165 #endif 1166 } 1167 splx(s); 1168 } 1169 } 1170 1171 integrate void 1172 scif_txsoft(sc, tp) 1173 struct scif_softc *sc; 1174 struct tty *tp; 1175 { 1176 1177 CLR(tp->t_state, TS_BUSY); 1178 if (ISSET(tp->t_state, TS_FLUSH)) 1179 CLR(tp->t_state, TS_FLUSH); 1180 else 1181 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1182 (*linesw[tp->t_line].l_start)(tp); 1183 } 1184 1185 integrate void 1186 scif_stsoft(sc, tp) 1187 struct scif_softc *sc; 1188 struct tty *tp; 1189 { 1190 #if 0 1191 /* XXX (msaitoh) */ 1192 u_char msr, delta; 1193 int s; 1194 1195 s = splserial(); 1196 msr = sc->sc_msr; 1197 delta = sc->sc_msr_delta; 1198 sc->sc_msr_delta = 0; 1199 splx(s); 1200 1201 if (ISSET(delta, sc->sc_msr_dcd)) { 1202 /* 1203 * Inform the tty layer that carrier detect changed. 1204 */ 1205 (void) (*linesw[tp->t_line].l_modem)(tp, ISSET(msr, MSR_DCD)); 1206 } 1207 1208 if (ISSET(delta, sc->sc_msr_cts)) { 1209 /* Block or unblock output according to flow control. */ 1210 if (ISSET(msr, sc->sc_msr_cts)) { 1211 sc->sc_tx_stopped = 0; 1212 (*linesw[tp->t_line].l_start)(tp); 1213 } else { 1214 sc->sc_tx_stopped = 1; 1215 } 1216 } 1217 1218 #ifdef SCIF_DEBUG 1219 if (scif_debug) 1220 scifstatus(sc, "scif_stsoft"); 1221 #endif 1222 #endif 1223 } 1224 1225 #ifdef __GENERIC_SOFT_INTERRUPTS 1226 void 1227 scifsoft(arg) 1228 void *arg; 1229 { 1230 struct scif_softc *sc = arg; 1231 struct tty *tp; 1232 1233 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1234 return; 1235 1236 { 1237 #else 1238 void 1239 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1240 scifsoft() 1241 #else 1242 scifsoft(arg) 1243 void *arg; 1244 #endif 1245 { 1246 struct scif_softc *sc; 1247 struct tty *tp; 1248 int unit; 1249 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1250 int s; 1251 1252 s = splsoftserial(); 1253 scif_softintr_scheduled = 0; 1254 #endif 1255 1256 for (unit = 0; unit < scif_cd.cd_ndevs; unit++) { 1257 sc = scif_cd.cd_devs[unit]; 1258 if (sc == NULL || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK)) 1259 continue; 1260 1261 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1262 continue; 1263 1264 tp = sc->sc_tty; 1265 if (tp == NULL) 1266 continue; 1267 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 1268 continue; 1269 #endif 1270 tp = sc->sc_tty; 1271 1272 if (sc->sc_rx_ready) { 1273 sc->sc_rx_ready = 0; 1274 scif_rxsoft(sc, tp); 1275 } 1276 1277 #if 0 1278 if (sc->sc_st_check) { 1279 sc->sc_st_check = 0; 1280 scif_stsoft(sc, tp); 1281 } 1282 #endif 1283 1284 if (sc->sc_tx_done) { 1285 sc->sc_tx_done = 0; 1286 scif_txsoft(sc, tp); 1287 } 1288 } 1289 1290 #ifndef __GENERIC_SOFT_INTERRUPTS 1291 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1292 splx(s); 1293 #endif 1294 #endif 1295 } 1296 1297 int 1298 scifintr(arg) 1299 void *arg; 1300 { 1301 struct scif_softc *sc = arg; 1302 u_char *put, *end; 1303 u_int cc; 1304 u_short ssr2; 1305 int count; 1306 1307 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1308 return (0); 1309 1310 end = sc->sc_ebuf; 1311 put = sc->sc_rbput; 1312 cc = sc->sc_rbavail; 1313 1314 ssr2 = SHREG_SCSSR2; 1315 if (ISSET(ssr2, SCSSR2_BRK)) { 1316 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR); 1317 #if defined(DDB) || defined(KGDB) 1318 #ifdef DDB 1319 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 1320 console_debugger(); 1321 } 1322 #endif 1323 #ifdef KGDB 1324 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) { 1325 kgdb_connect(1); 1326 } 1327 #endif 1328 #endif /* DDB || KGDB */ 1329 } 1330 count = SHREG_SCFDR2 & SCFDR2_RECVCNT; 1331 if (count != 0) { 1332 while ((cc > 0) && (count > 0)) { 1333 put[0] = SHREG_SCFRDR2; 1334 put[1] = (u_char)(SHREG_SCSSR2 & 0x00ff); 1335 1336 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR); 1337 1338 put += 2; 1339 if (put >= end) 1340 put = sc->sc_rbuf; 1341 cc--; 1342 count--; 1343 } 1344 1345 /* 1346 * Current string of incoming characters ended because 1347 * no more data was available or we ran out of space. 1348 * Schedule a receive event if any data was received. 1349 * If we're out of space, turn off receive interrupts. 1350 */ 1351 sc->sc_rbput = put; 1352 sc->sc_rbavail = cc; 1353 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1354 sc->sc_rx_ready = 1; 1355 1356 /* 1357 * See if we are in danger of overflowing a buffer. If 1358 * so, use hardware flow control to ease the pressure. 1359 */ 1360 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1361 cc < sc->sc_r_hiwat) { 1362 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1363 #if 0 1364 scif_hwiflow(sc); 1365 #endif 1366 } 1367 1368 /* 1369 * If we're out of space, disable receive interrupts 1370 * until the queue has drained a bit. 1371 */ 1372 if (!cc) { 1373 SHREG_SCSCR2 &= ~SCSCR2_RIE; 1374 } 1375 } else { 1376 if (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR)) { 1377 SHREG_SCSCR2 &= ~(SCSCR2_TIE | SCSCR2_RIE); 1378 } 1379 } 1380 1381 #if 0 1382 msr = bus_space_read_1(iot, ioh, scif_msr); 1383 delta = msr ^ sc->sc_msr; 1384 sc->sc_msr = msr; 1385 if (ISSET(delta, sc->sc_msr_mask)) { 1386 SET(sc->sc_msr_delta, delta); 1387 1388 /* 1389 * Pulse-per-second clock signal on edge of DCD? 1390 */ 1391 if (ISSET(delta, sc->sc_ppsmask)) { 1392 struct timeval tv; 1393 if (ISSET(msr, sc->sc_ppsmask) == 1394 sc->sc_ppsassert) { 1395 /* XXX nanotime() */ 1396 microtime(&tv); 1397 TIMEVAL_TO_TIMESPEC(&tv, 1398 &sc->ppsinfo.assert_timestamp); 1399 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 1400 timespecadd(&sc->ppsinfo.assert_timestamp, 1401 &sc->ppsparam.assert_offset, 1402 &sc->ppsinfo.assert_timestamp); 1403 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp); 1404 } 1405 1406 #ifdef PPS_SYNC 1407 if (sc->ppsparam.mode & PPS_HARDPPSONASSERT) 1408 hardpps(&tv, tv.tv_usec); 1409 #endif 1410 sc->ppsinfo.assert_sequence++; 1411 sc->ppsinfo.current_mode = 1412 sc->ppsparam.mode; 1413 1414 } else if (ISSET(msr, sc->sc_ppsmask) == 1415 sc->sc_ppsclear) { 1416 /* XXX nanotime() */ 1417 microtime(&tv); 1418 TIMEVAL_TO_TIMESPEC(&tv, 1419 &sc->ppsinfo.clear_timestamp); 1420 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 1421 timespecadd(&sc->ppsinfo.clear_timestamp, 1422 &sc->ppsparam.clear_offset, 1423 &sc->ppsinfo.clear_timestamp); 1424 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp); 1425 } 1426 1427 #ifdef PPS_SYNC 1428 if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR) 1429 hardpps(&tv, tv.tv_usec); 1430 #endif 1431 sc->ppsinfo.clear_sequence++; 1432 sc->ppsinfo.current_mode = 1433 sc->ppsparam.mode; 1434 } 1435 } 1436 1437 /* 1438 * Stop output immediately if we lose the output 1439 * flow control signal or carrier detect. 1440 */ 1441 if (ISSET(~msr, sc->sc_msr_mask)) { 1442 sc->sc_tbc = 0; 1443 sc->sc_heldtbc = 0; 1444 #ifdef SCIF_DEBUG 1445 if (scif_debug) 1446 scifstatus(sc, "scifintr "); 1447 #endif 1448 } 1449 1450 sc->sc_st_check = 1; 1451 } 1452 #endif 1453 1454 /* 1455 * Done handling any receive interrupts. See if data can be 1456 * transmitted as well. Schedule tx done event if no data left 1457 * and tty was marked busy. 1458 */ 1459 if (((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */ 1460 /* 1461 * If we've delayed a parameter change, do it now, and restart 1462 * output. 1463 */ 1464 if (sc->sc_heldchange) { 1465 sc->sc_heldchange = 0; 1466 sc->sc_tbc = sc->sc_heldtbc; 1467 sc->sc_heldtbc = 0; 1468 } 1469 1470 /* Output the next chunk of the contiguous buffer, if any. */ 1471 if (sc->sc_tbc > 0) { 1472 int n; 1473 int max; 1474 int i; 1475 1476 n = sc->sc_tbc; 1477 max = sc->sc_fifolen - 1478 ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8); 1479 if (n > max) 1480 n = max; 1481 1482 for (i = 0; i < n; i++) { 1483 PutcScif(*(sc->sc_tba)); 1484 sc->sc_tba++; 1485 } 1486 sc->sc_tbc -= n; 1487 } else { 1488 /* Disable transmit completion interrupts if necessary. */ 1489 #if 0 1490 if (ISSET(sc->sc_ier, IER_ETXRDY)) 1491 #endif 1492 SHREG_SCSCR2 &= ~SCSCR2_TIE; 1493 1494 if (sc->sc_tx_busy) { 1495 sc->sc_tx_busy = 0; 1496 sc->sc_tx_done = 1; 1497 } 1498 } 1499 } 1500 1501 /* Wake up the poller. */ 1502 #ifdef __GENERIC_SOFT_INTERRUPTS 1503 softintr_schedule(sc->sc_si); 1504 #else 1505 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1506 setsoftserial(); 1507 #else 1508 if (!scif_softintr_scheduled) { 1509 scif_softintr_scheduled = 1; 1510 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 1511 } 1512 #endif 1513 #endif 1514 1515 #if NRND > 0 && defined(RND_SCIF) 1516 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1517 #endif 1518 1519 return (1); 1520 } 1521 1522 void 1523 scifcnprobe(cp) 1524 struct consdev *cp; 1525 { 1526 int maj; 1527 1528 /* locate the major number */ 1529 for (maj = 0; maj < nchrdev; maj++) 1530 if (cdevsw[maj].d_open == scifopen) 1531 break; 1532 1533 /* Initialize required fields. */ 1534 cp->cn_dev = makedev(maj, 0); 1535 #ifdef SCIFCONSOLE 1536 cp->cn_pri = CN_REMOTE; 1537 #else 1538 cp->cn_pri = CN_NORMAL; 1539 #endif 1540 } 1541 1542 void 1543 scifcninit(cp) 1544 struct consdev *cp; 1545 { 1546 1547 InitializeScif(scifcn_speed); 1548 scifisconsole = 1; 1549 } 1550 1551 #define scif_getc GetcScif 1552 #define scif_putc PutcScif 1553 1554 int 1555 scifcngetc(dev) 1556 dev_t dev; 1557 { 1558 int c; 1559 int s; 1560 1561 s = splserial(); 1562 c = scif_getc(); 1563 splx(s); 1564 1565 return (c); 1566 } 1567 1568 void 1569 scifcnputc(dev, c) 1570 dev_t dev; 1571 int c; 1572 { 1573 int s; 1574 1575 s = splserial(); 1576 scif_putc(c); 1577 splx(s); 1578 } 1579
Indexes created Mon Sep 22 13:09:51 GMT 2025