scif.c revision 1.25
1 /* $NetBSD: scif.c,v 1.25 2002/04/28 17:10:32 uch Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Charles M. Hannum. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the NetBSD 47 * Foundation, Inc. and its contributors. 48 * 4. Neither the name of The NetBSD Foundation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 53 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 54 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * Copyright (c) 1991 The Regents of the University of California. 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. All advertising materials mentioning features or use of this software 78 * must display the following acknowledgement: 79 * This product includes software developed by the University of 80 * California, Berkeley and its contributors. 81 * 4. Neither the name of the University nor the names of its contributors 82 * may be used to endorse or promote products derived from this software 83 * without specific prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 86 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 88 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 89 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 90 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 91 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 92 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 93 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 94 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 95 * SUCH DAMAGE. 96 * 97 * @(#)com.c 7.5 (Berkeley) 5/16/91 98 */ 99 100 /* 101 * SH internal serial driver 102 * 103 * This code is derived from both z8530tty.c and com.c 104 */ 105 106 #include "opt_kgdb.h" 107 #include "opt_scif.h" 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/tty.h> 112 #include <sys/proc.h> 113 #include <sys/conf.h> 114 #include <sys/file.h> 115 #include <sys/syslog.h> 116 #include <sys/kernel.h> 117 #include <sys/device.h> 118 #include <sys/malloc.h> 119 #include <sys/kgdb.h> 120 121 #include <dev/cons.h> 122 123 #include <sh3/clock.h> 124 #include <sh3/exception.h> 125 #include <sh3/scifreg.h> 126 #include <machine/intr.h> 127 128 #include <sh3/dev/scifvar.h> 129 130 #include "locators.h" 131 132 static void scifstart(struct tty *); 133 static int scifparam(struct tty *, struct termios *); 134 static int kgdb_attached; 135 136 void scifcnprobe(struct consdev *); 137 void scifcninit(struct consdev *); 138 void scifcnputc(dev_t, int); 139 int scifcngetc(dev_t); 140 void scifcnpoolc(dev_t, int); 141 void scif_intr_init(void); 142 int scifintr(void *); 143 144 struct scif_softc { 145 struct device sc_dev; /* boilerplate */ 146 struct tty *sc_tty; 147 void *sc_si; 148 149 struct callout sc_diag_ch; 150 151 #if 0 152 bus_space_tag_t sc_iot; /* ISA i/o space identifier */ 153 bus_space_handle_t sc_ioh; /* ISA io handle */ 154 155 int sc_drq; 156 157 int sc_frequency; 158 #endif 159 160 u_int sc_overflows, 161 sc_floods, 162 sc_errors; /* number of retries so far */ 163 u_char sc_status[7]; /* copy of registers */ 164 165 int sc_hwflags; 166 int sc_swflags; 167 u_int sc_fifolen; 168 169 u_int sc_r_hiwat, 170 sc_r_lowat; 171 u_char *volatile sc_rbget, 172 *volatile sc_rbput; 173 volatile u_int sc_rbavail; 174 u_char *sc_rbuf, 175 *sc_ebuf; 176 177 u_char *sc_tba; /* transmit buffer address */ 178 u_int sc_tbc, /* transmit byte count */ 179 sc_heldtbc; 180 181 volatile u_char sc_rx_flags, 182 #define RX_TTY_BLOCKED 0x01 183 #define RX_TTY_OVERFLOWED 0x02 184 #define RX_IBUF_BLOCKED 0x04 185 #define RX_IBUF_OVERFLOWED 0x08 186 #define RX_ANY_BLOCK 0x0f 187 sc_tx_busy, /* working on an output chunk */ 188 sc_tx_done, /* done with one output chunk */ 189 sc_tx_stopped, /* H/W level stop (lost CTS) */ 190 sc_st_check, /* got a status interrupt */ 191 sc_rx_ready; 192 193 volatile u_char sc_heldchange; 194 }; 195 196 /* controller driver configuration */ 197 static int scif_match(struct device *, struct cfdata *, void *); 198 static void scif_attach(struct device *, struct device *, void *); 199 200 void scif_break(struct scif_softc *, int); 201 void scif_iflush(struct scif_softc *); 202 203 #define integrate static inline 204 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 205 void scifsoft(void *); 206 #else 207 #ifndef __NO_SOFT_SERIAL_INTERRUPT 208 void scifsoft(void); 209 #else 210 void scifsoft(void *); 211 #endif 212 #endif 213 integrate void scif_rxsoft(struct scif_softc *, struct tty *); 214 integrate void scif_txsoft(struct scif_softc *, struct tty *); 215 integrate void scif_stsoft(struct scif_softc *, struct tty *); 216 integrate void scif_schedrx(struct scif_softc *); 217 void scifdiag(void *); 218 219 220 #define SCIFUNIT_MASK 0x7ffff 221 #define SCIFDIALOUT_MASK 0x80000 222 223 #define SCIFUNIT(x) (minor(x) & SCIFUNIT_MASK) 224 #define SCIFDIALOUT(x) (minor(x) & SCIFDIALOUT_MASK) 225 226 /* Macros to clear/set/test flags. */ 227 #define SET(t, f) (t) |= (f) 228 #define CLR(t, f) (t) &= ~(f) 229 #define ISSET(t, f) ((t) & (f)) 230 231 /* Hardware flag masks */ 232 #define SCIF_HW_NOIEN 0x01 233 #define SCIF_HW_FIFO 0x02 234 #define SCIF_HW_FLOW 0x08 235 #define SCIF_HW_DEV_OK 0x20 236 #define SCIF_HW_CONSOLE 0x40 237 #define SCIF_HW_KGDB 0x80 238 239 /* Buffer size for character buffer */ 240 #define SCIF_RING_SIZE 2048 241 242 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 243 u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4; 244 u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4; 245 246 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 247 int scifconscflag = CONMODE; 248 int scifisconsole = 0; 249 250 #ifdef SCIFCN_SPEED 251 unsigned int scifcn_speed = SCIFCN_SPEED; 252 #else 253 unsigned int scifcn_speed = 9600; 254 #endif 255 256 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 257 258 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 259 #ifdef __NO_SOFT_SERIAL_INTERRUPT 260 volatile int scif_softintr_scheduled; 261 struct callout scif_soft_ch = CALLOUT_INITIALIZER; 262 #endif 263 #endif 264 265 u_int scif_rbuf_size = SCIF_RING_SIZE; 266 267 struct cfattach scif_ca = { 268 sizeof(struct scif_softc), scif_match, scif_attach 269 }; 270 271 extern struct cfdriver scif_cd; 272 273 cdev_decl(scif); 274 275 void InitializeScif (unsigned int); 276 277 /* 278 * following functions are debugging prupose only 279 */ 280 #define CR 0x0D 281 #define USART_ON (unsigned int)~0x08 282 283 void scif_putc(unsigned char); 284 unsigned char scif_getc(void); 285 int ScifErrCheck(void); 286 287 /* 288 * InitializeScif 289 * : unsigned int bps; 290 * : SCIF(Serial Communication Interface) 291 */ 292 293 void 294 InitializeScif(unsigned int bps) 295 { 296 297 /* Initialize SCR */ 298 SHREG_SCSCR2 = 0x00; 299 300 #if 0 301 SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE; 302 #else 303 SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST; 304 #endif 305 /* Serial Mode Register */ 306 SHREG_SCSMR2 = 0x00; /* 8bit,NonParity,Even,1Stop */ 307 308 /* Bit Rate Register */ 309 SHREG_SCBRR2 = divrnd(sh_clock_get_pclock(), 32 * bps) - 1; 310 311 /* 312 * wait 1mSec, because Send/Recv must begin 1 bit period after 313 * BRR is set. 314 */ 315 delay(1000); 316 317 #if 0 318 SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE; 319 #else 320 SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1; 321 #endif 322 323 /* Send permission, Receive permission ON */ 324 SHREG_SCSCR2 = SCSCR2_TE | SCSCR2_RE; 325 326 /* Serial Status Register */ 327 SHREG_SCSSR2 &= SCSSR2_TDFE; /* Clear Status */ 328 } 329 330 331 /* 332 * scif_putc 333 * : unsigned char c; 334 */ 335 336 void 337 scif_putc(unsigned char c) 338 { 339 340 if (c == '\n') 341 scif_putc('\r'); 342 343 /* wait for ready */ 344 while ((SHREG_SCFDR2 & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) 345 ; 346 347 /* write send data to send register */ 348 SHREG_SCFTDR2 = c; 349 350 /* clear ready flag */ 351 SHREG_SCSSR2 &= ~(SCSSR2_TDFE | SCSSR2_TEND); 352 } 353 354 /* 355 * : ScifErrCheck 356 * 0x80 = error 357 * 0x08 = frame error 358 * 0x04 = parity error 359 */ 360 int 361 ScifErrCheck(void) 362 { 363 364 return(SHREG_SCSSR2 & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)); 365 } 366 367 /* 368 * scif_getc 369 */ 370 #if 0 371 /* Old code */ 372 unsigned char 373 scif_getc(void) 374 { 375 unsigned char c, err_c; 376 377 while (((err_c = SHREG_SCSSR2) 378 & (SCSSR2_RDF | SCSSR2_ER | SCSSR2_FER | SCSSR2_PER | SCSSR2_DR)) == 0) 379 ; 380 if ((err_c & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)) != 0) { 381 SHREG_SCSSR2 &= ~SCSSR2_ER; 382 return(err_c |= 0x80); 383 } 384 385 c = SHREG_SCFRDR2; 386 387 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR); 388 389 return(c); 390 } 391 #else 392 unsigned char 393 scif_getc(void) 394 { 395 unsigned char c, err_c; 396 397 while (1) { 398 /* wait for ready */ 399 while ((SHREG_SCFDR2 & SCFDR2_RECVCNT) == 0) 400 ; 401 402 c = SHREG_SCFRDR2; 403 err_c = SHREG_SCSSR2; 404 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF 405 | SCSSR2_DR); 406 if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER 407 | SCSSR2_PER)) == 0) { 408 return(c); 409 } 410 } 411 412 } 413 #endif 414 415 #if 0 416 #define SCIF_MAX_UNITS 2 417 #else 418 #define SCIF_MAX_UNITS 1 419 #endif 420 421 422 static int 423 scif_match(struct device *parent, struct cfdata *cfp, void *aux) 424 { 425 426 if (strcmp(cfp->cf_driver->cd_name, "scif") 427 || cfp->cf_unit >= SCIF_MAX_UNITS) 428 return 0; 429 430 return 1; 431 } 432 433 static void 434 scif_attach(struct device *parent, struct device *self, void *aux) 435 { 436 struct scif_softc *sc = (struct scif_softc *)self; 437 struct tty *tp; 438 439 sc->sc_hwflags = 0; /* XXX */ 440 sc->sc_swflags = 0; /* XXX */ 441 sc->sc_fifolen = 16; 442 443 if (scifisconsole || kgdb_attached) { 444 /* InitializeScif(scifcn_speed); */ 445 SET(sc->sc_hwflags, SCIF_HW_CONSOLE); 446 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 447 if (kgdb_attached) { 448 SET(sc->sc_hwflags, SCIF_HW_KGDB); 449 printf("\n%s: kgdb\n", sc->sc_dev.dv_xname); 450 } else { 451 printf("\n%s: console\n", sc->sc_dev.dv_xname); 452 } 453 } else { 454 InitializeScif(9600); 455 printf("\n"); 456 } 457 458 callout_init(&sc->sc_diag_ch); 459 #ifdef SH4 460 intc_intr_establish(SH4_INTEVT_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 461 scifintr, sc); 462 intc_intr_establish(SH4_INTEVT_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 463 scifintr, sc); 464 intc_intr_establish(SH4_INTEVT_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 465 scifintr, sc); 466 intc_intr_establish(SH4_INTEVT_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 467 scifintr, sc); 468 #else 469 intc_intr_establish(SH7709_INTEVT2_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 470 scifintr, sc); 471 intc_intr_establish(SH7709_INTEVT2_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 472 scifintr, sc); 473 intc_intr_establish(SH7709_INTEVT2_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 474 scifintr, sc); 475 intc_intr_establish(SH7709_INTEVT2_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 476 scifintr, sc); 477 #endif 478 479 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 480 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, scifsoft, sc); 481 #endif 482 SET(sc->sc_hwflags, SCIF_HW_DEV_OK); 483 484 tp = ttymalloc(); 485 tp->t_oproc = scifstart; 486 tp->t_param = scifparam; 487 tp->t_hwiflow = NULL; 488 489 sc->sc_tty = tp; 490 sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 491 if (sc->sc_rbuf == NULL) { 492 printf("%s: unable to allocate ring buffer\n", 493 sc->sc_dev.dv_xname); 494 return; 495 } 496 sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1); 497 498 tty_attach(tp); 499 } 500 501 /* 502 * Start or restart transmission. 503 */ 504 static void 505 scifstart(struct tty *tp) 506 { 507 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 508 int s; 509 510 s = spltty(); 511 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 512 goto out; 513 if (sc->sc_tx_stopped) 514 goto out; 515 516 if (tp->t_outq.c_cc <= tp->t_lowat) { 517 if (ISSET(tp->t_state, TS_ASLEEP)) { 518 CLR(tp->t_state, TS_ASLEEP); 519 wakeup(&tp->t_outq); 520 } 521 selwakeup(&tp->t_wsel); 522 if (tp->t_outq.c_cc == 0) 523 goto out; 524 } 525 526 /* Grab the first contiguous region of buffer space. */ 527 { 528 u_char *tba; 529 int tbc; 530 531 tba = tp->t_outq.c_cf; 532 tbc = ndqb(&tp->t_outq, 0); 533 534 (void)splserial(); 535 536 sc->sc_tba = tba; 537 sc->sc_tbc = tbc; 538 } 539 540 SET(tp->t_state, TS_BUSY); 541 sc->sc_tx_busy = 1; 542 543 /* Enable transmit completion interrupts if necessary. */ 544 SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE; 545 546 /* Output the first chunk of the contiguous buffer. */ 547 { 548 int n; 549 int max; 550 int i; 551 552 n = sc->sc_tbc; 553 max = sc->sc_fifolen - ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8); 554 if (n > max) 555 n = max; 556 557 for (i = 0; i < n; i++) { 558 scif_putc(*(sc->sc_tba)); 559 sc->sc_tba++; 560 } 561 sc->sc_tbc -= n; 562 } 563 out: 564 splx(s); 565 return; 566 } 567 568 /* 569 * Set SCIF tty parameters from termios. 570 * XXX - Should just copy the whole termios after 571 * making sure all the changes could be done. 572 */ 573 static int 574 scifparam(struct tty *tp, struct termios *t) 575 { 576 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 577 int ospeed = t->c_ospeed; 578 int s; 579 580 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 581 return (EIO); 582 583 /* Check requested parameters. */ 584 if (ospeed < 0) 585 return (EINVAL); 586 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 587 return (EINVAL); 588 589 /* 590 * For the console, always force CLOCAL and !HUPCL, so that the port 591 * is always active. 592 */ 593 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 594 ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 595 SET(t->c_cflag, CLOCAL); 596 CLR(t->c_cflag, HUPCL); 597 } 598 599 /* 600 * If there were no changes, don't do anything. This avoids dropping 601 * input and improves performance when all we did was frob things like 602 * VMIN and VTIME. 603 */ 604 if (tp->t_ospeed == t->c_ospeed && 605 tp->t_cflag == t->c_cflag) 606 return (0); 607 608 #if 0 609 /* XXX (msaitoh) */ 610 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 611 #endif 612 613 s = splserial(); 614 615 /* 616 * Set the flow control pins depending on the current flow control 617 * mode. 618 */ 619 if (ISSET(t->c_cflag, CRTSCTS)) { 620 SHREG_SCFCR2 |= SCFCR2_MCE; 621 } else { 622 SHREG_SCFCR2 &= ~SCFCR2_MCE; 623 } 624 625 SHREG_SCBRR2 = divrnd(sh_clock_get_pclock(), 32 * ospeed) -1; 626 627 /* 628 * Set the FIFO threshold based on the receive speed. 629 * 630 * * If it's a low speed, it's probably a mouse or some other 631 * interactive device, so set the threshold low. 632 * * If it's a high speed, trim the trigger level down to prevent 633 * overflows. 634 * * Otherwise set it a bit higher. 635 */ 636 #if 0 637 /* XXX (msaitoh) */ 638 if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP)) 639 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 640 else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO)) 641 sc->sc_fifo = FIFO_ENABLE | 642 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : 643 t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4); 644 else 645 sc->sc_fifo = 0; 646 #endif 647 648 /* And copy to tty. */ 649 tp->t_ispeed = 0; 650 tp->t_ospeed = t->c_ospeed; 651 tp->t_cflag = t->c_cflag; 652 653 if (!sc->sc_heldchange) { 654 if (sc->sc_tx_busy) { 655 sc->sc_heldtbc = sc->sc_tbc; 656 sc->sc_tbc = 0; 657 sc->sc_heldchange = 1; 658 } 659 #if 0 660 /* XXX (msaitoh) */ 661 else 662 scif_loadchannelregs(sc); 663 #endif 664 } 665 666 if (!ISSET(t->c_cflag, CHWFLOW)) { 667 /* Disable the high water mark. */ 668 sc->sc_r_hiwat = 0; 669 sc->sc_r_lowat = 0; 670 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 671 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 672 scif_schedrx(sc); 673 } 674 } else { 675 sc->sc_r_hiwat = scif_rbuf_hiwat; 676 sc->sc_r_lowat = scif_rbuf_lowat; 677 } 678 679 splx(s); 680 681 #ifdef SCIF_DEBUG 682 if (scif_debug) 683 scifstatus(sc, "scifparam "); 684 #endif 685 686 if (!ISSET(t->c_cflag, CHWFLOW)) { 687 if (sc->sc_tx_stopped) { 688 sc->sc_tx_stopped = 0; 689 scifstart(tp); 690 } 691 } 692 693 return (0); 694 } 695 696 void 697 scif_iflush(struct scif_softc *sc) 698 { 699 int i; 700 unsigned char c; 701 702 i = SHREG_SCFDR2 & SCFDR2_RECVCNT; 703 704 while (i > 0) { 705 c = SHREG_SCFRDR2; 706 SHREG_SCSSR2 &= ~(SCSSR2_RDF | SCSSR2_DR); 707 i--; 708 } 709 } 710 711 int 712 scifopen(dev_t dev, int flag, int mode, struct proc *p) 713 { 714 int unit = SCIFUNIT(dev); 715 struct scif_softc *sc; 716 struct tty *tp; 717 int s, s2; 718 int error; 719 720 if (unit >= scif_cd.cd_ndevs) 721 return (ENXIO); 722 sc = scif_cd.cd_devs[unit]; 723 if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) || 724 sc->sc_rbuf == NULL) 725 return (ENXIO); 726 727 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 728 return (ENXIO); 729 730 #ifdef KGDB 731 /* 732 * If this is the kgdb port, no other use is permitted. 733 */ 734 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) 735 return (EBUSY); 736 #endif /* KGDB */ 737 738 tp = sc->sc_tty; 739 740 if (ISSET(tp->t_state, TS_ISOPEN) && 741 ISSET(tp->t_state, TS_XCLUDE) && 742 p->p_ucred->cr_uid != 0) 743 return (EBUSY); 744 745 s = spltty(); 746 747 /* 748 * Do the following iff this is a first open. 749 */ 750 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 751 struct termios t; 752 753 tp->t_dev = dev; 754 755 s2 = splserial(); 756 757 /* Turn on interrupts. */ 758 SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE; 759 760 splx(s2); 761 762 /* 763 * Initialize the termios status to the defaults. Add in the 764 * sticky bits from TIOCSFLAGS. 765 */ 766 t.c_ispeed = 0; 767 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 768 t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */ 769 t.c_cflag = scifconscflag; 770 } else { 771 t.c_ospeed = TTYDEF_SPEED; 772 t.c_cflag = TTYDEF_CFLAG; 773 } 774 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 775 SET(t.c_cflag, CLOCAL); 776 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 777 SET(t.c_cflag, CRTSCTS); 778 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 779 SET(t.c_cflag, MDMBUF); 780 /* Make sure scifparam() will do something. */ 781 tp->t_ospeed = 0; 782 (void) scifparam(tp, &t); 783 tp->t_iflag = TTYDEF_IFLAG; 784 tp->t_oflag = TTYDEF_OFLAG; 785 tp->t_lflag = TTYDEF_LFLAG; 786 ttychars(tp); 787 ttsetwater(tp); 788 789 s2 = splserial(); 790 791 /* Clear the input ring, and unblock. */ 792 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 793 sc->sc_rbavail = scif_rbuf_size; 794 scif_iflush(sc); 795 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 796 #if 0 797 /* XXX (msaitoh) */ 798 scif_hwiflow(sc); 799 #endif 800 801 #ifdef SCIF_DEBUG 802 if (scif_debug) 803 scifstatus(sc, "scifopen "); 804 #endif 805 806 splx(s2); 807 } 808 809 splx(s); 810 811 error = ttyopen(tp, SCIFDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 812 if (error) 813 goto bad; 814 815 error = (*tp->t_linesw->l_open)(dev, tp); 816 if (error) 817 goto bad; 818 819 return (0); 820 821 bad: 822 823 return (error); 824 } 825 826 int 827 scifclose(dev_t dev, int flag, int mode, struct proc *p) 828 { 829 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 830 struct tty *tp = sc->sc_tty; 831 832 /* XXX This is for cons.c. */ 833 if (!ISSET(tp->t_state, TS_ISOPEN)) 834 return (0); 835 836 (*tp->t_linesw->l_close)(tp, flag); 837 ttyclose(tp); 838 839 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 840 return (0); 841 842 return (0); 843 } 844 845 int 846 scifread(dev_t dev, struct uio *uio, int flag) 847 { 848 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 849 struct tty *tp = sc->sc_tty; 850 851 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 852 } 853 854 int 855 scifwrite(dev_t dev, struct uio *uio, int flag) 856 { 857 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 858 struct tty *tp = sc->sc_tty; 859 860 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 861 } 862 863 int 864 scifpoll(dev_t dev, int events, struct proc *p) 865 { 866 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 867 struct tty *tp = sc->sc_tty; 868 869 return ((*tp->t_linesw->l_poll)(tp, events, p)); 870 } 871 872 struct tty * 873 sciftty(dev_t dev) 874 { 875 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 876 struct tty *tp = sc->sc_tty; 877 878 return (tp); 879 } 880 881 int 882 scifioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 883 { 884 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 885 struct tty *tp = sc->sc_tty; 886 int error; 887 int s; 888 889 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 890 return (EIO); 891 892 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 893 if (error != EPASSTHROUGH) 894 return (error); 895 896 error = ttioctl(tp, cmd, data, flag, p); 897 if (error != EPASSTHROUGH) 898 return (error); 899 900 error = 0; 901 902 s = splserial(); 903 904 switch (cmd) { 905 case TIOCSBRK: 906 scif_break(sc, 1); 907 break; 908 909 case TIOCCBRK: 910 scif_break(sc, 0); 911 break; 912 913 case TIOCGFLAGS: 914 *(int *)data = sc->sc_swflags; 915 break; 916 917 case TIOCSFLAGS: 918 error = suser(p->p_ucred, &p->p_acflag); 919 if (error) 920 break; 921 sc->sc_swflags = *(int *)data; 922 break; 923 924 default: 925 error = EPASSTHROUGH; 926 break; 927 } 928 929 splx(s); 930 931 return (error); 932 } 933 934 integrate void 935 scif_schedrx(struct scif_softc *sc) 936 { 937 938 sc->sc_rx_ready = 1; 939 940 /* Wake up the poller. */ 941 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 942 softintr_schedule(sc->sc_si); 943 #else 944 #ifndef __NO_SOFT_SERIAL_INTERRUPT 945 setsoftserial(); 946 #else 947 if (!scif_softintr_scheduled) { 948 scif_softintr_scheduled = 1; 949 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 950 } 951 #endif 952 #endif 953 } 954 955 void 956 scif_break(struct scif_softc *sc, int onoff) 957 { 958 959 if (onoff) 960 SHREG_SCSSR2 &= ~SCSSR2_TDFE; 961 else 962 SHREG_SCSSR2 |= SCSSR2_TDFE; 963 964 #if 0 /* XXX */ 965 if (!sc->sc_heldchange) { 966 if (sc->sc_tx_busy) { 967 sc->sc_heldtbc = sc->sc_tbc; 968 sc->sc_tbc = 0; 969 sc->sc_heldchange = 1; 970 } else 971 scif_loadchannelregs(sc); 972 } 973 #endif 974 } 975 976 /* 977 * Stop output, e.g., for ^S or output flush. 978 */ 979 void 980 scifstop(struct tty *tp, int flag) 981 { 982 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 983 int s; 984 985 s = splserial(); 986 if (ISSET(tp->t_state, TS_BUSY)) { 987 /* Stop transmitting at the next chunk. */ 988 sc->sc_tbc = 0; 989 sc->sc_heldtbc = 0; 990 if (!ISSET(tp->t_state, TS_TTSTOP)) 991 SET(tp->t_state, TS_FLUSH); 992 } 993 splx(s); 994 } 995 996 void 997 scif_intr_init() 998 { 999 /* XXX */ 1000 } 1001 1002 void 1003 scifdiag(void *arg) 1004 { 1005 struct scif_softc *sc = arg; 1006 int overflows, floods; 1007 int s; 1008 1009 s = splserial(); 1010 overflows = sc->sc_overflows; 1011 sc->sc_overflows = 0; 1012 floods = sc->sc_floods; 1013 sc->sc_floods = 0; 1014 sc->sc_errors = 0; 1015 splx(s); 1016 1017 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1018 sc->sc_dev.dv_xname, 1019 overflows, overflows == 1 ? "" : "s", 1020 floods, floods == 1 ? "" : "s"); 1021 } 1022 1023 integrate void 1024 scif_rxsoft(struct scif_softc *sc, struct tty *tp) 1025 { 1026 int (*rint)(int c, struct tty *tp) = tp->t_linesw->l_rint; 1027 u_char *get, *end; 1028 u_int cc, scc; 1029 u_char ssr2; 1030 int code; 1031 int s; 1032 1033 end = sc->sc_ebuf; 1034 get = sc->sc_rbget; 1035 scc = cc = scif_rbuf_size - sc->sc_rbavail; 1036 1037 if (cc == scif_rbuf_size) { 1038 sc->sc_floods++; 1039 if (sc->sc_errors++ == 0) 1040 callout_reset(&sc->sc_diag_ch, 60 * hz, scifdiag, sc); 1041 } 1042 1043 while (cc) { 1044 code = get[0]; 1045 ssr2 = get[1]; 1046 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) { 1047 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER)) 1048 SET(code, TTY_FE); 1049 if (ISSET(ssr2, SCSSR2_PER)) 1050 SET(code, TTY_PE); 1051 } 1052 if ((*rint)(code, tp) == -1) { 1053 /* 1054 * The line discipline's buffer is out of space. 1055 */ 1056 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1057 /* 1058 * We're either not using flow control, or the 1059 * line discipline didn't tell us to block for 1060 * some reason. Either way, we have no way to 1061 * know when there's more space available, so 1062 * just drop the rest of the data. 1063 */ 1064 get += cc << 1; 1065 if (get >= end) 1066 get -= scif_rbuf_size << 1; 1067 cc = 0; 1068 } else { 1069 /* 1070 * Don't schedule any more receive processing 1071 * until the line discipline tells us there's 1072 * space available (through scifhwiflow()). 1073 * Leave the rest of the data in the input 1074 * buffer. 1075 */ 1076 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1077 } 1078 break; 1079 } 1080 get += 2; 1081 if (get >= end) 1082 get = sc->sc_rbuf; 1083 cc--; 1084 } 1085 1086 if (cc != scc) { 1087 sc->sc_rbget = get; 1088 s = splserial(); 1089 cc = sc->sc_rbavail += scc - cc; 1090 /* Buffers should be ok again, release possible block. */ 1091 if (cc >= sc->sc_r_lowat) { 1092 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1093 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1094 SHREG_SCSCR2 |= SCSCR2_RIE; 1095 } 1096 #if 0 1097 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1098 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1099 scif_hwiflow(sc); 1100 } 1101 #endif 1102 } 1103 splx(s); 1104 } 1105 } 1106 1107 integrate void 1108 scif_txsoft(struct scif_softc *sc, struct tty *tp) 1109 { 1110 1111 CLR(tp->t_state, TS_BUSY); 1112 if (ISSET(tp->t_state, TS_FLUSH)) 1113 CLR(tp->t_state, TS_FLUSH); 1114 else 1115 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1116 (*tp->t_linesw->l_start)(tp); 1117 } 1118 1119 integrate void 1120 scif_stsoft(struct scif_softc *sc, struct tty *tp) 1121 { 1122 #if 0 1123 /* XXX (msaitoh) */ 1124 u_char msr, delta; 1125 int s; 1126 1127 s = splserial(); 1128 msr = sc->sc_msr; 1129 delta = sc->sc_msr_delta; 1130 sc->sc_msr_delta = 0; 1131 splx(s); 1132 1133 if (ISSET(delta, sc->sc_msr_dcd)) { 1134 /* 1135 * Inform the tty layer that carrier detect changed. 1136 */ 1137 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1138 } 1139 1140 if (ISSET(delta, sc->sc_msr_cts)) { 1141 /* Block or unblock output according to flow control. */ 1142 if (ISSET(msr, sc->sc_msr_cts)) { 1143 sc->sc_tx_stopped = 0; 1144 (*tp->t_linesw->l_start)(tp); 1145 } else { 1146 sc->sc_tx_stopped = 1; 1147 } 1148 } 1149 1150 #ifdef SCIF_DEBUG 1151 if (scif_debug) 1152 scifstatus(sc, "scif_stsoft"); 1153 #endif 1154 #endif 1155 } 1156 1157 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1158 void 1159 scifsoft(void *arg) 1160 { 1161 struct scif_softc *sc = arg; 1162 struct tty *tp; 1163 1164 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1165 return; 1166 1167 { 1168 #else 1169 void 1170 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1171 scifsoft() 1172 #else 1173 scifsoft(void *arg) 1174 #endif 1175 { 1176 struct scif_softc *sc; 1177 struct tty *tp; 1178 int unit; 1179 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1180 int s; 1181 1182 s = splsoftserial(); 1183 scif_softintr_scheduled = 0; 1184 #endif 1185 1186 for (unit = 0; unit < scif_cd.cd_ndevs; unit++) { 1187 sc = scif_cd.cd_devs[unit]; 1188 if (sc == NULL || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK)) 1189 continue; 1190 1191 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1192 continue; 1193 1194 tp = sc->sc_tty; 1195 if (tp == NULL) 1196 continue; 1197 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 1198 continue; 1199 #endif 1200 tp = sc->sc_tty; 1201 1202 if (sc->sc_rx_ready) { 1203 sc->sc_rx_ready = 0; 1204 scif_rxsoft(sc, tp); 1205 } 1206 1207 #if 0 1208 if (sc->sc_st_check) { 1209 sc->sc_st_check = 0; 1210 scif_stsoft(sc, tp); 1211 } 1212 #endif 1213 1214 if (sc->sc_tx_done) { 1215 sc->sc_tx_done = 0; 1216 scif_txsoft(sc, tp); 1217 } 1218 } 1219 1220 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1221 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1222 splx(s); 1223 #endif 1224 #endif 1225 } 1226 1227 int 1228 scifintr(void *arg) 1229 { 1230 struct scif_softc *sc = arg; 1231 u_char *put, *end; 1232 u_int cc; 1233 u_short ssr2; 1234 int count; 1235 1236 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1237 return (0); 1238 1239 end = sc->sc_ebuf; 1240 put = sc->sc_rbput; 1241 cc = sc->sc_rbavail; 1242 1243 ssr2 = SHREG_SCSSR2; 1244 if (ISSET(ssr2, SCSSR2_BRK)) { 1245 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR); 1246 #ifdef DDB 1247 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 1248 console_debugger(); 1249 } 1250 #endif /* DDB */ 1251 #ifdef KGDB 1252 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) { 1253 kgdb_connect(1); 1254 } 1255 #endif /* KGDB */ 1256 } 1257 count = SHREG_SCFDR2 & SCFDR2_RECVCNT; 1258 if (count != 0) { 1259 while ((cc > 0) && (count > 0)) { 1260 put[0] = SHREG_SCFRDR2; 1261 put[1] = (u_char)(SHREG_SCSSR2 & 0x00ff); 1262 1263 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR); 1264 1265 put += 2; 1266 if (put >= end) 1267 put = sc->sc_rbuf; 1268 cc--; 1269 count--; 1270 } 1271 1272 /* 1273 * Current string of incoming characters ended because 1274 * no more data was available or we ran out of space. 1275 * Schedule a receive event if any data was received. 1276 * If we're out of space, turn off receive interrupts. 1277 */ 1278 sc->sc_rbput = put; 1279 sc->sc_rbavail = cc; 1280 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1281 sc->sc_rx_ready = 1; 1282 1283 /* 1284 * See if we are in danger of overflowing a buffer. If 1285 * so, use hardware flow control to ease the pressure. 1286 */ 1287 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1288 cc < sc->sc_r_hiwat) { 1289 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1290 #if 0 1291 scif_hwiflow(sc); 1292 #endif 1293 } 1294 1295 /* 1296 * If we're out of space, disable receive interrupts 1297 * until the queue has drained a bit. 1298 */ 1299 if (!cc) { 1300 SHREG_SCSCR2 &= ~SCSCR2_RIE; 1301 } 1302 } else { 1303 if (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR)) { 1304 SHREG_SCSCR2 &= ~(SCSCR2_TIE | SCSCR2_RIE); 1305 } 1306 } 1307 1308 #if 0 1309 msr = bus_space_read_1(iot, ioh, scif_msr); 1310 delta = msr ^ sc->sc_msr; 1311 sc->sc_msr = msr; 1312 if (ISSET(delta, sc->sc_msr_mask)) { 1313 SET(sc->sc_msr_delta, delta); 1314 1315 /* 1316 * Pulse-per-second clock signal on edge of DCD? 1317 */ 1318 if (ISSET(delta, sc->sc_ppsmask)) { 1319 struct timeval tv; 1320 if (ISSET(msr, sc->sc_ppsmask) == 1321 sc->sc_ppsassert) { 1322 /* XXX nanotime() */ 1323 microtime(&tv); 1324 TIMEVAL_TO_TIMESPEC(&tv, 1325 &sc->ppsinfo.assert_timestamp); 1326 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 1327 timespecadd(&sc->ppsinfo.assert_timestamp, 1328 &sc->ppsparam.assert_offset, 1329 &sc->ppsinfo.assert_timestamp); 1330 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp); 1331 } 1332 1333 #ifdef PPS_SYNC 1334 if (sc->ppsparam.mode & PPS_HARDPPSONASSERT) 1335 hardpps(&tv, tv.tv_usec); 1336 #endif 1337 sc->ppsinfo.assert_sequence++; 1338 sc->ppsinfo.current_mode = 1339 sc->ppsparam.mode; 1340 1341 } else if (ISSET(msr, sc->sc_ppsmask) == 1342 sc->sc_ppsclear) { 1343 /* XXX nanotime() */ 1344 microtime(&tv); 1345 TIMEVAL_TO_TIMESPEC(&tv, 1346 &sc->ppsinfo.clear_timestamp); 1347 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 1348 timespecadd(&sc->ppsinfo.clear_timestamp, 1349 &sc->ppsparam.clear_offset, 1350 &sc->ppsinfo.clear_timestamp); 1351 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp); 1352 } 1353 1354 #ifdef PPS_SYNC 1355 if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR) 1356 hardpps(&tv, tv.tv_usec); 1357 #endif 1358 sc->ppsinfo.clear_sequence++; 1359 sc->ppsinfo.current_mode = 1360 sc->ppsparam.mode; 1361 } 1362 } 1363 1364 /* 1365 * Stop output immediately if we lose the output 1366 * flow control signal or carrier detect. 1367 */ 1368 if (ISSET(~msr, sc->sc_msr_mask)) { 1369 sc->sc_tbc = 0; 1370 sc->sc_heldtbc = 0; 1371 #ifdef SCIF_DEBUG 1372 if (scif_debug) 1373 scifstatus(sc, "scifintr "); 1374 #endif 1375 } 1376 1377 sc->sc_st_check = 1; 1378 } 1379 #endif 1380 1381 /* 1382 * Done handling any receive interrupts. See if data can be 1383 * transmitted as well. Schedule tx done event if no data left 1384 * and tty was marked busy. 1385 */ 1386 if (((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */ 1387 /* 1388 * If we've delayed a parameter change, do it now, and restart 1389 * output. 1390 */ 1391 if (sc->sc_heldchange) { 1392 sc->sc_heldchange = 0; 1393 sc->sc_tbc = sc->sc_heldtbc; 1394 sc->sc_heldtbc = 0; 1395 } 1396 1397 /* Output the next chunk of the contiguous buffer, if any. */ 1398 if (sc->sc_tbc > 0) { 1399 int n; 1400 int max; 1401 int i; 1402 1403 n = sc->sc_tbc; 1404 max = sc->sc_fifolen - 1405 ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8); 1406 if (n > max) 1407 n = max; 1408 1409 for (i = 0; i < n; i++) { 1410 scif_putc(*(sc->sc_tba)); 1411 sc->sc_tba++; 1412 } 1413 sc->sc_tbc -= n; 1414 } else { 1415 /* Disable transmit completion interrupts if necessary. */ 1416 #if 0 1417 if (ISSET(sc->sc_ier, IER_ETXRDY)) 1418 #endif 1419 SHREG_SCSCR2 &= ~SCSCR2_TIE; 1420 1421 if (sc->sc_tx_busy) { 1422 sc->sc_tx_busy = 0; 1423 sc->sc_tx_done = 1; 1424 } 1425 } 1426 } 1427 1428 /* Wake up the poller. */ 1429 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1430 softintr_schedule(sc->sc_si); 1431 #else 1432 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1433 setsoftserial(); 1434 #else 1435 if (!scif_softintr_scheduled) { 1436 scif_softintr_scheduled = 1; 1437 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 1438 } 1439 #endif 1440 #endif 1441 1442 #if NRND > 0 && defined(RND_SCIF) 1443 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1444 #endif 1445 1446 return (1); 1447 } 1448 1449 void 1450 scifcnprobe(struct consdev *cp) 1451 { 1452 int maj; 1453 1454 /* locate the major number */ 1455 for (maj = 0; maj < nchrdev; maj++) 1456 if (cdevsw[maj].d_open == scifopen) 1457 break; 1458 1459 /* Initialize required fields. */ 1460 cp->cn_dev = makedev(maj, 0); 1461 #ifdef SCIFCONSOLE 1462 cp->cn_pri = CN_REMOTE; 1463 #else 1464 cp->cn_pri = CN_NORMAL; 1465 #endif 1466 } 1467 1468 void 1469 scifcninit(struct consdev *cp) 1470 { 1471 1472 InitializeScif(scifcn_speed); 1473 scifisconsole = 1; 1474 } 1475 1476 int 1477 scifcngetc(dev_t dev) 1478 { 1479 int c; 1480 int s; 1481 1482 s = splserial(); 1483 c = scif_getc(); 1484 splx(s); 1485 1486 return (c); 1487 } 1488 1489 void 1490 scifcnputc(dev_t dev, int c) 1491 { 1492 int s; 1493 1494 s = splserial(); 1495 scif_putc((u_char)c); 1496 splx(s); 1497 } 1498 1499 #ifdef KGDB 1500 int 1501 scif_kgdb_init() 1502 { 1503 1504 if (strcmp(kgdb_devname, "scif") != 0) 1505 return (1); 1506 1507 if (scifisconsole) 1508 return (1); /* can't share with console */ 1509 1510 InitializeScif(kgdb_rate); 1511 1512 kgdb_attach((int (*)(void *))scifcngetc, 1513 (void (*)(void *, int))scifcnputc, NULL); 1514 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 1515 kgdb_attached = 1; 1516 1517 return (0); 1518 } 1519 #endif /* KGDB */ 1520
Indexes created Sun Sep 28 12:09:53 GMT 2025