scif.c revision 1.29
1 /* $NetBSD: scif.c,v 1.29 2002/09/27 02:24:23 thorpej Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Charles M. Hannum. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the NetBSD 47 * Foundation, Inc. and its contributors. 48 * 4. Neither the name of The NetBSD Foundation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 53 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 54 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * Copyright (c) 1991 The Regents of the University of California. 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. All advertising materials mentioning features or use of this software 78 * must display the following acknowledgement: 79 * This product includes software developed by the University of 80 * California, Berkeley and its contributors. 81 * 4. Neither the name of the University nor the names of its contributors 82 * may be used to endorse or promote products derived from this software 83 * without specific prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 86 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 88 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 89 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 90 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 91 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 92 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 93 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 94 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 95 * SUCH DAMAGE. 96 * 97 * @(#)com.c 7.5 (Berkeley) 5/16/91 98 */ 99 100 /* 101 * SH internal serial driver 102 * 103 * This code is derived from both z8530tty.c and com.c 104 */ 105 106 #include "opt_kgdb.h" 107 #include "opt_scif.h" 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/tty.h> 112 #include <sys/proc.h> 113 #include <sys/conf.h> 114 #include <sys/file.h> 115 #include <sys/syslog.h> 116 #include <sys/kernel.h> 117 #include <sys/device.h> 118 #include <sys/malloc.h> 119 #include <sys/kgdb.h> 120 121 #include <dev/cons.h> 122 123 #include <sh3/clock.h> 124 #include <sh3/exception.h> 125 #include <sh3/scifreg.h> 126 #include <machine/intr.h> 127 128 #include <sh3/dev/scifvar.h> 129 130 #include "locators.h" 131 132 static void scifstart(struct tty *); 133 static int scifparam(struct tty *, struct termios *); 134 static int kgdb_attached; 135 136 void scifcnprobe(struct consdev *); 137 void scifcninit(struct consdev *); 138 void scifcnputc(dev_t, int); 139 int scifcngetc(dev_t); 140 void scifcnpoolc(dev_t, int); 141 void scif_intr_init(void); 142 int scifintr(void *); 143 144 struct scif_softc { 145 struct device sc_dev; /* boilerplate */ 146 struct tty *sc_tty; 147 void *sc_si; 148 149 struct callout sc_diag_ch; 150 151 #if 0 152 bus_space_tag_t sc_iot; /* ISA i/o space identifier */ 153 bus_space_handle_t sc_ioh; /* ISA io handle */ 154 155 int sc_drq; 156 157 int sc_frequency; 158 #endif 159 160 u_int sc_overflows, 161 sc_floods, 162 sc_errors; /* number of retries so far */ 163 u_char sc_status[7]; /* copy of registers */ 164 165 int sc_hwflags; 166 int sc_swflags; 167 u_int sc_fifolen; 168 169 u_int sc_r_hiwat, 170 sc_r_lowat; 171 u_char *volatile sc_rbget, 172 *volatile sc_rbput; 173 volatile u_int sc_rbavail; 174 u_char *sc_rbuf, 175 *sc_ebuf; 176 177 u_char *sc_tba; /* transmit buffer address */ 178 u_int sc_tbc, /* transmit byte count */ 179 sc_heldtbc; 180 181 volatile u_char sc_rx_flags, 182 #define RX_TTY_BLOCKED 0x01 183 #define RX_TTY_OVERFLOWED 0x02 184 #define RX_IBUF_BLOCKED 0x04 185 #define RX_IBUF_OVERFLOWED 0x08 186 #define RX_ANY_BLOCK 0x0f 187 sc_tx_busy, /* working on an output chunk */ 188 sc_tx_done, /* done with one output chunk */ 189 sc_tx_stopped, /* H/W level stop (lost CTS) */ 190 sc_st_check, /* got a status interrupt */ 191 sc_rx_ready; 192 193 volatile u_char sc_heldchange; 194 }; 195 196 /* controller driver configuration */ 197 static int scif_match(struct device *, struct cfdata *, void *); 198 static void scif_attach(struct device *, struct device *, void *); 199 200 void scif_break(struct scif_softc *, int); 201 void scif_iflush(struct scif_softc *); 202 203 #define integrate static inline 204 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 205 void scifsoft(void *); 206 #else 207 #ifndef __NO_SOFT_SERIAL_INTERRUPT 208 void scifsoft(void); 209 #else 210 void scifsoft(void *); 211 #endif 212 #endif 213 integrate void scif_rxsoft(struct scif_softc *, struct tty *); 214 integrate void scif_txsoft(struct scif_softc *, struct tty *); 215 integrate void scif_stsoft(struct scif_softc *, struct tty *); 216 integrate void scif_schedrx(struct scif_softc *); 217 void scifdiag(void *); 218 219 220 #define SCIFUNIT_MASK 0x7ffff 221 #define SCIFDIALOUT_MASK 0x80000 222 223 #define SCIFUNIT(x) (minor(x) & SCIFUNIT_MASK) 224 #define SCIFDIALOUT(x) (minor(x) & SCIFDIALOUT_MASK) 225 226 /* Macros to clear/set/test flags. */ 227 #define SET(t, f) (t) |= (f) 228 #define CLR(t, f) (t) &= ~(f) 229 #define ISSET(t, f) ((t) & (f)) 230 231 /* Hardware flag masks */ 232 #define SCIF_HW_NOIEN 0x01 233 #define SCIF_HW_FIFO 0x02 234 #define SCIF_HW_FLOW 0x08 235 #define SCIF_HW_DEV_OK 0x20 236 #define SCIF_HW_CONSOLE 0x40 237 #define SCIF_HW_KGDB 0x80 238 239 /* Buffer size for character buffer */ 240 #define SCIF_RING_SIZE 2048 241 242 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 243 u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4; 244 u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4; 245 246 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 247 int scifconscflag = CONMODE; 248 int scifisconsole = 0; 249 250 #ifdef SCIFCN_SPEED 251 unsigned int scifcn_speed = SCIFCN_SPEED; 252 #else 253 unsigned int scifcn_speed = 9600; 254 #endif 255 256 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 257 258 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 259 #ifdef __NO_SOFT_SERIAL_INTERRUPT 260 volatile int scif_softintr_scheduled; 261 struct callout scif_soft_ch = CALLOUT_INITIALIZER; 262 #endif 263 #endif 264 265 u_int scif_rbuf_size = SCIF_RING_SIZE; 266 267 struct cfattach scif_ca = { 268 sizeof(struct scif_softc), scif_match, scif_attach 269 }; 270 271 extern struct cfdriver scif_cd; 272 273 dev_type_open(scifopen); 274 dev_type_close(scifclose); 275 dev_type_read(scifread); 276 dev_type_write(scifwrite); 277 dev_type_ioctl(scifioctl); 278 dev_type_stop(scifstop); 279 dev_type_tty(sciftty); 280 dev_type_poll(scifpoll); 281 282 const struct cdevsw scif_cdevsw = { 283 scifopen, scifclose, scifread, scifwrite, scifioctl, 284 scifstop, sciftty, scifpoll, nommap, D_TTY 285 }; 286 287 void InitializeScif (unsigned int); 288 289 /* 290 * following functions are debugging prupose only 291 */ 292 #define CR 0x0D 293 #define USART_ON (unsigned int)~0x08 294 295 void scif_putc(unsigned char); 296 unsigned char scif_getc(void); 297 int ScifErrCheck(void); 298 299 /* 300 * InitializeScif 301 * : unsigned int bps; 302 * : SCIF(Serial Communication Interface) 303 */ 304 305 void 306 InitializeScif(unsigned int bps) 307 { 308 309 /* Initialize SCR */ 310 SHREG_SCSCR2 = 0x00; 311 312 #if 0 313 SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE; 314 #else 315 SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST; 316 #endif 317 /* Serial Mode Register */ 318 SHREG_SCSMR2 = 0x00; /* 8bit,NonParity,Even,1Stop */ 319 320 /* Bit Rate Register */ 321 SHREG_SCBRR2 = divrnd(sh_clock_get_pclock(), 32 * bps) - 1; 322 323 /* 324 * wait 1mSec, because Send/Recv must begin 1 bit period after 325 * BRR is set. 326 */ 327 delay(1000); 328 329 #if 0 330 SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE; 331 #else 332 SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1; 333 #endif 334 335 /* Send permission, Receive permission ON */ 336 SHREG_SCSCR2 = SCSCR2_TE | SCSCR2_RE; 337 338 /* Serial Status Register */ 339 SHREG_SCSSR2 &= SCSSR2_TDFE; /* Clear Status */ 340 } 341 342 343 /* 344 * scif_putc 345 * : unsigned char c; 346 */ 347 348 void 349 scif_putc(unsigned char c) 350 { 351 352 /* wait for ready */ 353 while ((SHREG_SCFDR2 & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) 354 ; 355 356 /* write send data to send register */ 357 SHREG_SCFTDR2 = c; 358 359 /* clear ready flag */ 360 SHREG_SCSSR2 &= ~(SCSSR2_TDFE | SCSSR2_TEND); 361 } 362 363 /* 364 * : ScifErrCheck 365 * 0x80 = error 366 * 0x08 = frame error 367 * 0x04 = parity error 368 */ 369 int 370 ScifErrCheck(void) 371 { 372 373 return(SHREG_SCSSR2 & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)); 374 } 375 376 /* 377 * scif_getc 378 */ 379 unsigned char 380 scif_getc(void) 381 { 382 unsigned char c, err_c; 383 #ifdef SH4 384 unsigned short err_c2; 385 #endif 386 387 while (1) { 388 /* wait for ready */ 389 while ((SHREG_SCFDR2 & SCFDR2_RECVCNT) == 0) 390 ; 391 392 c = SHREG_SCFRDR2; 393 err_c = SHREG_SCSSR2; 394 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF 395 | SCSSR2_DR); 396 #ifdef SH4 397 if (CPU_IS_SH4) { 398 err_c2 = SHREG_SCLSR2; 399 SHREG_SCLSR2 &= ~SCLSR2_ORER; 400 } 401 #endif 402 if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER 403 | SCSSR2_PER)) == 0) { 404 #ifdef SH4 405 if (CPU_IS_SH4 && ((err_c2 & SCLSR2_ORER) == 0)) 406 #endif 407 return(c); 408 } 409 } 410 411 } 412 413 #if 0 414 #define SCIF_MAX_UNITS 2 415 #else 416 #define SCIF_MAX_UNITS 1 417 #endif 418 419 420 static int 421 scif_match(struct device *parent, struct cfdata *cfp, void *aux) 422 { 423 424 if (strcmp(cfp->cf_name, "scif") 425 || cfp->cf_unit >= SCIF_MAX_UNITS) 426 return 0; 427 428 return 1; 429 } 430 431 static void 432 scif_attach(struct device *parent, struct device *self, void *aux) 433 { 434 struct scif_softc *sc = (struct scif_softc *)self; 435 struct tty *tp; 436 437 sc->sc_hwflags = 0; /* XXX */ 438 sc->sc_swflags = 0; /* XXX */ 439 sc->sc_fifolen = 16; 440 441 if (scifisconsole || kgdb_attached) { 442 /* InitializeScif(scifcn_speed); */ 443 SET(sc->sc_hwflags, SCIF_HW_CONSOLE); 444 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 445 if (kgdb_attached) { 446 SET(sc->sc_hwflags, SCIF_HW_KGDB); 447 printf("\n%s: kgdb\n", sc->sc_dev.dv_xname); 448 } else { 449 printf("\n%s: console\n", sc->sc_dev.dv_xname); 450 } 451 } else { 452 InitializeScif(9600); 453 printf("\n"); 454 } 455 456 callout_init(&sc->sc_diag_ch); 457 #ifdef SH4 458 intc_intr_establish(SH4_INTEVT_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 459 scifintr, sc); 460 intc_intr_establish(SH4_INTEVT_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 461 scifintr, sc); 462 intc_intr_establish(SH4_INTEVT_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 463 scifintr, sc); 464 intc_intr_establish(SH4_INTEVT_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 465 scifintr, sc); 466 #else 467 intc_intr_establish(SH7709_INTEVT2_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 468 scifintr, sc); 469 intc_intr_establish(SH7709_INTEVT2_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 470 scifintr, sc); 471 intc_intr_establish(SH7709_INTEVT2_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 472 scifintr, sc); 473 intc_intr_establish(SH7709_INTEVT2_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 474 scifintr, sc); 475 #endif 476 477 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 478 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, scifsoft, sc); 479 #endif 480 SET(sc->sc_hwflags, SCIF_HW_DEV_OK); 481 482 tp = ttymalloc(); 483 tp->t_oproc = scifstart; 484 tp->t_param = scifparam; 485 tp->t_hwiflow = NULL; 486 487 sc->sc_tty = tp; 488 sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 489 if (sc->sc_rbuf == NULL) { 490 printf("%s: unable to allocate ring buffer\n", 491 sc->sc_dev.dv_xname); 492 return; 493 } 494 sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1); 495 496 tty_attach(tp); 497 } 498 499 /* 500 * Start or restart transmission. 501 */ 502 static void 503 scifstart(struct tty *tp) 504 { 505 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 506 int s; 507 508 s = spltty(); 509 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 510 goto out; 511 if (sc->sc_tx_stopped) 512 goto out; 513 514 if (tp->t_outq.c_cc <= tp->t_lowat) { 515 if (ISSET(tp->t_state, TS_ASLEEP)) { 516 CLR(tp->t_state, TS_ASLEEP); 517 wakeup(&tp->t_outq); 518 } 519 selwakeup(&tp->t_wsel); 520 if (tp->t_outq.c_cc == 0) 521 goto out; 522 } 523 524 /* Grab the first contiguous region of buffer space. */ 525 { 526 u_char *tba; 527 int tbc; 528 529 tba = tp->t_outq.c_cf; 530 tbc = ndqb(&tp->t_outq, 0); 531 532 (void)splserial(); 533 534 sc->sc_tba = tba; 535 sc->sc_tbc = tbc; 536 } 537 538 SET(tp->t_state, TS_BUSY); 539 sc->sc_tx_busy = 1; 540 541 /* Enable transmit completion interrupts if necessary. */ 542 SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE; 543 544 /* Output the first chunk of the contiguous buffer. */ 545 { 546 int n; 547 int max; 548 int i; 549 550 n = sc->sc_tbc; 551 max = sc->sc_fifolen - ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8); 552 if (n > max) 553 n = max; 554 555 for (i = 0; i < n; i++) { 556 scif_putc(*(sc->sc_tba)); 557 sc->sc_tba++; 558 } 559 sc->sc_tbc -= n; 560 } 561 out: 562 splx(s); 563 return; 564 } 565 566 /* 567 * Set SCIF tty parameters from termios. 568 * XXX - Should just copy the whole termios after 569 * making sure all the changes could be done. 570 */ 571 static int 572 scifparam(struct tty *tp, struct termios *t) 573 { 574 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 575 int ospeed = t->c_ospeed; 576 int s; 577 578 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 579 return (EIO); 580 581 /* Check requested parameters. */ 582 if (ospeed < 0) 583 return (EINVAL); 584 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 585 return (EINVAL); 586 587 /* 588 * For the console, always force CLOCAL and !HUPCL, so that the port 589 * is always active. 590 */ 591 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 592 ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 593 SET(t->c_cflag, CLOCAL); 594 CLR(t->c_cflag, HUPCL); 595 } 596 597 /* 598 * If there were no changes, don't do anything. This avoids dropping 599 * input and improves performance when all we did was frob things like 600 * VMIN and VTIME. 601 */ 602 if (tp->t_ospeed == t->c_ospeed && 603 tp->t_cflag == t->c_cflag) 604 return (0); 605 606 #if 0 607 /* XXX (msaitoh) */ 608 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 609 #endif 610 611 s = splserial(); 612 613 /* 614 * Set the flow control pins depending on the current flow control 615 * mode. 616 */ 617 if (ISSET(t->c_cflag, CRTSCTS)) { 618 SHREG_SCFCR2 |= SCFCR2_MCE; 619 } else { 620 SHREG_SCFCR2 &= ~SCFCR2_MCE; 621 } 622 623 SHREG_SCBRR2 = divrnd(sh_clock_get_pclock(), 32 * ospeed) -1; 624 625 /* 626 * Set the FIFO threshold based on the receive speed. 627 * 628 * * If it's a low speed, it's probably a mouse or some other 629 * interactive device, so set the threshold low. 630 * * If it's a high speed, trim the trigger level down to prevent 631 * overflows. 632 * * Otherwise set it a bit higher. 633 */ 634 #if 0 635 /* XXX (msaitoh) */ 636 if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP)) 637 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 638 else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO)) 639 sc->sc_fifo = FIFO_ENABLE | 640 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : 641 t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4); 642 else 643 sc->sc_fifo = 0; 644 #endif 645 646 /* And copy to tty. */ 647 tp->t_ispeed = 0; 648 tp->t_ospeed = t->c_ospeed; 649 tp->t_cflag = t->c_cflag; 650 651 if (!sc->sc_heldchange) { 652 if (sc->sc_tx_busy) { 653 sc->sc_heldtbc = sc->sc_tbc; 654 sc->sc_tbc = 0; 655 sc->sc_heldchange = 1; 656 } 657 #if 0 658 /* XXX (msaitoh) */ 659 else 660 scif_loadchannelregs(sc); 661 #endif 662 } 663 664 if (!ISSET(t->c_cflag, CHWFLOW)) { 665 /* Disable the high water mark. */ 666 sc->sc_r_hiwat = 0; 667 sc->sc_r_lowat = 0; 668 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 669 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 670 scif_schedrx(sc); 671 } 672 } else { 673 sc->sc_r_hiwat = scif_rbuf_hiwat; 674 sc->sc_r_lowat = scif_rbuf_lowat; 675 } 676 677 splx(s); 678 679 #ifdef SCIF_DEBUG 680 if (scif_debug) 681 scifstatus(sc, "scifparam "); 682 #endif 683 684 if (!ISSET(t->c_cflag, CHWFLOW)) { 685 if (sc->sc_tx_stopped) { 686 sc->sc_tx_stopped = 0; 687 scifstart(tp); 688 } 689 } 690 691 return (0); 692 } 693 694 void 695 scif_iflush(struct scif_softc *sc) 696 { 697 int i; 698 unsigned char c; 699 700 i = SHREG_SCFDR2 & SCFDR2_RECVCNT; 701 702 while (i > 0) { 703 c = SHREG_SCFRDR2; 704 SHREG_SCSSR2 &= ~(SCSSR2_RDF | SCSSR2_DR); 705 i--; 706 } 707 } 708 709 int 710 scifopen(dev_t dev, int flag, int mode, struct proc *p) 711 { 712 int unit = SCIFUNIT(dev); 713 struct scif_softc *sc; 714 struct tty *tp; 715 int s, s2; 716 int error; 717 718 if (unit >= scif_cd.cd_ndevs) 719 return (ENXIO); 720 sc = scif_cd.cd_devs[unit]; 721 if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) || 722 sc->sc_rbuf == NULL) 723 return (ENXIO); 724 725 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 726 return (ENXIO); 727 728 #ifdef KGDB 729 /* 730 * If this is the kgdb port, no other use is permitted. 731 */ 732 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) 733 return (EBUSY); 734 #endif /* KGDB */ 735 736 tp = sc->sc_tty; 737 738 if (ISSET(tp->t_state, TS_ISOPEN) && 739 ISSET(tp->t_state, TS_XCLUDE) && 740 p->p_ucred->cr_uid != 0) 741 return (EBUSY); 742 743 s = spltty(); 744 745 /* 746 * Do the following iff this is a first open. 747 */ 748 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 749 struct termios t; 750 751 tp->t_dev = dev; 752 753 s2 = splserial(); 754 755 /* Turn on interrupts. */ 756 SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE; 757 758 splx(s2); 759 760 /* 761 * Initialize the termios status to the defaults. Add in the 762 * sticky bits from TIOCSFLAGS. 763 */ 764 t.c_ispeed = 0; 765 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 766 t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */ 767 t.c_cflag = scifconscflag; 768 } else { 769 t.c_ospeed = TTYDEF_SPEED; 770 t.c_cflag = TTYDEF_CFLAG; 771 } 772 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 773 SET(t.c_cflag, CLOCAL); 774 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 775 SET(t.c_cflag, CRTSCTS); 776 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 777 SET(t.c_cflag, MDMBUF); 778 /* Make sure scifparam() will do something. */ 779 tp->t_ospeed = 0; 780 (void) scifparam(tp, &t); 781 tp->t_iflag = TTYDEF_IFLAG; 782 tp->t_oflag = TTYDEF_OFLAG; 783 tp->t_lflag = TTYDEF_LFLAG; 784 ttychars(tp); 785 ttsetwater(tp); 786 787 s2 = splserial(); 788 789 /* Clear the input ring, and unblock. */ 790 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 791 sc->sc_rbavail = scif_rbuf_size; 792 scif_iflush(sc); 793 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 794 #if 0 795 /* XXX (msaitoh) */ 796 scif_hwiflow(sc); 797 #endif 798 799 #ifdef SCIF_DEBUG 800 if (scif_debug) 801 scifstatus(sc, "scifopen "); 802 #endif 803 804 splx(s2); 805 } 806 807 splx(s); 808 809 error = ttyopen(tp, SCIFDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 810 if (error) 811 goto bad; 812 813 error = (*tp->t_linesw->l_open)(dev, tp); 814 if (error) 815 goto bad; 816 817 return (0); 818 819 bad: 820 821 return (error); 822 } 823 824 int 825 scifclose(dev_t dev, int flag, int mode, struct proc *p) 826 { 827 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 828 struct tty *tp = sc->sc_tty; 829 830 /* XXX This is for cons.c. */ 831 if (!ISSET(tp->t_state, TS_ISOPEN)) 832 return (0); 833 834 (*tp->t_linesw->l_close)(tp, flag); 835 ttyclose(tp); 836 837 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 838 return (0); 839 840 return (0); 841 } 842 843 int 844 scifread(dev_t dev, struct uio *uio, int flag) 845 { 846 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 847 struct tty *tp = sc->sc_tty; 848 849 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 850 } 851 852 int 853 scifwrite(dev_t dev, struct uio *uio, int flag) 854 { 855 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 856 struct tty *tp = sc->sc_tty; 857 858 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 859 } 860 861 int 862 scifpoll(dev_t dev, int events, struct proc *p) 863 { 864 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 865 struct tty *tp = sc->sc_tty; 866 867 return ((*tp->t_linesw->l_poll)(tp, events, p)); 868 } 869 870 struct tty * 871 sciftty(dev_t dev) 872 { 873 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 874 struct tty *tp = sc->sc_tty; 875 876 return (tp); 877 } 878 879 int 880 scifioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 881 { 882 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 883 struct tty *tp = sc->sc_tty; 884 int error; 885 int s; 886 887 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 888 return (EIO); 889 890 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 891 if (error != EPASSTHROUGH) 892 return (error); 893 894 error = ttioctl(tp, cmd, data, flag, p); 895 if (error != EPASSTHROUGH) 896 return (error); 897 898 error = 0; 899 900 s = splserial(); 901 902 switch (cmd) { 903 case TIOCSBRK: 904 scif_break(sc, 1); 905 break; 906 907 case TIOCCBRK: 908 scif_break(sc, 0); 909 break; 910 911 case TIOCGFLAGS: 912 *(int *)data = sc->sc_swflags; 913 break; 914 915 case TIOCSFLAGS: 916 error = suser(p->p_ucred, &p->p_acflag); 917 if (error) 918 break; 919 sc->sc_swflags = *(int *)data; 920 break; 921 922 default: 923 error = EPASSTHROUGH; 924 break; 925 } 926 927 splx(s); 928 929 return (error); 930 } 931 932 integrate void 933 scif_schedrx(struct scif_softc *sc) 934 { 935 936 sc->sc_rx_ready = 1; 937 938 /* Wake up the poller. */ 939 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 940 softintr_schedule(sc->sc_si); 941 #else 942 #ifndef __NO_SOFT_SERIAL_INTERRUPT 943 setsoftserial(); 944 #else 945 if (!scif_softintr_scheduled) { 946 scif_softintr_scheduled = 1; 947 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 948 } 949 #endif 950 #endif 951 } 952 953 void 954 scif_break(struct scif_softc *sc, int onoff) 955 { 956 957 if (onoff) 958 SHREG_SCSSR2 &= ~SCSSR2_TDFE; 959 else 960 SHREG_SCSSR2 |= SCSSR2_TDFE; 961 962 #if 0 /* XXX */ 963 if (!sc->sc_heldchange) { 964 if (sc->sc_tx_busy) { 965 sc->sc_heldtbc = sc->sc_tbc; 966 sc->sc_tbc = 0; 967 sc->sc_heldchange = 1; 968 } else 969 scif_loadchannelregs(sc); 970 } 971 #endif 972 } 973 974 /* 975 * Stop output, e.g., for ^S or output flush. 976 */ 977 void 978 scifstop(struct tty *tp, int flag) 979 { 980 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 981 int s; 982 983 s = splserial(); 984 if (ISSET(tp->t_state, TS_BUSY)) { 985 /* Stop transmitting at the next chunk. */ 986 sc->sc_tbc = 0; 987 sc->sc_heldtbc = 0; 988 if (!ISSET(tp->t_state, TS_TTSTOP)) 989 SET(tp->t_state, TS_FLUSH); 990 } 991 splx(s); 992 } 993 994 void 995 scif_intr_init() 996 { 997 /* XXX */ 998 } 999 1000 void 1001 scifdiag(void *arg) 1002 { 1003 struct scif_softc *sc = arg; 1004 int overflows, floods; 1005 int s; 1006 1007 s = splserial(); 1008 overflows = sc->sc_overflows; 1009 sc->sc_overflows = 0; 1010 floods = sc->sc_floods; 1011 sc->sc_floods = 0; 1012 sc->sc_errors = 0; 1013 splx(s); 1014 1015 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1016 sc->sc_dev.dv_xname, 1017 overflows, overflows == 1 ? "" : "s", 1018 floods, floods == 1 ? "" : "s"); 1019 } 1020 1021 integrate void 1022 scif_rxsoft(struct scif_softc *sc, struct tty *tp) 1023 { 1024 int (*rint)(int c, struct tty *tp) = tp->t_linesw->l_rint; 1025 u_char *get, *end; 1026 u_int cc, scc; 1027 u_char ssr2; 1028 int code; 1029 int s; 1030 1031 end = sc->sc_ebuf; 1032 get = sc->sc_rbget; 1033 scc = cc = scif_rbuf_size - sc->sc_rbavail; 1034 1035 if (cc == scif_rbuf_size) { 1036 sc->sc_floods++; 1037 if (sc->sc_errors++ == 0) 1038 callout_reset(&sc->sc_diag_ch, 60 * hz, scifdiag, sc); 1039 } 1040 1041 while (cc) { 1042 code = get[0]; 1043 ssr2 = get[1]; 1044 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) { 1045 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER)) 1046 SET(code, TTY_FE); 1047 if (ISSET(ssr2, SCSSR2_PER)) 1048 SET(code, TTY_PE); 1049 } 1050 if ((*rint)(code, tp) == -1) { 1051 /* 1052 * The line discipline's buffer is out of space. 1053 */ 1054 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1055 /* 1056 * We're either not using flow control, or the 1057 * line discipline didn't tell us to block for 1058 * some reason. Either way, we have no way to 1059 * know when there's more space available, so 1060 * just drop the rest of the data. 1061 */ 1062 get += cc << 1; 1063 if (get >= end) 1064 get -= scif_rbuf_size << 1; 1065 cc = 0; 1066 } else { 1067 /* 1068 * Don't schedule any more receive processing 1069 * until the line discipline tells us there's 1070 * space available (through scifhwiflow()). 1071 * Leave the rest of the data in the input 1072 * buffer. 1073 */ 1074 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1075 } 1076 break; 1077 } 1078 get += 2; 1079 if (get >= end) 1080 get = sc->sc_rbuf; 1081 cc--; 1082 } 1083 1084 if (cc != scc) { 1085 sc->sc_rbget = get; 1086 s = splserial(); 1087 cc = sc->sc_rbavail += scc - cc; 1088 /* Buffers should be ok again, release possible block. */ 1089 if (cc >= sc->sc_r_lowat) { 1090 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1091 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1092 SHREG_SCSCR2 |= SCSCR2_RIE; 1093 } 1094 #if 0 1095 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1096 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1097 scif_hwiflow(sc); 1098 } 1099 #endif 1100 } 1101 splx(s); 1102 } 1103 } 1104 1105 integrate void 1106 scif_txsoft(struct scif_softc *sc, struct tty *tp) 1107 { 1108 1109 CLR(tp->t_state, TS_BUSY); 1110 if (ISSET(tp->t_state, TS_FLUSH)) 1111 CLR(tp->t_state, TS_FLUSH); 1112 else 1113 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1114 (*tp->t_linesw->l_start)(tp); 1115 } 1116 1117 integrate void 1118 scif_stsoft(struct scif_softc *sc, struct tty *tp) 1119 { 1120 #if 0 1121 /* XXX (msaitoh) */ 1122 u_char msr, delta; 1123 int s; 1124 1125 s = splserial(); 1126 msr = sc->sc_msr; 1127 delta = sc->sc_msr_delta; 1128 sc->sc_msr_delta = 0; 1129 splx(s); 1130 1131 if (ISSET(delta, sc->sc_msr_dcd)) { 1132 /* 1133 * Inform the tty layer that carrier detect changed. 1134 */ 1135 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1136 } 1137 1138 if (ISSET(delta, sc->sc_msr_cts)) { 1139 /* Block or unblock output according to flow control. */ 1140 if (ISSET(msr, sc->sc_msr_cts)) { 1141 sc->sc_tx_stopped = 0; 1142 (*tp->t_linesw->l_start)(tp); 1143 } else { 1144 sc->sc_tx_stopped = 1; 1145 } 1146 } 1147 1148 #ifdef SCIF_DEBUG 1149 if (scif_debug) 1150 scifstatus(sc, "scif_stsoft"); 1151 #endif 1152 #endif 1153 } 1154 1155 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1156 void 1157 scifsoft(void *arg) 1158 { 1159 struct scif_softc *sc = arg; 1160 struct tty *tp; 1161 1162 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1163 return; 1164 1165 { 1166 #else 1167 void 1168 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1169 scifsoft() 1170 #else 1171 scifsoft(void *arg) 1172 #endif 1173 { 1174 struct scif_softc *sc; 1175 struct tty *tp; 1176 int unit; 1177 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1178 int s; 1179 1180 s = splsoftserial(); 1181 scif_softintr_scheduled = 0; 1182 #endif 1183 1184 for (unit = 0; unit < scif_cd.cd_ndevs; unit++) { 1185 sc = scif_cd.cd_devs[unit]; 1186 if (sc == NULL || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK)) 1187 continue; 1188 1189 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1190 continue; 1191 1192 tp = sc->sc_tty; 1193 if (tp == NULL) 1194 continue; 1195 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 1196 continue; 1197 #endif 1198 tp = sc->sc_tty; 1199 1200 if (sc->sc_rx_ready) { 1201 sc->sc_rx_ready = 0; 1202 scif_rxsoft(sc, tp); 1203 } 1204 1205 #if 0 1206 if (sc->sc_st_check) { 1207 sc->sc_st_check = 0; 1208 scif_stsoft(sc, tp); 1209 } 1210 #endif 1211 1212 if (sc->sc_tx_done) { 1213 sc->sc_tx_done = 0; 1214 scif_txsoft(sc, tp); 1215 } 1216 } 1217 1218 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1219 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1220 splx(s); 1221 #endif 1222 #endif 1223 } 1224 1225 int 1226 scifintr(void *arg) 1227 { 1228 struct scif_softc *sc = arg; 1229 u_char *put, *end; 1230 u_int cc; 1231 u_short ssr2; 1232 int count; 1233 1234 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1235 return (0); 1236 1237 end = sc->sc_ebuf; 1238 put = sc->sc_rbput; 1239 cc = sc->sc_rbavail; 1240 1241 do { 1242 ssr2 = SHREG_SCSSR2; 1243 if (ISSET(ssr2, SCSSR2_BRK)) { 1244 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR); 1245 #ifdef DDB 1246 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 1247 console_debugger(); 1248 } 1249 #endif /* DDB */ 1250 #ifdef KGDB 1251 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) { 1252 kgdb_connect(1); 1253 } 1254 #endif /* KGDB */ 1255 } 1256 count = SHREG_SCFDR2 & SCFDR2_RECVCNT; 1257 if (count != 0) { 1258 while (1) { 1259 u_char c = SHREG_SCFRDR2; 1260 u_char err = (u_char)(SHREG_SCSSR2 & 0x00ff); 1261 1262 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR); 1263 #ifdef SH4 1264 if (CPU_IS_SH4) 1265 SHREG_SCLSR2 &= ~SCLSR2_ORER; 1266 #endif 1267 if ((cc > 0) && (count > 0)) { 1268 put[0] = c; 1269 put[1] = err; 1270 put += 2; 1271 if (put >= end) 1272 put = sc->sc_rbuf; 1273 cc--; 1274 count--; 1275 } else 1276 break; 1277 } 1278 1279 /* 1280 * Current string of incoming characters ended because 1281 * no more data was available or we ran out of space. 1282 * Schedule a receive event if any data was received. 1283 * If we're out of space, turn off receive interrupts. 1284 */ 1285 sc->sc_rbput = put; 1286 sc->sc_rbavail = cc; 1287 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1288 sc->sc_rx_ready = 1; 1289 1290 /* 1291 * See if we are in danger of overflowing a buffer. If 1292 * so, use hardware flow control to ease the pressure. 1293 */ 1294 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1295 cc < sc->sc_r_hiwat) { 1296 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1297 #if 0 1298 scif_hwiflow(sc); 1299 #endif 1300 } 1301 1302 /* 1303 * If we're out of space, disable receive interrupts 1304 * until the queue has drained a bit. 1305 */ 1306 if (!cc) { 1307 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1308 SHREG_SCSCR2 &= ~SCSCR2_RIE; 1309 } 1310 } else { 1311 if (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR)) { 1312 SHREG_SCSCR2 &= ~(SCSCR2_TIE | SCSCR2_RIE); 1313 delay(10); 1314 SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE; 1315 continue; 1316 } 1317 } 1318 } while (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR)); 1319 1320 #if 0 1321 msr = bus_space_read_1(iot, ioh, scif_msr); 1322 delta = msr ^ sc->sc_msr; 1323 sc->sc_msr = msr; 1324 if (ISSET(delta, sc->sc_msr_mask)) { 1325 SET(sc->sc_msr_delta, delta); 1326 1327 /* 1328 * Pulse-per-second clock signal on edge of DCD? 1329 */ 1330 if (ISSET(delta, sc->sc_ppsmask)) { 1331 struct timeval tv; 1332 if (ISSET(msr, sc->sc_ppsmask) == 1333 sc->sc_ppsassert) { 1334 /* XXX nanotime() */ 1335 microtime(&tv); 1336 TIMEVAL_TO_TIMESPEC(&tv, 1337 &sc->ppsinfo.assert_timestamp); 1338 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 1339 timespecadd(&sc->ppsinfo.assert_timestamp, 1340 &sc->ppsparam.assert_offset, 1341 &sc->ppsinfo.assert_timestamp); 1342 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp); 1343 } 1344 1345 #ifdef PPS_SYNC 1346 if (sc->ppsparam.mode & PPS_HARDPPSONASSERT) 1347 hardpps(&tv, tv.tv_usec); 1348 #endif 1349 sc->ppsinfo.assert_sequence++; 1350 sc->ppsinfo.current_mode = 1351 sc->ppsparam.mode; 1352 1353 } else if (ISSET(msr, sc->sc_ppsmask) == 1354 sc->sc_ppsclear) { 1355 /* XXX nanotime() */ 1356 microtime(&tv); 1357 TIMEVAL_TO_TIMESPEC(&tv, 1358 &sc->ppsinfo.clear_timestamp); 1359 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 1360 timespecadd(&sc->ppsinfo.clear_timestamp, 1361 &sc->ppsparam.clear_offset, 1362 &sc->ppsinfo.clear_timestamp); 1363 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp); 1364 } 1365 1366 #ifdef PPS_SYNC 1367 if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR) 1368 hardpps(&tv, tv.tv_usec); 1369 #endif 1370 sc->ppsinfo.clear_sequence++; 1371 sc->ppsinfo.current_mode = 1372 sc->ppsparam.mode; 1373 } 1374 } 1375 1376 /* 1377 * Stop output immediately if we lose the output 1378 * flow control signal or carrier detect. 1379 */ 1380 if (ISSET(~msr, sc->sc_msr_mask)) { 1381 sc->sc_tbc = 0; 1382 sc->sc_heldtbc = 0; 1383 #ifdef SCIF_DEBUG 1384 if (scif_debug) 1385 scifstatus(sc, "scifintr "); 1386 #endif 1387 } 1388 1389 sc->sc_st_check = 1; 1390 } 1391 #endif 1392 1393 /* 1394 * Done handling any receive interrupts. See if data can be 1395 * transmitted as well. Schedule tx done event if no data left 1396 * and tty was marked busy. 1397 */ 1398 if (((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */ 1399 /* 1400 * If we've delayed a parameter change, do it now, and restart 1401 * output. 1402 */ 1403 if (sc->sc_heldchange) { 1404 sc->sc_heldchange = 0; 1405 sc->sc_tbc = sc->sc_heldtbc; 1406 sc->sc_heldtbc = 0; 1407 } 1408 1409 /* Output the next chunk of the contiguous buffer, if any. */ 1410 if (sc->sc_tbc > 0) { 1411 int n; 1412 int max; 1413 int i; 1414 1415 n = sc->sc_tbc; 1416 max = sc->sc_fifolen - 1417 ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8); 1418 if (n > max) 1419 n = max; 1420 1421 for (i = 0; i < n; i++) { 1422 scif_putc(*(sc->sc_tba)); 1423 sc->sc_tba++; 1424 } 1425 sc->sc_tbc -= n; 1426 } else { 1427 /* Disable transmit completion interrupts if necessary. */ 1428 #if 0 1429 if (ISSET(sc->sc_ier, IER_ETXRDY)) 1430 #endif 1431 SHREG_SCSCR2 &= ~SCSCR2_TIE; 1432 1433 if (sc->sc_tx_busy) { 1434 sc->sc_tx_busy = 0; 1435 sc->sc_tx_done = 1; 1436 } 1437 } 1438 } 1439 1440 /* Wake up the poller. */ 1441 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1442 softintr_schedule(sc->sc_si); 1443 #else 1444 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1445 setsoftserial(); 1446 #else 1447 if (!scif_softintr_scheduled) { 1448 scif_softintr_scheduled = 1; 1449 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 1450 } 1451 #endif 1452 #endif 1453 1454 #if NRND > 0 && defined(RND_SCIF) 1455 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1456 #endif 1457 1458 return (1); 1459 } 1460 1461 void 1462 scifcnprobe(struct consdev *cp) 1463 { 1464 int maj; 1465 1466 /* locate the major number */ 1467 maj = cdevsw_lookup_major(&scif_cdevsw); 1468 1469 /* Initialize required fields. */ 1470 cp->cn_dev = makedev(maj, 0); 1471 #ifdef SCIFCONSOLE 1472 cp->cn_pri = CN_REMOTE; 1473 #else 1474 cp->cn_pri = CN_NORMAL; 1475 #endif 1476 } 1477 1478 void 1479 scifcninit(struct consdev *cp) 1480 { 1481 1482 InitializeScif(scifcn_speed); 1483 scifisconsole = 1; 1484 } 1485 1486 int 1487 scifcngetc(dev_t dev) 1488 { 1489 int c; 1490 int s; 1491 1492 s = splserial(); 1493 c = scif_getc(); 1494 splx(s); 1495 1496 return (c); 1497 } 1498 1499 void 1500 scifcnputc(dev_t dev, int c) 1501 { 1502 int s; 1503 1504 s = splserial(); 1505 scif_putc((u_char)c); 1506 splx(s); 1507 } 1508 1509 #ifdef KGDB 1510 int 1511 scif_kgdb_init() 1512 { 1513 1514 if (strcmp(kgdb_devname, "scif") != 0) 1515 return (1); 1516 1517 if (scifisconsole) 1518 return (1); /* can't share with console */ 1519 1520 InitializeScif(kgdb_rate); 1521 1522 kgdb_attach((int (*)(void *))scifcngetc, 1523 (void (*)(void *, int))scifcnputc, NULL); 1524 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 1525 kgdb_attached = 1; 1526 1527 return (0); 1528 } 1529 #endif /* KGDB */ 1530
Indexes created Tue Sep 23 07:09:52 GMT 2025