scif.c revision 1.31
1 /* $NetBSD: scif.c,v 1.31 2002/10/01 21:24:43 thorpej Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Charles M. Hannum. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the NetBSD 47 * Foundation, Inc. and its contributors. 48 * 4. Neither the name of The NetBSD Foundation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 53 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 54 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * Copyright (c) 1991 The Regents of the University of California. 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. All advertising materials mentioning features or use of this software 78 * must display the following acknowledgement: 79 * This product includes software developed by the University of 80 * California, Berkeley and its contributors. 81 * 4. Neither the name of the University nor the names of its contributors 82 * may be used to endorse or promote products derived from this software 83 * without specific prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 86 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 88 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 89 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 90 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 91 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 92 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 93 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 94 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 95 * SUCH DAMAGE. 96 * 97 * @(#)com.c 7.5 (Berkeley) 5/16/91 98 */ 99 100 /* 101 * SH internal serial driver 102 * 103 * This code is derived from both z8530tty.c and com.c 104 */ 105 106 #include "opt_kgdb.h" 107 #include "opt_scif.h" 108 109 #include <sys/param.h> 110 #include <sys/systm.h> 111 #include <sys/tty.h> 112 #include <sys/proc.h> 113 #include <sys/conf.h> 114 #include <sys/file.h> 115 #include <sys/syslog.h> 116 #include <sys/kernel.h> 117 #include <sys/device.h> 118 #include <sys/malloc.h> 119 #include <sys/kgdb.h> 120 121 #include <dev/cons.h> 122 123 #include <sh3/clock.h> 124 #include <sh3/exception.h> 125 #include <sh3/scifreg.h> 126 #include <machine/intr.h> 127 128 #include <sh3/dev/scifvar.h> 129 130 #include "locators.h" 131 132 static void scifstart(struct tty *); 133 static int scifparam(struct tty *, struct termios *); 134 static int kgdb_attached; 135 136 void scifcnprobe(struct consdev *); 137 void scifcninit(struct consdev *); 138 void scifcnputc(dev_t, int); 139 int scifcngetc(dev_t); 140 void scifcnpoolc(dev_t, int); 141 void scif_intr_init(void); 142 int scifintr(void *); 143 144 struct scif_softc { 145 struct device sc_dev; /* boilerplate */ 146 struct tty *sc_tty; 147 void *sc_si; 148 149 struct callout sc_diag_ch; 150 151 #if 0 152 bus_space_tag_t sc_iot; /* ISA i/o space identifier */ 153 bus_space_handle_t sc_ioh; /* ISA io handle */ 154 155 int sc_drq; 156 157 int sc_frequency; 158 #endif 159 160 u_int sc_overflows, 161 sc_floods, 162 sc_errors; /* number of retries so far */ 163 u_char sc_status[7]; /* copy of registers */ 164 165 int sc_hwflags; 166 int sc_swflags; 167 u_int sc_fifolen; 168 169 u_int sc_r_hiwat, 170 sc_r_lowat; 171 u_char *volatile sc_rbget, 172 *volatile sc_rbput; 173 volatile u_int sc_rbavail; 174 u_char *sc_rbuf, 175 *sc_ebuf; 176 177 u_char *sc_tba; /* transmit buffer address */ 178 u_int sc_tbc, /* transmit byte count */ 179 sc_heldtbc; 180 181 volatile u_char sc_rx_flags, 182 #define RX_TTY_BLOCKED 0x01 183 #define RX_TTY_OVERFLOWED 0x02 184 #define RX_IBUF_BLOCKED 0x04 185 #define RX_IBUF_OVERFLOWED 0x08 186 #define RX_ANY_BLOCK 0x0f 187 sc_tx_busy, /* working on an output chunk */ 188 sc_tx_done, /* done with one output chunk */ 189 sc_tx_stopped, /* H/W level stop (lost CTS) */ 190 sc_st_check, /* got a status interrupt */ 191 sc_rx_ready; 192 193 volatile u_char sc_heldchange; 194 }; 195 196 /* controller driver configuration */ 197 static int scif_match(struct device *, struct cfdata *, void *); 198 static void scif_attach(struct device *, struct device *, void *); 199 200 void scif_break(struct scif_softc *, int); 201 void scif_iflush(struct scif_softc *); 202 203 #define integrate static inline 204 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 205 void scifsoft(void *); 206 #else 207 #ifndef __NO_SOFT_SERIAL_INTERRUPT 208 void scifsoft(void); 209 #else 210 void scifsoft(void *); 211 #endif 212 #endif 213 integrate void scif_rxsoft(struct scif_softc *, struct tty *); 214 integrate void scif_txsoft(struct scif_softc *, struct tty *); 215 integrate void scif_stsoft(struct scif_softc *, struct tty *); 216 integrate void scif_schedrx(struct scif_softc *); 217 void scifdiag(void *); 218 219 220 #define SCIFUNIT_MASK 0x7ffff 221 #define SCIFDIALOUT_MASK 0x80000 222 223 #define SCIFUNIT(x) (minor(x) & SCIFUNIT_MASK) 224 #define SCIFDIALOUT(x) (minor(x) & SCIFDIALOUT_MASK) 225 226 /* Macros to clear/set/test flags. */ 227 #define SET(t, f) (t) |= (f) 228 #define CLR(t, f) (t) &= ~(f) 229 #define ISSET(t, f) ((t) & (f)) 230 231 /* Hardware flag masks */ 232 #define SCIF_HW_NOIEN 0x01 233 #define SCIF_HW_FIFO 0x02 234 #define SCIF_HW_FLOW 0x08 235 #define SCIF_HW_DEV_OK 0x20 236 #define SCIF_HW_CONSOLE 0x40 237 #define SCIF_HW_KGDB 0x80 238 239 /* Buffer size for character buffer */ 240 #define SCIF_RING_SIZE 2048 241 242 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 243 u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4; 244 u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4; 245 246 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 247 int scifconscflag = CONMODE; 248 int scifisconsole = 0; 249 250 #ifdef SCIFCN_SPEED 251 unsigned int scifcn_speed = SCIFCN_SPEED; 252 #else 253 unsigned int scifcn_speed = 9600; 254 #endif 255 256 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 257 258 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 259 #ifdef __NO_SOFT_SERIAL_INTERRUPT 260 volatile int scif_softintr_scheduled; 261 struct callout scif_soft_ch = CALLOUT_INITIALIZER; 262 #endif 263 #endif 264 265 u_int scif_rbuf_size = SCIF_RING_SIZE; 266 267 CFATTACH_DECL(scif, sizeof(struct scif_softc), 268 scif_match, scif_attach, NULL, NULL) 269 270 extern struct cfdriver scif_cd; 271 272 dev_type_open(scifopen); 273 dev_type_close(scifclose); 274 dev_type_read(scifread); 275 dev_type_write(scifwrite); 276 dev_type_ioctl(scifioctl); 277 dev_type_stop(scifstop); 278 dev_type_tty(sciftty); 279 dev_type_poll(scifpoll); 280 281 const struct cdevsw scif_cdevsw = { 282 scifopen, scifclose, scifread, scifwrite, scifioctl, 283 scifstop, sciftty, scifpoll, nommap, D_TTY 284 }; 285 286 void InitializeScif (unsigned int); 287 288 /* 289 * following functions are debugging prupose only 290 */ 291 #define CR 0x0D 292 #define USART_ON (unsigned int)~0x08 293 294 void scif_putc(unsigned char); 295 unsigned char scif_getc(void); 296 int ScifErrCheck(void); 297 298 /* 299 * InitializeScif 300 * : unsigned int bps; 301 * : SCIF(Serial Communication Interface) 302 */ 303 304 void 305 InitializeScif(unsigned int bps) 306 { 307 308 /* Initialize SCR */ 309 SHREG_SCSCR2 = 0x00; 310 311 #if 0 312 SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE; 313 #else 314 SHREG_SCFCR2 = SCFCR2_TFRST | SCFCR2_RFRST; 315 #endif 316 /* Serial Mode Register */ 317 SHREG_SCSMR2 = 0x00; /* 8bit,NonParity,Even,1Stop */ 318 319 /* Bit Rate Register */ 320 SHREG_SCBRR2 = divrnd(sh_clock_get_pclock(), 32 * bps) - 1; 321 322 /* 323 * wait 1mSec, because Send/Recv must begin 1 bit period after 324 * BRR is set. 325 */ 326 delay(1000); 327 328 #if 0 329 SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE; 330 #else 331 SHREG_SCFCR2 = FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1; 332 #endif 333 334 /* Send permission, Receive permission ON */ 335 SHREG_SCSCR2 = SCSCR2_TE | SCSCR2_RE; 336 337 /* Serial Status Register */ 338 SHREG_SCSSR2 &= SCSSR2_TDFE; /* Clear Status */ 339 } 340 341 342 /* 343 * scif_putc 344 * : unsigned char c; 345 */ 346 347 void 348 scif_putc(unsigned char c) 349 { 350 351 /* wait for ready */ 352 while ((SHREG_SCFDR2 & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) 353 ; 354 355 /* write send data to send register */ 356 SHREG_SCFTDR2 = c; 357 358 /* clear ready flag */ 359 SHREG_SCSSR2 &= ~(SCSSR2_TDFE | SCSSR2_TEND); 360 } 361 362 /* 363 * : ScifErrCheck 364 * 0x80 = error 365 * 0x08 = frame error 366 * 0x04 = parity error 367 */ 368 int 369 ScifErrCheck(void) 370 { 371 372 return(SHREG_SCSSR2 & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)); 373 } 374 375 /* 376 * scif_getc 377 */ 378 unsigned char 379 scif_getc(void) 380 { 381 unsigned char c, err_c; 382 #ifdef SH4 383 unsigned short err_c2; 384 #endif 385 386 while (1) { 387 /* wait for ready */ 388 while ((SHREG_SCFDR2 & SCFDR2_RECVCNT) == 0) 389 ; 390 391 c = SHREG_SCFRDR2; 392 err_c = SHREG_SCSSR2; 393 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF 394 | SCSSR2_DR); 395 #ifdef SH4 396 if (CPU_IS_SH4) { 397 err_c2 = SHREG_SCLSR2; 398 SHREG_SCLSR2 &= ~SCLSR2_ORER; 399 } 400 #endif 401 if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER 402 | SCSSR2_PER)) == 0) { 403 #ifdef SH4 404 if (CPU_IS_SH4 && ((err_c2 & SCLSR2_ORER) == 0)) 405 #endif 406 return(c); 407 } 408 } 409 410 } 411 412 #if 0 413 #define SCIF_MAX_UNITS 2 414 #else 415 #define SCIF_MAX_UNITS 1 416 #endif 417 418 419 static int 420 scif_match(struct device *parent, struct cfdata *cfp, void *aux) 421 { 422 423 if (strcmp(cfp->cf_name, "scif") 424 || cfp->cf_unit >= SCIF_MAX_UNITS) 425 return 0; 426 427 return 1; 428 } 429 430 static void 431 scif_attach(struct device *parent, struct device *self, void *aux) 432 { 433 struct scif_softc *sc = (struct scif_softc *)self; 434 struct tty *tp; 435 436 sc->sc_hwflags = 0; /* XXX */ 437 sc->sc_swflags = 0; /* XXX */ 438 sc->sc_fifolen = 16; 439 440 if (scifisconsole || kgdb_attached) { 441 /* InitializeScif(scifcn_speed); */ 442 SET(sc->sc_hwflags, SCIF_HW_CONSOLE); 443 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 444 if (kgdb_attached) { 445 SET(sc->sc_hwflags, SCIF_HW_KGDB); 446 printf("\n%s: kgdb\n", sc->sc_dev.dv_xname); 447 } else { 448 printf("\n%s: console\n", sc->sc_dev.dv_xname); 449 } 450 } else { 451 InitializeScif(9600); 452 printf("\n"); 453 } 454 455 callout_init(&sc->sc_diag_ch); 456 #ifdef SH4 457 intc_intr_establish(SH4_INTEVT_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 458 scifintr, sc); 459 intc_intr_establish(SH4_INTEVT_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 460 scifintr, sc); 461 intc_intr_establish(SH4_INTEVT_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 462 scifintr, sc); 463 intc_intr_establish(SH4_INTEVT_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 464 scifintr, sc); 465 #else 466 intc_intr_establish(SH7709_INTEVT2_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 467 scifintr, sc); 468 intc_intr_establish(SH7709_INTEVT2_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 469 scifintr, sc); 470 intc_intr_establish(SH7709_INTEVT2_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 471 scifintr, sc); 472 intc_intr_establish(SH7709_INTEVT2_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 473 scifintr, sc); 474 #endif 475 476 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 477 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, scifsoft, sc); 478 #endif 479 SET(sc->sc_hwflags, SCIF_HW_DEV_OK); 480 481 tp = ttymalloc(); 482 tp->t_oproc = scifstart; 483 tp->t_param = scifparam; 484 tp->t_hwiflow = NULL; 485 486 sc->sc_tty = tp; 487 sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 488 if (sc->sc_rbuf == NULL) { 489 printf("%s: unable to allocate ring buffer\n", 490 sc->sc_dev.dv_xname); 491 return; 492 } 493 sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1); 494 495 tty_attach(tp); 496 } 497 498 /* 499 * Start or restart transmission. 500 */ 501 static void 502 scifstart(struct tty *tp) 503 { 504 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 505 int s; 506 507 s = spltty(); 508 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 509 goto out; 510 if (sc->sc_tx_stopped) 511 goto out; 512 513 if (tp->t_outq.c_cc <= tp->t_lowat) { 514 if (ISSET(tp->t_state, TS_ASLEEP)) { 515 CLR(tp->t_state, TS_ASLEEP); 516 wakeup(&tp->t_outq); 517 } 518 selwakeup(&tp->t_wsel); 519 if (tp->t_outq.c_cc == 0) 520 goto out; 521 } 522 523 /* Grab the first contiguous region of buffer space. */ 524 { 525 u_char *tba; 526 int tbc; 527 528 tba = tp->t_outq.c_cf; 529 tbc = ndqb(&tp->t_outq, 0); 530 531 (void)splserial(); 532 533 sc->sc_tba = tba; 534 sc->sc_tbc = tbc; 535 } 536 537 SET(tp->t_state, TS_BUSY); 538 sc->sc_tx_busy = 1; 539 540 /* Enable transmit completion interrupts if necessary. */ 541 SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE; 542 543 /* Output the first chunk of the contiguous buffer. */ 544 { 545 int n; 546 int max; 547 int i; 548 549 n = sc->sc_tbc; 550 max = sc->sc_fifolen - ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8); 551 if (n > max) 552 n = max; 553 554 for (i = 0; i < n; i++) { 555 scif_putc(*(sc->sc_tba)); 556 sc->sc_tba++; 557 } 558 sc->sc_tbc -= n; 559 } 560 out: 561 splx(s); 562 return; 563 } 564 565 /* 566 * Set SCIF tty parameters from termios. 567 * XXX - Should just copy the whole termios after 568 * making sure all the changes could be done. 569 */ 570 static int 571 scifparam(struct tty *tp, struct termios *t) 572 { 573 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 574 int ospeed = t->c_ospeed; 575 int s; 576 577 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 578 return (EIO); 579 580 /* Check requested parameters. */ 581 if (ospeed < 0) 582 return (EINVAL); 583 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 584 return (EINVAL); 585 586 /* 587 * For the console, always force CLOCAL and !HUPCL, so that the port 588 * is always active. 589 */ 590 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 591 ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 592 SET(t->c_cflag, CLOCAL); 593 CLR(t->c_cflag, HUPCL); 594 } 595 596 /* 597 * If there were no changes, don't do anything. This avoids dropping 598 * input and improves performance when all we did was frob things like 599 * VMIN and VTIME. 600 */ 601 if (tp->t_ospeed == t->c_ospeed && 602 tp->t_cflag == t->c_cflag) 603 return (0); 604 605 #if 0 606 /* XXX (msaitoh) */ 607 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 608 #endif 609 610 s = splserial(); 611 612 /* 613 * Set the flow control pins depending on the current flow control 614 * mode. 615 */ 616 if (ISSET(t->c_cflag, CRTSCTS)) { 617 SHREG_SCFCR2 |= SCFCR2_MCE; 618 } else { 619 SHREG_SCFCR2 &= ~SCFCR2_MCE; 620 } 621 622 SHREG_SCBRR2 = divrnd(sh_clock_get_pclock(), 32 * ospeed) -1; 623 624 /* 625 * Set the FIFO threshold based on the receive speed. 626 * 627 * * If it's a low speed, it's probably a mouse or some other 628 * interactive device, so set the threshold low. 629 * * If it's a high speed, trim the trigger level down to prevent 630 * overflows. 631 * * Otherwise set it a bit higher. 632 */ 633 #if 0 634 /* XXX (msaitoh) */ 635 if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP)) 636 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 637 else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO)) 638 sc->sc_fifo = FIFO_ENABLE | 639 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : 640 t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4); 641 else 642 sc->sc_fifo = 0; 643 #endif 644 645 /* And copy to tty. */ 646 tp->t_ispeed = 0; 647 tp->t_ospeed = t->c_ospeed; 648 tp->t_cflag = t->c_cflag; 649 650 if (!sc->sc_heldchange) { 651 if (sc->sc_tx_busy) { 652 sc->sc_heldtbc = sc->sc_tbc; 653 sc->sc_tbc = 0; 654 sc->sc_heldchange = 1; 655 } 656 #if 0 657 /* XXX (msaitoh) */ 658 else 659 scif_loadchannelregs(sc); 660 #endif 661 } 662 663 if (!ISSET(t->c_cflag, CHWFLOW)) { 664 /* Disable the high water mark. */ 665 sc->sc_r_hiwat = 0; 666 sc->sc_r_lowat = 0; 667 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 668 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 669 scif_schedrx(sc); 670 } 671 } else { 672 sc->sc_r_hiwat = scif_rbuf_hiwat; 673 sc->sc_r_lowat = scif_rbuf_lowat; 674 } 675 676 splx(s); 677 678 #ifdef SCIF_DEBUG 679 if (scif_debug) 680 scifstatus(sc, "scifparam "); 681 #endif 682 683 if (!ISSET(t->c_cflag, CHWFLOW)) { 684 if (sc->sc_tx_stopped) { 685 sc->sc_tx_stopped = 0; 686 scifstart(tp); 687 } 688 } 689 690 return (0); 691 } 692 693 void 694 scif_iflush(struct scif_softc *sc) 695 { 696 int i; 697 unsigned char c; 698 699 i = SHREG_SCFDR2 & SCFDR2_RECVCNT; 700 701 while (i > 0) { 702 c = SHREG_SCFRDR2; 703 SHREG_SCSSR2 &= ~(SCSSR2_RDF | SCSSR2_DR); 704 i--; 705 } 706 } 707 708 int 709 scifopen(dev_t dev, int flag, int mode, struct proc *p) 710 { 711 int unit = SCIFUNIT(dev); 712 struct scif_softc *sc; 713 struct tty *tp; 714 int s, s2; 715 int error; 716 717 if (unit >= scif_cd.cd_ndevs) 718 return (ENXIO); 719 sc = scif_cd.cd_devs[unit]; 720 if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) || 721 sc->sc_rbuf == NULL) 722 return (ENXIO); 723 724 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 725 return (ENXIO); 726 727 #ifdef KGDB 728 /* 729 * If this is the kgdb port, no other use is permitted. 730 */ 731 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) 732 return (EBUSY); 733 #endif /* KGDB */ 734 735 tp = sc->sc_tty; 736 737 if (ISSET(tp->t_state, TS_ISOPEN) && 738 ISSET(tp->t_state, TS_XCLUDE) && 739 p->p_ucred->cr_uid != 0) 740 return (EBUSY); 741 742 s = spltty(); 743 744 /* 745 * Do the following iff this is a first open. 746 */ 747 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 748 struct termios t; 749 750 tp->t_dev = dev; 751 752 s2 = splserial(); 753 754 /* Turn on interrupts. */ 755 SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE; 756 757 splx(s2); 758 759 /* 760 * Initialize the termios status to the defaults. Add in the 761 * sticky bits from TIOCSFLAGS. 762 */ 763 t.c_ispeed = 0; 764 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 765 t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */ 766 t.c_cflag = scifconscflag; 767 } else { 768 t.c_ospeed = TTYDEF_SPEED; 769 t.c_cflag = TTYDEF_CFLAG; 770 } 771 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 772 SET(t.c_cflag, CLOCAL); 773 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 774 SET(t.c_cflag, CRTSCTS); 775 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 776 SET(t.c_cflag, MDMBUF); 777 /* Make sure scifparam() will do something. */ 778 tp->t_ospeed = 0; 779 (void) scifparam(tp, &t); 780 tp->t_iflag = TTYDEF_IFLAG; 781 tp->t_oflag = TTYDEF_OFLAG; 782 tp->t_lflag = TTYDEF_LFLAG; 783 ttychars(tp); 784 ttsetwater(tp); 785 786 s2 = splserial(); 787 788 /* Clear the input ring, and unblock. */ 789 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 790 sc->sc_rbavail = scif_rbuf_size; 791 scif_iflush(sc); 792 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 793 #if 0 794 /* XXX (msaitoh) */ 795 scif_hwiflow(sc); 796 #endif 797 798 #ifdef SCIF_DEBUG 799 if (scif_debug) 800 scifstatus(sc, "scifopen "); 801 #endif 802 803 splx(s2); 804 } 805 806 splx(s); 807 808 error = ttyopen(tp, SCIFDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 809 if (error) 810 goto bad; 811 812 error = (*tp->t_linesw->l_open)(dev, tp); 813 if (error) 814 goto bad; 815 816 return (0); 817 818 bad: 819 820 return (error); 821 } 822 823 int 824 scifclose(dev_t dev, int flag, int mode, struct proc *p) 825 { 826 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 827 struct tty *tp = sc->sc_tty; 828 829 /* XXX This is for cons.c. */ 830 if (!ISSET(tp->t_state, TS_ISOPEN)) 831 return (0); 832 833 (*tp->t_linesw->l_close)(tp, flag); 834 ttyclose(tp); 835 836 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 837 return (0); 838 839 return (0); 840 } 841 842 int 843 scifread(dev_t dev, struct uio *uio, int flag) 844 { 845 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 846 struct tty *tp = sc->sc_tty; 847 848 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 849 } 850 851 int 852 scifwrite(dev_t dev, struct uio *uio, int flag) 853 { 854 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 855 struct tty *tp = sc->sc_tty; 856 857 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 858 } 859 860 int 861 scifpoll(dev_t dev, int events, struct proc *p) 862 { 863 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 864 struct tty *tp = sc->sc_tty; 865 866 return ((*tp->t_linesw->l_poll)(tp, events, p)); 867 } 868 869 struct tty * 870 sciftty(dev_t dev) 871 { 872 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 873 struct tty *tp = sc->sc_tty; 874 875 return (tp); 876 } 877 878 int 879 scifioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 880 { 881 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 882 struct tty *tp = sc->sc_tty; 883 int error; 884 int s; 885 886 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 887 return (EIO); 888 889 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 890 if (error != EPASSTHROUGH) 891 return (error); 892 893 error = ttioctl(tp, cmd, data, flag, p); 894 if (error != EPASSTHROUGH) 895 return (error); 896 897 error = 0; 898 899 s = splserial(); 900 901 switch (cmd) { 902 case TIOCSBRK: 903 scif_break(sc, 1); 904 break; 905 906 case TIOCCBRK: 907 scif_break(sc, 0); 908 break; 909 910 case TIOCGFLAGS: 911 *(int *)data = sc->sc_swflags; 912 break; 913 914 case TIOCSFLAGS: 915 error = suser(p->p_ucred, &p->p_acflag); 916 if (error) 917 break; 918 sc->sc_swflags = *(int *)data; 919 break; 920 921 default: 922 error = EPASSTHROUGH; 923 break; 924 } 925 926 splx(s); 927 928 return (error); 929 } 930 931 integrate void 932 scif_schedrx(struct scif_softc *sc) 933 { 934 935 sc->sc_rx_ready = 1; 936 937 /* Wake up the poller. */ 938 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 939 softintr_schedule(sc->sc_si); 940 #else 941 #ifndef __NO_SOFT_SERIAL_INTERRUPT 942 setsoftserial(); 943 #else 944 if (!scif_softintr_scheduled) { 945 scif_softintr_scheduled = 1; 946 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 947 } 948 #endif 949 #endif 950 } 951 952 void 953 scif_break(struct scif_softc *sc, int onoff) 954 { 955 956 if (onoff) 957 SHREG_SCSSR2 &= ~SCSSR2_TDFE; 958 else 959 SHREG_SCSSR2 |= SCSSR2_TDFE; 960 961 #if 0 /* XXX */ 962 if (!sc->sc_heldchange) { 963 if (sc->sc_tx_busy) { 964 sc->sc_heldtbc = sc->sc_tbc; 965 sc->sc_tbc = 0; 966 sc->sc_heldchange = 1; 967 } else 968 scif_loadchannelregs(sc); 969 } 970 #endif 971 } 972 973 /* 974 * Stop output, e.g., for ^S or output flush. 975 */ 976 void 977 scifstop(struct tty *tp, int flag) 978 { 979 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 980 int s; 981 982 s = splserial(); 983 if (ISSET(tp->t_state, TS_BUSY)) { 984 /* Stop transmitting at the next chunk. */ 985 sc->sc_tbc = 0; 986 sc->sc_heldtbc = 0; 987 if (!ISSET(tp->t_state, TS_TTSTOP)) 988 SET(tp->t_state, TS_FLUSH); 989 } 990 splx(s); 991 } 992 993 void 994 scif_intr_init() 995 { 996 /* XXX */ 997 } 998 999 void 1000 scifdiag(void *arg) 1001 { 1002 struct scif_softc *sc = arg; 1003 int overflows, floods; 1004 int s; 1005 1006 s = splserial(); 1007 overflows = sc->sc_overflows; 1008 sc->sc_overflows = 0; 1009 floods = sc->sc_floods; 1010 sc->sc_floods = 0; 1011 sc->sc_errors = 0; 1012 splx(s); 1013 1014 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1015 sc->sc_dev.dv_xname, 1016 overflows, overflows == 1 ? "" : "s", 1017 floods, floods == 1 ? "" : "s"); 1018 } 1019 1020 integrate void 1021 scif_rxsoft(struct scif_softc *sc, struct tty *tp) 1022 { 1023 int (*rint)(int c, struct tty *tp) = tp->t_linesw->l_rint; 1024 u_char *get, *end; 1025 u_int cc, scc; 1026 u_char ssr2; 1027 int code; 1028 int s; 1029 1030 end = sc->sc_ebuf; 1031 get = sc->sc_rbget; 1032 scc = cc = scif_rbuf_size - sc->sc_rbavail; 1033 1034 if (cc == scif_rbuf_size) { 1035 sc->sc_floods++; 1036 if (sc->sc_errors++ == 0) 1037 callout_reset(&sc->sc_diag_ch, 60 * hz, scifdiag, sc); 1038 } 1039 1040 while (cc) { 1041 code = get[0]; 1042 ssr2 = get[1]; 1043 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) { 1044 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER)) 1045 SET(code, TTY_FE); 1046 if (ISSET(ssr2, SCSSR2_PER)) 1047 SET(code, TTY_PE); 1048 } 1049 if ((*rint)(code, tp) == -1) { 1050 /* 1051 * The line discipline's buffer is out of space. 1052 */ 1053 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1054 /* 1055 * We're either not using flow control, or the 1056 * line discipline didn't tell us to block for 1057 * some reason. Either way, we have no way to 1058 * know when there's more space available, so 1059 * just drop the rest of the data. 1060 */ 1061 get += cc << 1; 1062 if (get >= end) 1063 get -= scif_rbuf_size << 1; 1064 cc = 0; 1065 } else { 1066 /* 1067 * Don't schedule any more receive processing 1068 * until the line discipline tells us there's 1069 * space available (through scifhwiflow()). 1070 * Leave the rest of the data in the input 1071 * buffer. 1072 */ 1073 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1074 } 1075 break; 1076 } 1077 get += 2; 1078 if (get >= end) 1079 get = sc->sc_rbuf; 1080 cc--; 1081 } 1082 1083 if (cc != scc) { 1084 sc->sc_rbget = get; 1085 s = splserial(); 1086 cc = sc->sc_rbavail += scc - cc; 1087 /* Buffers should be ok again, release possible block. */ 1088 if (cc >= sc->sc_r_lowat) { 1089 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1090 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1091 SHREG_SCSCR2 |= SCSCR2_RIE; 1092 } 1093 #if 0 1094 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1095 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1096 scif_hwiflow(sc); 1097 } 1098 #endif 1099 } 1100 splx(s); 1101 } 1102 } 1103 1104 integrate void 1105 scif_txsoft(struct scif_softc *sc, struct tty *tp) 1106 { 1107 1108 CLR(tp->t_state, TS_BUSY); 1109 if (ISSET(tp->t_state, TS_FLUSH)) 1110 CLR(tp->t_state, TS_FLUSH); 1111 else 1112 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1113 (*tp->t_linesw->l_start)(tp); 1114 } 1115 1116 integrate void 1117 scif_stsoft(struct scif_softc *sc, struct tty *tp) 1118 { 1119 #if 0 1120 /* XXX (msaitoh) */ 1121 u_char msr, delta; 1122 int s; 1123 1124 s = splserial(); 1125 msr = sc->sc_msr; 1126 delta = sc->sc_msr_delta; 1127 sc->sc_msr_delta = 0; 1128 splx(s); 1129 1130 if (ISSET(delta, sc->sc_msr_dcd)) { 1131 /* 1132 * Inform the tty layer that carrier detect changed. 1133 */ 1134 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1135 } 1136 1137 if (ISSET(delta, sc->sc_msr_cts)) { 1138 /* Block or unblock output according to flow control. */ 1139 if (ISSET(msr, sc->sc_msr_cts)) { 1140 sc->sc_tx_stopped = 0; 1141 (*tp->t_linesw->l_start)(tp); 1142 } else { 1143 sc->sc_tx_stopped = 1; 1144 } 1145 } 1146 1147 #ifdef SCIF_DEBUG 1148 if (scif_debug) 1149 scifstatus(sc, "scif_stsoft"); 1150 #endif 1151 #endif 1152 } 1153 1154 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1155 void 1156 scifsoft(void *arg) 1157 { 1158 struct scif_softc *sc = arg; 1159 struct tty *tp; 1160 1161 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1162 return; 1163 1164 { 1165 #else 1166 void 1167 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1168 scifsoft() 1169 #else 1170 scifsoft(void *arg) 1171 #endif 1172 { 1173 struct scif_softc *sc; 1174 struct tty *tp; 1175 int unit; 1176 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1177 int s; 1178 1179 s = splsoftserial(); 1180 scif_softintr_scheduled = 0; 1181 #endif 1182 1183 for (unit = 0; unit < scif_cd.cd_ndevs; unit++) { 1184 sc = scif_cd.cd_devs[unit]; 1185 if (sc == NULL || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK)) 1186 continue; 1187 1188 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1189 continue; 1190 1191 tp = sc->sc_tty; 1192 if (tp == NULL) 1193 continue; 1194 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 1195 continue; 1196 #endif 1197 tp = sc->sc_tty; 1198 1199 if (sc->sc_rx_ready) { 1200 sc->sc_rx_ready = 0; 1201 scif_rxsoft(sc, tp); 1202 } 1203 1204 #if 0 1205 if (sc->sc_st_check) { 1206 sc->sc_st_check = 0; 1207 scif_stsoft(sc, tp); 1208 } 1209 #endif 1210 1211 if (sc->sc_tx_done) { 1212 sc->sc_tx_done = 0; 1213 scif_txsoft(sc, tp); 1214 } 1215 } 1216 1217 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1218 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1219 splx(s); 1220 #endif 1221 #endif 1222 } 1223 1224 int 1225 scifintr(void *arg) 1226 { 1227 struct scif_softc *sc = arg; 1228 u_char *put, *end; 1229 u_int cc; 1230 u_short ssr2; 1231 int count; 1232 1233 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1234 return (0); 1235 1236 end = sc->sc_ebuf; 1237 put = sc->sc_rbput; 1238 cc = sc->sc_rbavail; 1239 1240 do { 1241 ssr2 = SHREG_SCSSR2; 1242 if (ISSET(ssr2, SCSSR2_BRK)) { 1243 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR); 1244 #ifdef DDB 1245 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 1246 console_debugger(); 1247 } 1248 #endif /* DDB */ 1249 #ifdef KGDB 1250 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) { 1251 kgdb_connect(1); 1252 } 1253 #endif /* KGDB */ 1254 } 1255 count = SHREG_SCFDR2 & SCFDR2_RECVCNT; 1256 if (count != 0) { 1257 while (1) { 1258 u_char c = SHREG_SCFRDR2; 1259 u_char err = (u_char)(SHREG_SCSSR2 & 0x00ff); 1260 1261 SHREG_SCSSR2 &= ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR); 1262 #ifdef SH4 1263 if (CPU_IS_SH4) 1264 SHREG_SCLSR2 &= ~SCLSR2_ORER; 1265 #endif 1266 if ((cc > 0) && (count > 0)) { 1267 put[0] = c; 1268 put[1] = err; 1269 put += 2; 1270 if (put >= end) 1271 put = sc->sc_rbuf; 1272 cc--; 1273 count--; 1274 } else 1275 break; 1276 } 1277 1278 /* 1279 * Current string of incoming characters ended because 1280 * no more data was available or we ran out of space. 1281 * Schedule a receive event if any data was received. 1282 * If we're out of space, turn off receive interrupts. 1283 */ 1284 sc->sc_rbput = put; 1285 sc->sc_rbavail = cc; 1286 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1287 sc->sc_rx_ready = 1; 1288 1289 /* 1290 * See if we are in danger of overflowing a buffer. If 1291 * so, use hardware flow control to ease the pressure. 1292 */ 1293 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1294 cc < sc->sc_r_hiwat) { 1295 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1296 #if 0 1297 scif_hwiflow(sc); 1298 #endif 1299 } 1300 1301 /* 1302 * If we're out of space, disable receive interrupts 1303 * until the queue has drained a bit. 1304 */ 1305 if (!cc) { 1306 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1307 SHREG_SCSCR2 &= ~SCSCR2_RIE; 1308 } 1309 } else { 1310 if (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR)) { 1311 SHREG_SCSCR2 &= ~(SCSCR2_TIE | SCSCR2_RIE); 1312 delay(10); 1313 SHREG_SCSCR2 |= SCSCR2_TIE | SCSCR2_RIE; 1314 continue; 1315 } 1316 } 1317 } while (SHREG_SCSSR2 & (SCSSR2_RDF | SCSSR2_DR)); 1318 1319 #if 0 1320 msr = bus_space_read_1(iot, ioh, scif_msr); 1321 delta = msr ^ sc->sc_msr; 1322 sc->sc_msr = msr; 1323 if (ISSET(delta, sc->sc_msr_mask)) { 1324 SET(sc->sc_msr_delta, delta); 1325 1326 /* 1327 * Pulse-per-second clock signal on edge of DCD? 1328 */ 1329 if (ISSET(delta, sc->sc_ppsmask)) { 1330 struct timeval tv; 1331 if (ISSET(msr, sc->sc_ppsmask) == 1332 sc->sc_ppsassert) { 1333 /* XXX nanotime() */ 1334 microtime(&tv); 1335 TIMEVAL_TO_TIMESPEC(&tv, 1336 &sc->ppsinfo.assert_timestamp); 1337 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 1338 timespecadd(&sc->ppsinfo.assert_timestamp, 1339 &sc->ppsparam.assert_offset, 1340 &sc->ppsinfo.assert_timestamp); 1341 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp); 1342 } 1343 1344 #ifdef PPS_SYNC 1345 if (sc->ppsparam.mode & PPS_HARDPPSONASSERT) 1346 hardpps(&tv, tv.tv_usec); 1347 #endif 1348 sc->ppsinfo.assert_sequence++; 1349 sc->ppsinfo.current_mode = 1350 sc->ppsparam.mode; 1351 1352 } else if (ISSET(msr, sc->sc_ppsmask) == 1353 sc->sc_ppsclear) { 1354 /* XXX nanotime() */ 1355 microtime(&tv); 1356 TIMEVAL_TO_TIMESPEC(&tv, 1357 &sc->ppsinfo.clear_timestamp); 1358 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 1359 timespecadd(&sc->ppsinfo.clear_timestamp, 1360 &sc->ppsparam.clear_offset, 1361 &sc->ppsinfo.clear_timestamp); 1362 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp); 1363 } 1364 1365 #ifdef PPS_SYNC 1366 if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR) 1367 hardpps(&tv, tv.tv_usec); 1368 #endif 1369 sc->ppsinfo.clear_sequence++; 1370 sc->ppsinfo.current_mode = 1371 sc->ppsparam.mode; 1372 } 1373 } 1374 1375 /* 1376 * Stop output immediately if we lose the output 1377 * flow control signal or carrier detect. 1378 */ 1379 if (ISSET(~msr, sc->sc_msr_mask)) { 1380 sc->sc_tbc = 0; 1381 sc->sc_heldtbc = 0; 1382 #ifdef SCIF_DEBUG 1383 if (scif_debug) 1384 scifstatus(sc, "scifintr "); 1385 #endif 1386 } 1387 1388 sc->sc_st_check = 1; 1389 } 1390 #endif 1391 1392 /* 1393 * Done handling any receive interrupts. See if data can be 1394 * transmitted as well. Schedule tx done event if no data left 1395 * and tty was marked busy. 1396 */ 1397 if (((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */ 1398 /* 1399 * If we've delayed a parameter change, do it now, and restart 1400 * output. 1401 */ 1402 if (sc->sc_heldchange) { 1403 sc->sc_heldchange = 0; 1404 sc->sc_tbc = sc->sc_heldtbc; 1405 sc->sc_heldtbc = 0; 1406 } 1407 1408 /* Output the next chunk of the contiguous buffer, if any. */ 1409 if (sc->sc_tbc > 0) { 1410 int n; 1411 int max; 1412 int i; 1413 1414 n = sc->sc_tbc; 1415 max = sc->sc_fifolen - 1416 ((SHREG_SCFDR2 & SCFDR2_TXCNT) >> 8); 1417 if (n > max) 1418 n = max; 1419 1420 for (i = 0; i < n; i++) { 1421 scif_putc(*(sc->sc_tba)); 1422 sc->sc_tba++; 1423 } 1424 sc->sc_tbc -= n; 1425 } else { 1426 /* Disable transmit completion interrupts if necessary. */ 1427 #if 0 1428 if (ISSET(sc->sc_ier, IER_ETXRDY)) 1429 #endif 1430 SHREG_SCSCR2 &= ~SCSCR2_TIE; 1431 1432 if (sc->sc_tx_busy) { 1433 sc->sc_tx_busy = 0; 1434 sc->sc_tx_done = 1; 1435 } 1436 } 1437 } 1438 1439 /* Wake up the poller. */ 1440 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1441 softintr_schedule(sc->sc_si); 1442 #else 1443 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1444 setsoftserial(); 1445 #else 1446 if (!scif_softintr_scheduled) { 1447 scif_softintr_scheduled = 1; 1448 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 1449 } 1450 #endif 1451 #endif 1452 1453 #if NRND > 0 && defined(RND_SCIF) 1454 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1455 #endif 1456 1457 return (1); 1458 } 1459 1460 void 1461 scifcnprobe(struct consdev *cp) 1462 { 1463 int maj; 1464 1465 /* locate the major number */ 1466 maj = cdevsw_lookup_major(&scif_cdevsw); 1467 1468 /* Initialize required fields. */ 1469 cp->cn_dev = makedev(maj, 0); 1470 #ifdef SCIFCONSOLE 1471 cp->cn_pri = CN_REMOTE; 1472 #else 1473 cp->cn_pri = CN_NORMAL; 1474 #endif 1475 } 1476 1477 void 1478 scifcninit(struct consdev *cp) 1479 { 1480 1481 InitializeScif(scifcn_speed); 1482 scifisconsole = 1; 1483 } 1484 1485 int 1486 scifcngetc(dev_t dev) 1487 { 1488 int c; 1489 int s; 1490 1491 s = splserial(); 1492 c = scif_getc(); 1493 splx(s); 1494 1495 return (c); 1496 } 1497 1498 void 1499 scifcnputc(dev_t dev, int c) 1500 { 1501 int s; 1502 1503 s = splserial(); 1504 scif_putc((u_char)c); 1505 splx(s); 1506 } 1507 1508 #ifdef KGDB 1509 int 1510 scif_kgdb_init() 1511 { 1512 1513 if (strcmp(kgdb_devname, "scif") != 0) 1514 return (1); 1515 1516 if (scifisconsole) 1517 return (1); /* can't share with console */ 1518 1519 InitializeScif(kgdb_rate); 1520 1521 kgdb_attach((int (*)(void *))scifcngetc, 1522 (void (*)(void *, int))scifcnputc, NULL); 1523 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 1524 kgdb_attached = 1; 1525 1526 return (0); 1527 } 1528 #endif /* KGDB */ 1529
Indexes created Tue Sep 23 07:09:52 GMT 2025