scif.c revision 1.37
1 /* $NetBSD: scif.c,v 1.37 2004/10/19 02:12:21 uwe Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Charles M. Hannum. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the NetBSD 47 * Foundation, Inc. and its contributors. 48 * 4. Neither the name of The NetBSD Foundation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 53 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 54 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * Copyright (c) 1991 The Regents of the University of California. 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. Neither the name of the University nor the names of its contributors 78 * may be used to endorse or promote products derived from this software 79 * without specific prior written permission. 80 * 81 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 82 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 83 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 84 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 85 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 86 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 87 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 88 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 89 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 90 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 91 * SUCH DAMAGE. 92 * 93 * @(#)com.c 7.5 (Berkeley) 5/16/91 94 */ 95 96 /* 97 * SH internal serial driver 98 * 99 * This code is derived from both z8530tty.c and com.c 100 */ 101 102 #include <sys/cdefs.h> 103 __KERNEL_RCSID(0, "$NetBSD: scif.c,v 1.37 2004/10/19 02:12:21 uwe Exp $"); 104 105 #include "opt_kgdb.h" 106 #include "opt_scif.h" 107 108 #include <sys/param.h> 109 #include <sys/systm.h> 110 #include <sys/tty.h> 111 #include <sys/proc.h> 112 #include <sys/conf.h> 113 #include <sys/file.h> 114 #include <sys/syslog.h> 115 #include <sys/kernel.h> 116 #include <sys/device.h> 117 #include <sys/malloc.h> 118 #include <sys/kgdb.h> 119 120 #include <dev/cons.h> 121 122 #include <sh3/clock.h> 123 #include <sh3/exception.h> 124 #include <sh3/scifreg.h> 125 #include <machine/intr.h> 126 127 #include <sh3/dev/scifvar.h> 128 129 #include "locators.h" 130 131 static void scifstart(struct tty *); 132 static int scifparam(struct tty *, struct termios *); 133 static int kgdb_attached; 134 135 void scifcnprobe(struct consdev *); 136 void scifcninit(struct consdev *); 137 void scifcnputc(dev_t, int); 138 int scifcngetc(dev_t); 139 void scifcnpoolc(dev_t, int); 140 void scif_intr_init(void); 141 int scifintr(void *); 142 143 struct scif_softc { 144 struct device sc_dev; /* boilerplate */ 145 struct tty *sc_tty; 146 void *sc_si; 147 148 struct callout sc_diag_ch; 149 150 #if 0 151 bus_space_tag_t sc_iot; /* ISA i/o space identifier */ 152 bus_space_handle_t sc_ioh; /* ISA io handle */ 153 154 int sc_drq; 155 156 int sc_frequency; 157 #endif 158 159 u_int sc_overflows, 160 sc_floods, 161 sc_errors; /* number of retries so far */ 162 u_char sc_status[7]; /* copy of registers */ 163 164 int sc_hwflags; 165 int sc_swflags; 166 u_int sc_fifolen; 167 168 u_int sc_r_hiwat, 169 sc_r_lowat; 170 u_char *volatile sc_rbget, 171 *volatile sc_rbput; 172 volatile u_int sc_rbavail; 173 u_char *sc_rbuf, 174 *sc_ebuf; 175 176 u_char *sc_tba; /* transmit buffer address */ 177 u_int sc_tbc, /* transmit byte count */ 178 sc_heldtbc; 179 180 volatile u_char sc_rx_flags, 181 #define RX_TTY_BLOCKED 0x01 182 #define RX_TTY_OVERFLOWED 0x02 183 #define RX_IBUF_BLOCKED 0x04 184 #define RX_IBUF_OVERFLOWED 0x08 185 #define RX_ANY_BLOCK 0x0f 186 sc_tx_busy, /* working on an output chunk */ 187 sc_tx_done, /* done with one output chunk */ 188 sc_tx_stopped, /* H/W level stop (lost CTS) */ 189 sc_st_check, /* got a status interrupt */ 190 sc_rx_ready; 191 192 volatile u_char sc_heldchange; 193 }; 194 195 /* controller driver configuration */ 196 static int scif_match(struct device *, struct cfdata *, void *); 197 static void scif_attach(struct device *, struct device *, void *); 198 199 void scif_break(struct scif_softc *, int); 200 void scif_iflush(struct scif_softc *); 201 202 #define integrate static inline 203 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 204 void scifsoft(void *); 205 #else 206 #ifndef __NO_SOFT_SERIAL_INTERRUPT 207 void scifsoft(void); 208 #else 209 void scifsoft(void *); 210 #endif 211 #endif 212 integrate void scif_rxsoft(struct scif_softc *, struct tty *); 213 integrate void scif_txsoft(struct scif_softc *, struct tty *); 214 integrate void scif_stsoft(struct scif_softc *, struct tty *); 215 integrate void scif_schedrx(struct scif_softc *); 216 void scifdiag(void *); 217 218 219 #define SCIFUNIT_MASK 0x7ffff 220 #define SCIFDIALOUT_MASK 0x80000 221 222 #define SCIFUNIT(x) (minor(x) & SCIFUNIT_MASK) 223 #define SCIFDIALOUT(x) (minor(x) & SCIFDIALOUT_MASK) 224 225 /* Macros to clear/set/test flags. */ 226 #define SET(t, f) (t) |= (f) 227 #define CLR(t, f) (t) &= ~(f) 228 #define ISSET(t, f) ((t) & (f)) 229 230 /* Hardware flag masks */ 231 #define SCIF_HW_NOIEN 0x01 232 #define SCIF_HW_FIFO 0x02 233 #define SCIF_HW_FLOW 0x08 234 #define SCIF_HW_DEV_OK 0x20 235 #define SCIF_HW_CONSOLE 0x40 236 #define SCIF_HW_KGDB 0x80 237 238 /* Buffer size for character buffer */ 239 #define SCIF_RING_SIZE 2048 240 241 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 242 u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4; 243 u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4; 244 245 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 246 int scifconscflag = CONMODE; 247 int scifisconsole = 0; 248 249 #ifdef SCIFCN_SPEED 250 unsigned int scifcn_speed = SCIFCN_SPEED; 251 #else 252 unsigned int scifcn_speed = 9600; 253 #endif 254 255 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 256 257 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 258 #ifdef __NO_SOFT_SERIAL_INTERRUPT 259 volatile int scif_softintr_scheduled; 260 struct callout scif_soft_ch = CALLOUT_INITIALIZER; 261 #endif 262 #endif 263 264 u_int scif_rbuf_size = SCIF_RING_SIZE; 265 266 CFATTACH_DECL(scif, sizeof(struct scif_softc), 267 scif_match, scif_attach, NULL, NULL); 268 269 extern struct cfdriver scif_cd; 270 271 dev_type_open(scifopen); 272 dev_type_close(scifclose); 273 dev_type_read(scifread); 274 dev_type_write(scifwrite); 275 dev_type_ioctl(scifioctl); 276 dev_type_stop(scifstop); 277 dev_type_tty(sciftty); 278 dev_type_poll(scifpoll); 279 280 const struct cdevsw scif_cdevsw = { 281 scifopen, scifclose, scifread, scifwrite, scifioctl, 282 scifstop, sciftty, scifpoll, nommap, ttykqfilter, D_TTY 283 }; 284 285 void InitializeScif (unsigned int); 286 287 /* 288 * following functions are debugging prupose only 289 */ 290 #define CR 0x0D 291 #define USART_ON (unsigned int)~0x08 292 293 void scif_putc(unsigned char); 294 unsigned char scif_getc(void); 295 int ScifErrCheck(void); 296 297 298 /* XXX: uwe 299 * Prepare for bus_spacification. The difference in access widths is 300 * still handled by the magic definitions in scifreg.h 301 */ 302 #define scif_smr_read() SHREG_SCSMR2 303 #define scif_smr_write(v) (SHREG_SCSMR2 = (v)) 304 305 #define scif_brr_read() SHREG_SCBRR2 306 #define scif_brr_write(v) (SHREG_SCBRR2 = (v)) 307 308 #define scif_scr_read() SHREG_SCSCR2 309 #define scif_scr_write(v) (SHREG_SCSCR2 = (v)) 310 311 #define scif_ftdr_write(v) (SHREG_SCFTDR2 = (v)) 312 313 #define scif_ssr_read() SHREG_SCSSR2 314 #define scif_ssr_write(v) (SHREG_SCSSR2 = (v)) 315 316 #define scif_frdr_read() SHREG_SCFRDR2 317 318 #define scif_fcr_read() SHREG_SCFCR2 319 #define scif_fcr_write(v) (SHREG_SCFCR2 = (v)) 320 321 #define scif_fdr_read() SHREG_SCFDR2 322 323 #ifdef SH4 /* additional registers in sh4 */ 324 325 #define scif_sptr_read() SHREG_SCSPTR2 326 #define scif_sptr_write(v) (SHREG_SCSPTR2 = (v)) 327 328 #define scif_lsr_read() SHREG_SCLSR2 329 #define scif_lsr_write(v) (SHREG_SCLSR2 = (v)) 330 331 #endif /* SH4 */ 332 333 334 /* 335 * InitializeScif 336 * : unsigned int bps; 337 * : SCIF(Serial Communication Interface) 338 */ 339 340 void 341 InitializeScif(unsigned int bps) 342 { 343 344 /* Initialize SCR */ 345 scif_scr_write(0x00); 346 347 #if 0 348 scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE); 349 #else 350 scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST); 351 #endif 352 /* Serial Mode Register */ 353 scif_smr_write(0x00); /* 8bit,NonParity,Even,1Stop */ 354 355 /* Bit Rate Register */ 356 scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * bps) - 1); 357 358 /* 359 * wait 1mSec, because Send/Recv must begin 1 bit period after 360 * BRR is set. 361 */ 362 delay(1000); 363 364 #if 0 365 scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE); 366 #else 367 scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1); 368 #endif 369 370 /* Send permission, Receive permission ON */ 371 scif_scr_write(SCSCR2_TE | SCSCR2_RE); 372 373 /* Serial Status Register */ 374 scif_ssr_write(scif_ssr_read() & SCSSR2_TDFE); /* Clear Status */ 375 } 376 377 378 /* 379 * scif_putc 380 * : unsigned char c; 381 */ 382 383 void 384 scif_putc(unsigned char c) 385 { 386 387 /* wait for ready */ 388 while ((scif_fdr_read() & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) 389 continue; 390 391 /* write send data to send register */ 392 scif_ftdr_write(c); 393 394 /* clear ready flag */ 395 scif_ssr_write(scif_ssr_read() & ~(SCSSR2_TDFE | SCSSR2_TEND)); 396 } 397 398 /* 399 * : ScifErrCheck 400 * 0x80 = error 401 * 0x08 = frame error 402 * 0x04 = parity error 403 */ 404 int 405 ScifErrCheck(void) 406 { 407 408 return (scif_ssr_read() & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)); 409 } 410 411 /* 412 * scif_getc 413 */ 414 unsigned char 415 scif_getc(void) 416 { 417 unsigned char c, err_c; 418 #ifdef SH4 419 unsigned short err_c2; 420 #endif 421 422 for (;;) { 423 /* wait for ready */ 424 while ((scif_fdr_read() & SCFDR2_RECVCNT) == 0) 425 continue; 426 427 c = scif_frdr_read(); 428 err_c = scif_ssr_read(); 429 scif_ssr_write(scif_ssr_read() 430 & ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF | SCSSR2_DR)); 431 #ifdef SH4 432 if (CPU_IS_SH4) { 433 err_c2 = scif_lsr_read(); 434 scif_lsr_write(scif_lsr_read() & ~SCLSR2_ORER); 435 } 436 #endif 437 if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER 438 | SCSSR2_PER)) == 0) { 439 #ifdef SH4 440 if (CPU_IS_SH4 && ((err_c2 & SCLSR2_ORER) == 0)) 441 #endif 442 return(c); 443 } 444 } 445 446 } 447 448 #if 0 449 #define SCIF_MAX_UNITS 2 450 #else 451 #define SCIF_MAX_UNITS 1 452 #endif 453 454 455 static int 456 scif_match(struct device *parent, struct cfdata *cfp, void *aux) 457 { 458 459 if (strcmp(cfp->cf_name, "scif") 460 || cfp->cf_unit >= SCIF_MAX_UNITS) 461 return 0; 462 463 return 1; 464 } 465 466 static void 467 scif_attach(struct device *parent, struct device *self, void *aux) 468 { 469 struct scif_softc *sc = (struct scif_softc *)self; 470 struct tty *tp; 471 472 sc->sc_hwflags = 0; /* XXX */ 473 sc->sc_swflags = 0; /* XXX */ 474 sc->sc_fifolen = 16; 475 476 if (scifisconsole || kgdb_attached) { 477 /* InitializeScif(scifcn_speed); */ 478 SET(sc->sc_hwflags, SCIF_HW_CONSOLE); 479 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 480 if (kgdb_attached) { 481 SET(sc->sc_hwflags, SCIF_HW_KGDB); 482 printf("\n%s: kgdb\n", sc->sc_dev.dv_xname); 483 } else { 484 printf("\n%s: console\n", sc->sc_dev.dv_xname); 485 } 486 } else { 487 InitializeScif(9600); 488 printf("\n"); 489 } 490 491 callout_init(&sc->sc_diag_ch); 492 #ifdef SH4 493 intc_intr_establish(SH4_INTEVT_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 494 scifintr, sc); 495 intc_intr_establish(SH4_INTEVT_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 496 scifintr, sc); 497 intc_intr_establish(SH4_INTEVT_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 498 scifintr, sc); 499 intc_intr_establish(SH4_INTEVT_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 500 scifintr, sc); 501 #else 502 intc_intr_establish(SH7709_INTEVT2_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 503 scifintr, sc); 504 intc_intr_establish(SH7709_INTEVT2_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 505 scifintr, sc); 506 intc_intr_establish(SH7709_INTEVT2_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 507 scifintr, sc); 508 intc_intr_establish(SH7709_INTEVT2_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 509 scifintr, sc); 510 #endif 511 512 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 513 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, scifsoft, sc); 514 #endif 515 SET(sc->sc_hwflags, SCIF_HW_DEV_OK); 516 517 tp = ttymalloc(); 518 tp->t_oproc = scifstart; 519 tp->t_param = scifparam; 520 tp->t_hwiflow = NULL; 521 522 sc->sc_tty = tp; 523 sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 524 if (sc->sc_rbuf == NULL) { 525 printf("%s: unable to allocate ring buffer\n", 526 sc->sc_dev.dv_xname); 527 return; 528 } 529 sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1); 530 531 tty_attach(tp); 532 } 533 534 /* 535 * Start or restart transmission. 536 */ 537 static void 538 scifstart(struct tty *tp) 539 { 540 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 541 int s; 542 543 s = spltty(); 544 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 545 goto out; 546 if (sc->sc_tx_stopped) 547 goto out; 548 549 if (tp->t_outq.c_cc <= tp->t_lowat) { 550 if (ISSET(tp->t_state, TS_ASLEEP)) { 551 CLR(tp->t_state, TS_ASLEEP); 552 wakeup(&tp->t_outq); 553 } 554 selwakeup(&tp->t_wsel); 555 if (tp->t_outq.c_cc == 0) 556 goto out; 557 } 558 559 /* Grab the first contiguous region of buffer space. */ 560 { 561 u_char *tba; 562 int tbc; 563 564 tba = tp->t_outq.c_cf; 565 tbc = ndqb(&tp->t_outq, 0); 566 567 (void)splserial(); 568 569 sc->sc_tba = tba; 570 sc->sc_tbc = tbc; 571 } 572 573 SET(tp->t_state, TS_BUSY); 574 sc->sc_tx_busy = 1; 575 576 /* Enable transmit completion interrupts if necessary. */ 577 scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE); 578 579 /* Output the first chunk of the contiguous buffer. */ 580 { 581 int n; 582 int max; 583 int i; 584 585 n = sc->sc_tbc; 586 max = sc->sc_fifolen - ((scif_fdr_read() & SCFDR2_TXCNT) >> 8); 587 if (n > max) 588 n = max; 589 590 for (i = 0; i < n; i++) { 591 scif_putc(*(sc->sc_tba)); 592 sc->sc_tba++; 593 } 594 sc->sc_tbc -= n; 595 } 596 out: 597 splx(s); 598 return; 599 } 600 601 /* 602 * Set SCIF tty parameters from termios. 603 * XXX - Should just copy the whole termios after 604 * making sure all the changes could be done. 605 */ 606 static int 607 scifparam(struct tty *tp, struct termios *t) 608 { 609 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 610 int ospeed = t->c_ospeed; 611 int s; 612 613 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 614 return (EIO); 615 616 /* Check requested parameters. */ 617 if (ospeed < 0) 618 return (EINVAL); 619 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 620 return (EINVAL); 621 622 /* 623 * For the console, always force CLOCAL and !HUPCL, so that the port 624 * is always active. 625 */ 626 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 627 ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 628 SET(t->c_cflag, CLOCAL); 629 CLR(t->c_cflag, HUPCL); 630 } 631 632 /* 633 * If there were no changes, don't do anything. This avoids dropping 634 * input and improves performance when all we did was frob things like 635 * VMIN and VTIME. 636 */ 637 if (tp->t_ospeed == t->c_ospeed && 638 tp->t_cflag == t->c_cflag) 639 return (0); 640 641 #if 0 642 /* XXX (msaitoh) */ 643 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 644 #endif 645 646 s = splserial(); 647 648 /* 649 * Set the flow control pins depending on the current flow control 650 * mode. 651 */ 652 if (ISSET(t->c_cflag, CRTSCTS)) { 653 scif_fcr_write(scif_fcr_read() | SCFCR2_MCE); 654 } else { 655 scif_fcr_write(scif_fcr_read() & ~SCFCR2_MCE); 656 } 657 658 scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * ospeed) -1); 659 660 /* 661 * Set the FIFO threshold based on the receive speed. 662 * 663 * * If it's a low speed, it's probably a mouse or some other 664 * interactive device, so set the threshold low. 665 * * If it's a high speed, trim the trigger level down to prevent 666 * overflows. 667 * * Otherwise set it a bit higher. 668 */ 669 #if 0 670 /* XXX (msaitoh) */ 671 if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP)) 672 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 673 else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO)) 674 sc->sc_fifo = FIFO_ENABLE | 675 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : 676 t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4); 677 else 678 sc->sc_fifo = 0; 679 #endif 680 681 /* And copy to tty. */ 682 tp->t_ispeed = 0; 683 tp->t_ospeed = t->c_ospeed; 684 tp->t_cflag = t->c_cflag; 685 686 if (!sc->sc_heldchange) { 687 if (sc->sc_tx_busy) { 688 sc->sc_heldtbc = sc->sc_tbc; 689 sc->sc_tbc = 0; 690 sc->sc_heldchange = 1; 691 } 692 #if 0 693 /* XXX (msaitoh) */ 694 else 695 scif_loadchannelregs(sc); 696 #endif 697 } 698 699 if (!ISSET(t->c_cflag, CHWFLOW)) { 700 /* Disable the high water mark. */ 701 sc->sc_r_hiwat = 0; 702 sc->sc_r_lowat = 0; 703 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 704 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 705 scif_schedrx(sc); 706 } 707 } else { 708 sc->sc_r_hiwat = scif_rbuf_hiwat; 709 sc->sc_r_lowat = scif_rbuf_lowat; 710 } 711 712 splx(s); 713 714 #ifdef SCIF_DEBUG 715 if (scif_debug) 716 scifstatus(sc, "scifparam "); 717 #endif 718 719 if (!ISSET(t->c_cflag, CHWFLOW)) { 720 if (sc->sc_tx_stopped) { 721 sc->sc_tx_stopped = 0; 722 scifstart(tp); 723 } 724 } 725 726 return (0); 727 } 728 729 void 730 scif_iflush(struct scif_softc *sc) 731 { 732 int i; 733 unsigned char c; 734 735 i = scif_fdr_read() & SCFDR2_RECVCNT; 736 737 while (i > 0) { 738 c = scif_frdr_read(); 739 scif_ssr_write(scif_ssr_read() & ~(SCSSR2_RDF | SCSSR2_DR)); 740 i--; 741 } 742 } 743 744 int 745 scifopen(dev_t dev, int flag, int mode, struct proc *p) 746 { 747 int unit = SCIFUNIT(dev); 748 struct scif_softc *sc; 749 struct tty *tp; 750 int s, s2; 751 int error; 752 753 if (unit >= scif_cd.cd_ndevs) 754 return (ENXIO); 755 sc = scif_cd.cd_devs[unit]; 756 if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) || 757 sc->sc_rbuf == NULL) 758 return (ENXIO); 759 760 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 761 return (ENXIO); 762 763 #ifdef KGDB 764 /* 765 * If this is the kgdb port, no other use is permitted. 766 */ 767 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) 768 return (EBUSY); 769 #endif /* KGDB */ 770 771 tp = sc->sc_tty; 772 773 if (ISSET(tp->t_state, TS_ISOPEN) && 774 ISSET(tp->t_state, TS_XCLUDE) && 775 p->p_ucred->cr_uid != 0) 776 return (EBUSY); 777 778 s = spltty(); 779 780 /* 781 * Do the following iff this is a first open. 782 */ 783 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 784 struct termios t; 785 786 tp->t_dev = dev; 787 788 s2 = splserial(); 789 790 /* Turn on interrupts. */ 791 scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE); 792 793 splx(s2); 794 795 /* 796 * Initialize the termios status to the defaults. Add in the 797 * sticky bits from TIOCSFLAGS. 798 */ 799 t.c_ispeed = 0; 800 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 801 t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */ 802 t.c_cflag = scifconscflag; 803 } else { 804 t.c_ospeed = TTYDEF_SPEED; 805 t.c_cflag = TTYDEF_CFLAG; 806 } 807 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 808 SET(t.c_cflag, CLOCAL); 809 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 810 SET(t.c_cflag, CRTSCTS); 811 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 812 SET(t.c_cflag, MDMBUF); 813 /* Make sure scifparam() will do something. */ 814 tp->t_ospeed = 0; 815 (void) scifparam(tp, &t); 816 tp->t_iflag = TTYDEF_IFLAG; 817 tp->t_oflag = TTYDEF_OFLAG; 818 tp->t_lflag = TTYDEF_LFLAG; 819 ttychars(tp); 820 ttsetwater(tp); 821 822 s2 = splserial(); 823 824 /* Clear the input ring, and unblock. */ 825 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 826 sc->sc_rbavail = scif_rbuf_size; 827 scif_iflush(sc); 828 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 829 #if 0 830 /* XXX (msaitoh) */ 831 scif_hwiflow(sc); 832 #endif 833 834 #ifdef SCIF_DEBUG 835 if (scif_debug) 836 scifstatus(sc, "scifopen "); 837 #endif 838 839 splx(s2); 840 } 841 842 splx(s); 843 844 error = ttyopen(tp, SCIFDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 845 if (error) 846 goto bad; 847 848 error = (*tp->t_linesw->l_open)(dev, tp); 849 if (error) 850 goto bad; 851 852 return (0); 853 854 bad: 855 856 return (error); 857 } 858 859 int 860 scifclose(dev_t dev, int flag, int mode, struct proc *p) 861 { 862 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 863 struct tty *tp = sc->sc_tty; 864 865 /* XXX This is for cons.c. */ 866 if (!ISSET(tp->t_state, TS_ISOPEN)) 867 return (0); 868 869 (*tp->t_linesw->l_close)(tp, flag); 870 ttyclose(tp); 871 872 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 873 return (0); 874 875 return (0); 876 } 877 878 int 879 scifread(dev_t dev, struct uio *uio, int flag) 880 { 881 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 882 struct tty *tp = sc->sc_tty; 883 884 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 885 } 886 887 int 888 scifwrite(dev_t dev, struct uio *uio, int flag) 889 { 890 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 891 struct tty *tp = sc->sc_tty; 892 893 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 894 } 895 896 int 897 scifpoll(dev_t dev, int events, struct proc *p) 898 { 899 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 900 struct tty *tp = sc->sc_tty; 901 902 return ((*tp->t_linesw->l_poll)(tp, events, p)); 903 } 904 905 struct tty * 906 sciftty(dev_t dev) 907 { 908 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 909 struct tty *tp = sc->sc_tty; 910 911 return (tp); 912 } 913 914 int 915 scifioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 916 { 917 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 918 struct tty *tp = sc->sc_tty; 919 int error; 920 int s; 921 922 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 923 return (EIO); 924 925 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 926 if (error != EPASSTHROUGH) 927 return (error); 928 929 error = ttioctl(tp, cmd, data, flag, p); 930 if (error != EPASSTHROUGH) 931 return (error); 932 933 error = 0; 934 935 s = splserial(); 936 937 switch (cmd) { 938 case TIOCSBRK: 939 scif_break(sc, 1); 940 break; 941 942 case TIOCCBRK: 943 scif_break(sc, 0); 944 break; 945 946 case TIOCGFLAGS: 947 *(int *)data = sc->sc_swflags; 948 break; 949 950 case TIOCSFLAGS: 951 error = suser(p->p_ucred, &p->p_acflag); 952 if (error) 953 break; 954 sc->sc_swflags = *(int *)data; 955 break; 956 957 default: 958 error = EPASSTHROUGH; 959 break; 960 } 961 962 splx(s); 963 964 return (error); 965 } 966 967 integrate void 968 scif_schedrx(struct scif_softc *sc) 969 { 970 971 sc->sc_rx_ready = 1; 972 973 /* Wake up the poller. */ 974 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 975 softintr_schedule(sc->sc_si); 976 #else 977 #ifndef __NO_SOFT_SERIAL_INTERRUPT 978 setsoftserial(); 979 #else 980 if (!scif_softintr_scheduled) { 981 scif_softintr_scheduled = 1; 982 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 983 } 984 #endif 985 #endif 986 } 987 988 void 989 scif_break(struct scif_softc *sc, int onoff) 990 { 991 992 if (onoff) 993 scif_ssr_write(scif_ssr_read() & ~SCSSR2_TDFE); 994 else 995 scif_ssr_write(scif_ssr_read() | SCSSR2_TDFE); 996 997 #if 0 /* XXX */ 998 if (!sc->sc_heldchange) { 999 if (sc->sc_tx_busy) { 1000 sc->sc_heldtbc = sc->sc_tbc; 1001 sc->sc_tbc = 0; 1002 sc->sc_heldchange = 1; 1003 } else 1004 scif_loadchannelregs(sc); 1005 } 1006 #endif 1007 } 1008 1009 /* 1010 * Stop output, e.g., for ^S or output flush. 1011 */ 1012 void 1013 scifstop(struct tty *tp, int flag) 1014 { 1015 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 1016 int s; 1017 1018 s = splserial(); 1019 if (ISSET(tp->t_state, TS_BUSY)) { 1020 /* Stop transmitting at the next chunk. */ 1021 sc->sc_tbc = 0; 1022 sc->sc_heldtbc = 0; 1023 if (!ISSET(tp->t_state, TS_TTSTOP)) 1024 SET(tp->t_state, TS_FLUSH); 1025 } 1026 splx(s); 1027 } 1028 1029 void 1030 scif_intr_init() 1031 { 1032 /* XXX */ 1033 } 1034 1035 void 1036 scifdiag(void *arg) 1037 { 1038 struct scif_softc *sc = arg; 1039 int overflows, floods; 1040 int s; 1041 1042 s = splserial(); 1043 overflows = sc->sc_overflows; 1044 sc->sc_overflows = 0; 1045 floods = sc->sc_floods; 1046 sc->sc_floods = 0; 1047 sc->sc_errors = 0; 1048 splx(s); 1049 1050 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1051 sc->sc_dev.dv_xname, 1052 overflows, overflows == 1 ? "" : "s", 1053 floods, floods == 1 ? "" : "s"); 1054 } 1055 1056 integrate void 1057 scif_rxsoft(struct scif_softc *sc, struct tty *tp) 1058 { 1059 int (*rint)(int c, struct tty *tp) = tp->t_linesw->l_rint; 1060 u_char *get, *end; 1061 u_int cc, scc; 1062 u_char ssr2; 1063 int code; 1064 int s; 1065 1066 end = sc->sc_ebuf; 1067 get = sc->sc_rbget; 1068 scc = cc = scif_rbuf_size - sc->sc_rbavail; 1069 1070 if (cc == scif_rbuf_size) { 1071 sc->sc_floods++; 1072 if (sc->sc_errors++ == 0) 1073 callout_reset(&sc->sc_diag_ch, 60 * hz, scifdiag, sc); 1074 } 1075 1076 while (cc) { 1077 code = get[0]; 1078 ssr2 = get[1]; 1079 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) { 1080 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER)) 1081 SET(code, TTY_FE); 1082 if (ISSET(ssr2, SCSSR2_PER)) 1083 SET(code, TTY_PE); 1084 } 1085 if ((*rint)(code, tp) == -1) { 1086 /* 1087 * The line discipline's buffer is out of space. 1088 */ 1089 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1090 /* 1091 * We're either not using flow control, or the 1092 * line discipline didn't tell us to block for 1093 * some reason. Either way, we have no way to 1094 * know when there's more space available, so 1095 * just drop the rest of the data. 1096 */ 1097 get += cc << 1; 1098 if (get >= end) 1099 get -= scif_rbuf_size << 1; 1100 cc = 0; 1101 } else { 1102 /* 1103 * Don't schedule any more receive processing 1104 * until the line discipline tells us there's 1105 * space available (through scifhwiflow()). 1106 * Leave the rest of the data in the input 1107 * buffer. 1108 */ 1109 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1110 } 1111 break; 1112 } 1113 get += 2; 1114 if (get >= end) 1115 get = sc->sc_rbuf; 1116 cc--; 1117 } 1118 1119 if (cc != scc) { 1120 sc->sc_rbget = get; 1121 s = splserial(); 1122 cc = sc->sc_rbavail += scc - cc; 1123 /* Buffers should be ok again, release possible block. */ 1124 if (cc >= sc->sc_r_lowat) { 1125 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1126 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1127 scif_scr_write(scif_scr_read() | SCSCR2_RIE); 1128 } 1129 #if 0 1130 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1131 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1132 scif_hwiflow(sc); 1133 } 1134 #endif 1135 } 1136 splx(s); 1137 } 1138 } 1139 1140 integrate void 1141 scif_txsoft(struct scif_softc *sc, struct tty *tp) 1142 { 1143 1144 CLR(tp->t_state, TS_BUSY); 1145 if (ISSET(tp->t_state, TS_FLUSH)) 1146 CLR(tp->t_state, TS_FLUSH); 1147 else 1148 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1149 (*tp->t_linesw->l_start)(tp); 1150 } 1151 1152 integrate void 1153 scif_stsoft(struct scif_softc *sc, struct tty *tp) 1154 { 1155 #if 0 1156 /* XXX (msaitoh) */ 1157 u_char msr, delta; 1158 int s; 1159 1160 s = splserial(); 1161 msr = sc->sc_msr; 1162 delta = sc->sc_msr_delta; 1163 sc->sc_msr_delta = 0; 1164 splx(s); 1165 1166 if (ISSET(delta, sc->sc_msr_dcd)) { 1167 /* 1168 * Inform the tty layer that carrier detect changed. 1169 */ 1170 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1171 } 1172 1173 if (ISSET(delta, sc->sc_msr_cts)) { 1174 /* Block or unblock output according to flow control. */ 1175 if (ISSET(msr, sc->sc_msr_cts)) { 1176 sc->sc_tx_stopped = 0; 1177 (*tp->t_linesw->l_start)(tp); 1178 } else { 1179 sc->sc_tx_stopped = 1; 1180 } 1181 } 1182 1183 #ifdef SCIF_DEBUG 1184 if (scif_debug) 1185 scifstatus(sc, "scif_stsoft"); 1186 #endif 1187 #endif 1188 } 1189 1190 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1191 void 1192 scifsoft(void *arg) 1193 { 1194 struct scif_softc *sc = arg; 1195 struct tty *tp; 1196 1197 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1198 return; 1199 1200 { 1201 #else 1202 void 1203 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1204 scifsoft() 1205 #else 1206 scifsoft(void *arg) 1207 #endif 1208 { 1209 struct scif_softc *sc; 1210 struct tty *tp; 1211 int unit; 1212 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1213 int s; 1214 1215 s = splsoftserial(); 1216 scif_softintr_scheduled = 0; 1217 #endif 1218 1219 for (unit = 0; unit < scif_cd.cd_ndevs; unit++) { 1220 sc = scif_cd.cd_devs[unit]; 1221 if (sc == NULL || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK)) 1222 continue; 1223 1224 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1225 continue; 1226 1227 tp = sc->sc_tty; 1228 if (tp == NULL) 1229 continue; 1230 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 1231 continue; 1232 #endif 1233 tp = sc->sc_tty; 1234 1235 if (sc->sc_rx_ready) { 1236 sc->sc_rx_ready = 0; 1237 scif_rxsoft(sc, tp); 1238 } 1239 1240 #if 0 1241 if (sc->sc_st_check) { 1242 sc->sc_st_check = 0; 1243 scif_stsoft(sc, tp); 1244 } 1245 #endif 1246 1247 if (sc->sc_tx_done) { 1248 sc->sc_tx_done = 0; 1249 scif_txsoft(sc, tp); 1250 } 1251 } 1252 1253 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1254 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1255 splx(s); 1256 #endif 1257 #endif 1258 } 1259 1260 int 1261 scifintr(void *arg) 1262 { 1263 struct scif_softc *sc = arg; 1264 u_char *put, *end; 1265 u_int cc; 1266 u_short ssr2; 1267 int count; 1268 1269 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1270 return (0); 1271 1272 end = sc->sc_ebuf; 1273 put = sc->sc_rbput; 1274 cc = sc->sc_rbavail; 1275 1276 do { 1277 ssr2 = scif_ssr_read(); 1278 if (ISSET(ssr2, SCSSR2_BRK)) { 1279 scif_ssr_write(scif_ssr_read() 1280 & ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR)); 1281 #ifdef DDB 1282 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 1283 console_debugger(); 1284 } 1285 #endif /* DDB */ 1286 #ifdef KGDB 1287 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) { 1288 kgdb_connect(1); 1289 } 1290 #endif /* KGDB */ 1291 } 1292 count = scif_fdr_read() & SCFDR2_RECVCNT; 1293 if (count != 0) { 1294 for (;;) { 1295 u_char c = scif_frdr_read(); 1296 u_char err = (u_char)(scif_ssr_read() & 0x00ff); 1297 1298 scif_ssr_write(scif_ssr_read() 1299 & ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR)); 1300 #ifdef SH4 1301 if (CPU_IS_SH4) 1302 scif_lsr_write(scif_lsr_read() 1303 & ~SCLSR2_ORER); 1304 #endif 1305 if ((cc > 0) && (count > 0)) { 1306 put[0] = c; 1307 put[1] = err; 1308 put += 2; 1309 if (put >= end) 1310 put = sc->sc_rbuf; 1311 cc--; 1312 count--; 1313 } else 1314 break; 1315 } 1316 1317 /* 1318 * Current string of incoming characters ended because 1319 * no more data was available or we ran out of space. 1320 * Schedule a receive event if any data was received. 1321 * If we're out of space, turn off receive interrupts. 1322 */ 1323 sc->sc_rbput = put; 1324 sc->sc_rbavail = cc; 1325 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1326 sc->sc_rx_ready = 1; 1327 1328 /* 1329 * See if we are in danger of overflowing a buffer. If 1330 * so, use hardware flow control to ease the pressure. 1331 */ 1332 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1333 cc < sc->sc_r_hiwat) { 1334 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1335 #if 0 1336 scif_hwiflow(sc); 1337 #endif 1338 } 1339 1340 /* 1341 * If we're out of space, disable receive interrupts 1342 * until the queue has drained a bit. 1343 */ 1344 if (!cc) { 1345 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1346 scif_scr_write(scif_scr_read() & ~SCSCR2_RIE); 1347 } 1348 } else { 1349 if (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR)) { 1350 scif_scr_write(scif_scr_read() 1351 & ~(SCSCR2_TIE | SCSCR2_RIE)); 1352 delay(10); 1353 scif_scr_write(scif_scr_read() 1354 | SCSCR2_TIE | SCSCR2_RIE); 1355 continue; 1356 } 1357 } 1358 } while (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR)); 1359 1360 #if 0 1361 msr = bus_space_read_1(iot, ioh, scif_msr); 1362 delta = msr ^ sc->sc_msr; 1363 sc->sc_msr = msr; 1364 if (ISSET(delta, sc->sc_msr_mask)) { 1365 SET(sc->sc_msr_delta, delta); 1366 1367 /* 1368 * Pulse-per-second clock signal on edge of DCD? 1369 */ 1370 if (ISSET(delta, sc->sc_ppsmask)) { 1371 struct timeval tv; 1372 if (ISSET(msr, sc->sc_ppsmask) == 1373 sc->sc_ppsassert) { 1374 /* XXX nanotime() */ 1375 microtime(&tv); 1376 TIMEVAL_TO_TIMESPEC(&tv, 1377 &sc->ppsinfo.assert_timestamp); 1378 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 1379 timespecadd(&sc->ppsinfo.assert_timestamp, 1380 &sc->ppsparam.assert_offset, 1381 &sc->ppsinfo.assert_timestamp); 1382 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp); 1383 } 1384 1385 #ifdef PPS_SYNC 1386 if (sc->ppsparam.mode & PPS_HARDPPSONASSERT) 1387 hardpps(&tv, tv.tv_usec); 1388 #endif 1389 sc->ppsinfo.assert_sequence++; 1390 sc->ppsinfo.current_mode = 1391 sc->ppsparam.mode; 1392 1393 } else if (ISSET(msr, sc->sc_ppsmask) == 1394 sc->sc_ppsclear) { 1395 /* XXX nanotime() */ 1396 microtime(&tv); 1397 TIMEVAL_TO_TIMESPEC(&tv, 1398 &sc->ppsinfo.clear_timestamp); 1399 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 1400 timespecadd(&sc->ppsinfo.clear_timestamp, 1401 &sc->ppsparam.clear_offset, 1402 &sc->ppsinfo.clear_timestamp); 1403 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp); 1404 } 1405 1406 #ifdef PPS_SYNC 1407 if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR) 1408 hardpps(&tv, tv.tv_usec); 1409 #endif 1410 sc->ppsinfo.clear_sequence++; 1411 sc->ppsinfo.current_mode = 1412 sc->ppsparam.mode; 1413 } 1414 } 1415 1416 /* 1417 * Stop output immediately if we lose the output 1418 * flow control signal or carrier detect. 1419 */ 1420 if (ISSET(~msr, sc->sc_msr_mask)) { 1421 sc->sc_tbc = 0; 1422 sc->sc_heldtbc = 0; 1423 #ifdef SCIF_DEBUG 1424 if (scif_debug) 1425 scifstatus(sc, "scifintr "); 1426 #endif 1427 } 1428 1429 sc->sc_st_check = 1; 1430 } 1431 #endif 1432 1433 /* 1434 * Done handling any receive interrupts. See if data can be 1435 * transmitted as well. Schedule tx done event if no data left 1436 * and tty was marked busy. 1437 */ 1438 if (((scif_fdr_read() & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */ 1439 /* 1440 * If we've delayed a parameter change, do it now, and restart 1441 * output. 1442 */ 1443 if (sc->sc_heldchange) { 1444 sc->sc_heldchange = 0; 1445 sc->sc_tbc = sc->sc_heldtbc; 1446 sc->sc_heldtbc = 0; 1447 } 1448 1449 /* Output the next chunk of the contiguous buffer, if any. */ 1450 if (sc->sc_tbc > 0) { 1451 int n; 1452 int max; 1453 int i; 1454 1455 n = sc->sc_tbc; 1456 max = sc->sc_fifolen - 1457 ((scif_fdr_read() & SCFDR2_TXCNT) >> 8); 1458 if (n > max) 1459 n = max; 1460 1461 for (i = 0; i < n; i++) { 1462 scif_putc(*(sc->sc_tba)); 1463 sc->sc_tba++; 1464 } 1465 sc->sc_tbc -= n; 1466 } else { 1467 /* Disable transmit completion interrupts if necessary. */ 1468 #if 0 1469 if (ISSET(sc->sc_ier, IER_ETXRDY)) 1470 #endif 1471 scif_scr_write(scif_scr_read() & ~SCSCR2_TIE); 1472 1473 if (sc->sc_tx_busy) { 1474 sc->sc_tx_busy = 0; 1475 sc->sc_tx_done = 1; 1476 } 1477 } 1478 } 1479 1480 /* Wake up the poller. */ 1481 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1482 softintr_schedule(sc->sc_si); 1483 #else 1484 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1485 setsoftserial(); 1486 #else 1487 if (!scif_softintr_scheduled) { 1488 scif_softintr_scheduled = 1; 1489 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 1490 } 1491 #endif 1492 #endif 1493 1494 #if NRND > 0 && defined(RND_SCIF) 1495 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1496 #endif 1497 1498 return (1); 1499 } 1500 1501 void 1502 scifcnprobe(struct consdev *cp) 1503 { 1504 int maj; 1505 1506 /* locate the major number */ 1507 maj = cdevsw_lookup_major(&scif_cdevsw); 1508 1509 /* Initialize required fields. */ 1510 cp->cn_dev = makedev(maj, 0); 1511 #ifdef SCIFCONSOLE 1512 cp->cn_pri = CN_REMOTE; 1513 #else 1514 cp->cn_pri = CN_NORMAL; 1515 #endif 1516 } 1517 1518 void 1519 scifcninit(struct consdev *cp) 1520 { 1521 1522 InitializeScif(scifcn_speed); 1523 scifisconsole = 1; 1524 } 1525 1526 int 1527 scifcngetc(dev_t dev) 1528 { 1529 int c; 1530 int s; 1531 1532 s = splserial(); 1533 c = scif_getc(); 1534 splx(s); 1535 1536 return (c); 1537 } 1538 1539 void 1540 scifcnputc(dev_t dev, int c) 1541 { 1542 int s; 1543 1544 s = splserial(); 1545 scif_putc((u_char)c); 1546 splx(s); 1547 } 1548 1549 #ifdef KGDB 1550 int 1551 scif_kgdb_init() 1552 { 1553 1554 if (strcmp(kgdb_devname, "scif") != 0) 1555 return (1); 1556 1557 if (scifisconsole) 1558 return (1); /* can't share with console */ 1559 1560 InitializeScif(kgdb_rate); 1561 1562 kgdb_attach((int (*)(void *))scifcngetc, 1563 (void (*)(void *, int))scifcnputc, NULL); 1564 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 1565 kgdb_attached = 1; 1566 1567 return (0); 1568 } 1569 #endif /* KGDB */ 1570
Indexes created Tue Sep 23 14:10:03 GMT 2025