scif.c revision 1.38
1 /* $NetBSD: scif.c,v 1.38 2004/12/13 02:14:13 chs Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Charles M. Hannum. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the NetBSD 47 * Foundation, Inc. and its contributors. 48 * 4. Neither the name of The NetBSD Foundation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 53 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 54 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * Copyright (c) 1991 The Regents of the University of California. 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. Neither the name of the University nor the names of its contributors 78 * may be used to endorse or promote products derived from this software 79 * without specific prior written permission. 80 * 81 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 82 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 83 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 84 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 85 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 86 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 87 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 88 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 89 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 90 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 91 * SUCH DAMAGE. 92 * 93 * @(#)com.c 7.5 (Berkeley) 5/16/91 94 */ 95 96 /* 97 * SH internal serial driver 98 * 99 * This code is derived from both z8530tty.c and com.c 100 */ 101 102 #include <sys/cdefs.h> 103 __KERNEL_RCSID(0, "$NetBSD: scif.c,v 1.38 2004/12/13 02:14:13 chs Exp $"); 104 105 #include "opt_kgdb.h" 106 #include "opt_scif.h" 107 108 #include <sys/param.h> 109 #include <sys/systm.h> 110 #include <sys/tty.h> 111 #include <sys/proc.h> 112 #include <sys/conf.h> 113 #include <sys/file.h> 114 #include <sys/syslog.h> 115 #include <sys/kernel.h> 116 #include <sys/device.h> 117 #include <sys/malloc.h> 118 #include <sys/kgdb.h> 119 120 #include <dev/cons.h> 121 122 #include <sh3/clock.h> 123 #include <sh3/exception.h> 124 #include <sh3/scifreg.h> 125 #include <machine/intr.h> 126 127 #include <sh3/dev/scifvar.h> 128 129 #include "locators.h" 130 131 static void scifstart(struct tty *); 132 static int scifparam(struct tty *, struct termios *); 133 static int kgdb_attached; 134 135 void scifcnprobe(struct consdev *); 136 void scifcninit(struct consdev *); 137 void scifcnputc(dev_t, int); 138 int scifcngetc(dev_t); 139 void scifcnpoolc(dev_t, int); 140 void scif_intr_init(void); 141 int scifintr(void *); 142 143 struct scif_softc { 144 struct device sc_dev; /* boilerplate */ 145 struct tty *sc_tty; 146 void *sc_si; 147 148 struct callout sc_diag_ch; 149 150 #if 0 151 bus_space_tag_t sc_iot; /* ISA i/o space identifier */ 152 bus_space_handle_t sc_ioh; /* ISA io handle */ 153 154 int sc_drq; 155 156 int sc_frequency; 157 #endif 158 159 u_int sc_overflows, 160 sc_floods, 161 sc_errors; /* number of retries so far */ 162 u_char sc_status[7]; /* copy of registers */ 163 164 int sc_hwflags; 165 int sc_swflags; 166 u_int sc_fifolen; 167 168 u_int sc_r_hiwat, 169 sc_r_lowat; 170 u_char *volatile sc_rbget, 171 *volatile sc_rbput; 172 volatile u_int sc_rbavail; 173 u_char *sc_rbuf, 174 *sc_ebuf; 175 176 u_char *sc_tba; /* transmit buffer address */ 177 u_int sc_tbc, /* transmit byte count */ 178 sc_heldtbc; 179 180 volatile u_char sc_rx_flags, 181 #define RX_TTY_BLOCKED 0x01 182 #define RX_TTY_OVERFLOWED 0x02 183 #define RX_IBUF_BLOCKED 0x04 184 #define RX_IBUF_OVERFLOWED 0x08 185 #define RX_ANY_BLOCK 0x0f 186 sc_tx_busy, /* working on an output chunk */ 187 sc_tx_done, /* done with one output chunk */ 188 sc_tx_stopped, /* H/W level stop (lost CTS) */ 189 sc_st_check, /* got a status interrupt */ 190 sc_rx_ready; 191 192 volatile u_char sc_heldchange; 193 }; 194 195 /* controller driver configuration */ 196 static int scif_match(struct device *, struct cfdata *, void *); 197 static void scif_attach(struct device *, struct device *, void *); 198 199 void scif_break(struct scif_softc *, int); 200 void scif_iflush(struct scif_softc *); 201 202 #define integrate static inline 203 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 204 void scifsoft(void *); 205 #else 206 #ifndef __NO_SOFT_SERIAL_INTERRUPT 207 void scifsoft(void); 208 #else 209 void scifsoft(void *); 210 #endif 211 #endif 212 integrate void scif_rxsoft(struct scif_softc *, struct tty *); 213 integrate void scif_txsoft(struct scif_softc *, struct tty *); 214 integrate void scif_stsoft(struct scif_softc *, struct tty *); 215 integrate void scif_schedrx(struct scif_softc *); 216 void scifdiag(void *); 217 218 219 #define SCIFUNIT_MASK 0x7ffff 220 #define SCIFDIALOUT_MASK 0x80000 221 222 #define SCIFUNIT(x) (minor(x) & SCIFUNIT_MASK) 223 #define SCIFDIALOUT(x) (minor(x) & SCIFDIALOUT_MASK) 224 225 /* Macros to clear/set/test flags. */ 226 #define SET(t, f) (t) |= (f) 227 #define CLR(t, f) (t) &= ~(f) 228 #define ISSET(t, f) ((t) & (f)) 229 230 /* Hardware flag masks */ 231 #define SCIF_HW_NOIEN 0x01 232 #define SCIF_HW_FIFO 0x02 233 #define SCIF_HW_FLOW 0x08 234 #define SCIF_HW_DEV_OK 0x20 235 #define SCIF_HW_CONSOLE 0x40 236 #define SCIF_HW_KGDB 0x80 237 238 /* Buffer size for character buffer */ 239 #define SCIF_RING_SIZE 2048 240 241 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 242 u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4; 243 u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4; 244 245 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 246 int scifconscflag = CONMODE; 247 int scifisconsole = 0; 248 249 #ifdef SCIFCN_SPEED 250 unsigned int scifcn_speed = SCIFCN_SPEED; 251 #else 252 unsigned int scifcn_speed = 9600; 253 #endif 254 255 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 256 257 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 258 #ifdef __NO_SOFT_SERIAL_INTERRUPT 259 volatile int scif_softintr_scheduled; 260 struct callout scif_soft_ch = CALLOUT_INITIALIZER; 261 #endif 262 #endif 263 264 u_int scif_rbuf_size = SCIF_RING_SIZE; 265 266 CFATTACH_DECL(scif, sizeof(struct scif_softc), 267 scif_match, scif_attach, NULL, NULL); 268 269 extern struct cfdriver scif_cd; 270 271 static int scif_attached; 272 273 dev_type_open(scifopen); 274 dev_type_close(scifclose); 275 dev_type_read(scifread); 276 dev_type_write(scifwrite); 277 dev_type_ioctl(scifioctl); 278 dev_type_stop(scifstop); 279 dev_type_tty(sciftty); 280 dev_type_poll(scifpoll); 281 282 const struct cdevsw scif_cdevsw = { 283 scifopen, scifclose, scifread, scifwrite, scifioctl, 284 scifstop, sciftty, scifpoll, nommap, ttykqfilter, D_TTY 285 }; 286 287 void InitializeScif (unsigned int); 288 289 /* 290 * following functions are debugging prupose only 291 */ 292 #define CR 0x0D 293 #define USART_ON (unsigned int)~0x08 294 295 void scif_putc(unsigned char); 296 unsigned char scif_getc(void); 297 int ScifErrCheck(void); 298 299 300 /* XXX: uwe 301 * Prepare for bus_spacification. The difference in access widths is 302 * still handled by the magic definitions in scifreg.h 303 */ 304 #define scif_smr_read() SHREG_SCSMR2 305 #define scif_smr_write(v) (SHREG_SCSMR2 = (v)) 306 307 #define scif_brr_read() SHREG_SCBRR2 308 #define scif_brr_write(v) (SHREG_SCBRR2 = (v)) 309 310 #define scif_scr_read() SHREG_SCSCR2 311 #define scif_scr_write(v) (SHREG_SCSCR2 = (v)) 312 313 #define scif_ftdr_write(v) (SHREG_SCFTDR2 = (v)) 314 315 #define scif_ssr_read() SHREG_SCSSR2 316 #define scif_ssr_write(v) (SHREG_SCSSR2 = (v)) 317 318 #define scif_frdr_read() SHREG_SCFRDR2 319 320 #define scif_fcr_read() SHREG_SCFCR2 321 #define scif_fcr_write(v) (SHREG_SCFCR2 = (v)) 322 323 #define scif_fdr_read() SHREG_SCFDR2 324 325 #ifdef SH4 /* additional registers in sh4 */ 326 327 #define scif_sptr_read() SHREG_SCSPTR2 328 #define scif_sptr_write(v) (SHREG_SCSPTR2 = (v)) 329 330 #define scif_lsr_read() SHREG_SCLSR2 331 #define scif_lsr_write(v) (SHREG_SCLSR2 = (v)) 332 333 #endif /* SH4 */ 334 335 336 /* 337 * InitializeScif 338 * : unsigned int bps; 339 * : SCIF(Serial Communication Interface) 340 */ 341 342 void 343 InitializeScif(unsigned int bps) 344 { 345 346 /* Initialize SCR */ 347 scif_scr_write(0x00); 348 349 #if 0 350 scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE); 351 #else 352 scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST); 353 #endif 354 /* Serial Mode Register */ 355 scif_smr_write(0x00); /* 8bit,NonParity,Even,1Stop */ 356 357 /* Bit Rate Register */ 358 scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * bps) - 1); 359 360 /* 361 * wait 1mSec, because Send/Recv must begin 1 bit period after 362 * BRR is set. 363 */ 364 delay(1000); 365 366 #if 0 367 scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE); 368 #else 369 scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1); 370 #endif 371 372 /* Send permission, Receive permission ON */ 373 scif_scr_write(SCSCR2_TE | SCSCR2_RE); 374 375 /* Serial Status Register */ 376 scif_ssr_write(scif_ssr_read() & SCSSR2_TDFE); /* Clear Status */ 377 } 378 379 380 /* 381 * scif_putc 382 * : unsigned char c; 383 */ 384 385 void 386 scif_putc(unsigned char c) 387 { 388 389 /* wait for ready */ 390 while ((scif_fdr_read() & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) 391 continue; 392 393 /* write send data to send register */ 394 scif_ftdr_write(c); 395 396 /* clear ready flag */ 397 scif_ssr_write(scif_ssr_read() & ~(SCSSR2_TDFE | SCSSR2_TEND)); 398 } 399 400 /* 401 * : ScifErrCheck 402 * 0x80 = error 403 * 0x08 = frame error 404 * 0x04 = parity error 405 */ 406 int 407 ScifErrCheck(void) 408 { 409 410 return (scif_ssr_read() & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)); 411 } 412 413 /* 414 * scif_getc 415 */ 416 unsigned char 417 scif_getc(void) 418 { 419 unsigned char c, err_c; 420 #ifdef SH4 421 unsigned short err_c2; 422 #endif 423 424 for (;;) { 425 /* wait for ready */ 426 while ((scif_fdr_read() & SCFDR2_RECVCNT) == 0) 427 continue; 428 429 c = scif_frdr_read(); 430 err_c = scif_ssr_read(); 431 scif_ssr_write(scif_ssr_read() 432 & ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF | SCSSR2_DR)); 433 #ifdef SH4 434 if (CPU_IS_SH4) { 435 err_c2 = scif_lsr_read(); 436 scif_lsr_write(scif_lsr_read() & ~SCLSR2_ORER); 437 } 438 #endif 439 if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER 440 | SCSSR2_PER)) == 0) { 441 #ifdef SH4 442 if (CPU_IS_SH4 && ((err_c2 & SCLSR2_ORER) == 0)) 443 #endif 444 return(c); 445 } 446 } 447 448 } 449 450 static int 451 scif_match(struct device *parent, struct cfdata *cfp, void *aux) 452 { 453 454 if (strcmp(cfp->cf_name, "scif") || scif_attached) 455 return 0; 456 457 return 1; 458 } 459 460 static void 461 scif_attach(struct device *parent, struct device *self, void *aux) 462 { 463 struct scif_softc *sc = (struct scif_softc *)self; 464 struct tty *tp; 465 466 scif_attached = 1; 467 468 sc->sc_hwflags = 0; /* XXX */ 469 sc->sc_swflags = 0; /* XXX */ 470 sc->sc_fifolen = 16; 471 472 if (scifisconsole || kgdb_attached) { 473 /* InitializeScif(scifcn_speed); */ 474 SET(sc->sc_hwflags, SCIF_HW_CONSOLE); 475 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 476 if (kgdb_attached) { 477 SET(sc->sc_hwflags, SCIF_HW_KGDB); 478 printf("\n%s: kgdb\n", sc->sc_dev.dv_xname); 479 } else { 480 printf("\n%s: console\n", sc->sc_dev.dv_xname); 481 } 482 } else { 483 InitializeScif(9600); 484 printf("\n"); 485 } 486 487 callout_init(&sc->sc_diag_ch); 488 #ifdef SH4 489 intc_intr_establish(SH4_INTEVT_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 490 scifintr, sc); 491 intc_intr_establish(SH4_INTEVT_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 492 scifintr, sc); 493 intc_intr_establish(SH4_INTEVT_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 494 scifintr, sc); 495 intc_intr_establish(SH4_INTEVT_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 496 scifintr, sc); 497 #else 498 intc_intr_establish(SH7709_INTEVT2_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 499 scifintr, sc); 500 intc_intr_establish(SH7709_INTEVT2_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 501 scifintr, sc); 502 intc_intr_establish(SH7709_INTEVT2_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 503 scifintr, sc); 504 intc_intr_establish(SH7709_INTEVT2_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 505 scifintr, sc); 506 #endif 507 508 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 509 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, scifsoft, sc); 510 #endif 511 SET(sc->sc_hwflags, SCIF_HW_DEV_OK); 512 513 tp = ttymalloc(); 514 tp->t_oproc = scifstart; 515 tp->t_param = scifparam; 516 tp->t_hwiflow = NULL; 517 518 sc->sc_tty = tp; 519 sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 520 if (sc->sc_rbuf == NULL) { 521 printf("%s: unable to allocate ring buffer\n", 522 sc->sc_dev.dv_xname); 523 return; 524 } 525 sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1); 526 527 tty_attach(tp); 528 } 529 530 /* 531 * Start or restart transmission. 532 */ 533 static void 534 scifstart(struct tty *tp) 535 { 536 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 537 int s; 538 539 s = spltty(); 540 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 541 goto out; 542 if (sc->sc_tx_stopped) 543 goto out; 544 545 if (tp->t_outq.c_cc <= tp->t_lowat) { 546 if (ISSET(tp->t_state, TS_ASLEEP)) { 547 CLR(tp->t_state, TS_ASLEEP); 548 wakeup(&tp->t_outq); 549 } 550 selwakeup(&tp->t_wsel); 551 if (tp->t_outq.c_cc == 0) 552 goto out; 553 } 554 555 /* Grab the first contiguous region of buffer space. */ 556 { 557 u_char *tba; 558 int tbc; 559 560 tba = tp->t_outq.c_cf; 561 tbc = ndqb(&tp->t_outq, 0); 562 563 (void)splserial(); 564 565 sc->sc_tba = tba; 566 sc->sc_tbc = tbc; 567 } 568 569 SET(tp->t_state, TS_BUSY); 570 sc->sc_tx_busy = 1; 571 572 /* Enable transmit completion interrupts if necessary. */ 573 scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE); 574 575 /* Output the first chunk of the contiguous buffer. */ 576 { 577 int n; 578 int max; 579 int i; 580 581 n = sc->sc_tbc; 582 max = sc->sc_fifolen - ((scif_fdr_read() & SCFDR2_TXCNT) >> 8); 583 if (n > max) 584 n = max; 585 586 for (i = 0; i < n; i++) { 587 scif_putc(*(sc->sc_tba)); 588 sc->sc_tba++; 589 } 590 sc->sc_tbc -= n; 591 } 592 out: 593 splx(s); 594 return; 595 } 596 597 /* 598 * Set SCIF tty parameters from termios. 599 * XXX - Should just copy the whole termios after 600 * making sure all the changes could be done. 601 */ 602 static int 603 scifparam(struct tty *tp, struct termios *t) 604 { 605 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 606 int ospeed = t->c_ospeed; 607 int s; 608 609 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 610 return (EIO); 611 612 /* Check requested parameters. */ 613 if (ospeed < 0) 614 return (EINVAL); 615 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 616 return (EINVAL); 617 618 /* 619 * For the console, always force CLOCAL and !HUPCL, so that the port 620 * is always active. 621 */ 622 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 623 ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 624 SET(t->c_cflag, CLOCAL); 625 CLR(t->c_cflag, HUPCL); 626 } 627 628 /* 629 * If there were no changes, don't do anything. This avoids dropping 630 * input and improves performance when all we did was frob things like 631 * VMIN and VTIME. 632 */ 633 if (tp->t_ospeed == t->c_ospeed && 634 tp->t_cflag == t->c_cflag) 635 return (0); 636 637 #if 0 638 /* XXX (msaitoh) */ 639 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 640 #endif 641 642 s = splserial(); 643 644 /* 645 * Set the flow control pins depending on the current flow control 646 * mode. 647 */ 648 if (ISSET(t->c_cflag, CRTSCTS)) { 649 scif_fcr_write(scif_fcr_read() | SCFCR2_MCE); 650 } else { 651 scif_fcr_write(scif_fcr_read() & ~SCFCR2_MCE); 652 } 653 654 scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * ospeed) -1); 655 656 /* 657 * Set the FIFO threshold based on the receive speed. 658 * 659 * * If it's a low speed, it's probably a mouse or some other 660 * interactive device, so set the threshold low. 661 * * If it's a high speed, trim the trigger level down to prevent 662 * overflows. 663 * * Otherwise set it a bit higher. 664 */ 665 #if 0 666 /* XXX (msaitoh) */ 667 if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP)) 668 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 669 else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO)) 670 sc->sc_fifo = FIFO_ENABLE | 671 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : 672 t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4); 673 else 674 sc->sc_fifo = 0; 675 #endif 676 677 /* And copy to tty. */ 678 tp->t_ispeed = 0; 679 tp->t_ospeed = t->c_ospeed; 680 tp->t_cflag = t->c_cflag; 681 682 if (!sc->sc_heldchange) { 683 if (sc->sc_tx_busy) { 684 sc->sc_heldtbc = sc->sc_tbc; 685 sc->sc_tbc = 0; 686 sc->sc_heldchange = 1; 687 } 688 #if 0 689 /* XXX (msaitoh) */ 690 else 691 scif_loadchannelregs(sc); 692 #endif 693 } 694 695 if (!ISSET(t->c_cflag, CHWFLOW)) { 696 /* Disable the high water mark. */ 697 sc->sc_r_hiwat = 0; 698 sc->sc_r_lowat = 0; 699 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 700 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 701 scif_schedrx(sc); 702 } 703 } else { 704 sc->sc_r_hiwat = scif_rbuf_hiwat; 705 sc->sc_r_lowat = scif_rbuf_lowat; 706 } 707 708 splx(s); 709 710 #ifdef SCIF_DEBUG 711 if (scif_debug) 712 scifstatus(sc, "scifparam "); 713 #endif 714 715 if (!ISSET(t->c_cflag, CHWFLOW)) { 716 if (sc->sc_tx_stopped) { 717 sc->sc_tx_stopped = 0; 718 scifstart(tp); 719 } 720 } 721 722 return (0); 723 } 724 725 void 726 scif_iflush(struct scif_softc *sc) 727 { 728 int i; 729 unsigned char c; 730 731 i = scif_fdr_read() & SCFDR2_RECVCNT; 732 733 while (i > 0) { 734 c = scif_frdr_read(); 735 scif_ssr_write(scif_ssr_read() & ~(SCSSR2_RDF | SCSSR2_DR)); 736 i--; 737 } 738 } 739 740 int 741 scifopen(dev_t dev, int flag, int mode, struct proc *p) 742 { 743 int unit = SCIFUNIT(dev); 744 struct scif_softc *sc; 745 struct tty *tp; 746 int s, s2; 747 int error; 748 749 if (unit >= scif_cd.cd_ndevs) 750 return (ENXIO); 751 sc = scif_cd.cd_devs[unit]; 752 if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) || 753 sc->sc_rbuf == NULL) 754 return (ENXIO); 755 756 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 757 return (ENXIO); 758 759 #ifdef KGDB 760 /* 761 * If this is the kgdb port, no other use is permitted. 762 */ 763 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) 764 return (EBUSY); 765 #endif /* KGDB */ 766 767 tp = sc->sc_tty; 768 769 if (ISSET(tp->t_state, TS_ISOPEN) && 770 ISSET(tp->t_state, TS_XCLUDE) && 771 p->p_ucred->cr_uid != 0) 772 return (EBUSY); 773 774 s = spltty(); 775 776 /* 777 * Do the following iff this is a first open. 778 */ 779 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 780 struct termios t; 781 782 tp->t_dev = dev; 783 784 s2 = splserial(); 785 786 /* Turn on interrupts. */ 787 scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE); 788 789 splx(s2); 790 791 /* 792 * Initialize the termios status to the defaults. Add in the 793 * sticky bits from TIOCSFLAGS. 794 */ 795 t.c_ispeed = 0; 796 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 797 t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */ 798 t.c_cflag = scifconscflag; 799 } else { 800 t.c_ospeed = TTYDEF_SPEED; 801 t.c_cflag = TTYDEF_CFLAG; 802 } 803 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 804 SET(t.c_cflag, CLOCAL); 805 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 806 SET(t.c_cflag, CRTSCTS); 807 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 808 SET(t.c_cflag, MDMBUF); 809 /* Make sure scifparam() will do something. */ 810 tp->t_ospeed = 0; 811 (void) scifparam(tp, &t); 812 tp->t_iflag = TTYDEF_IFLAG; 813 tp->t_oflag = TTYDEF_OFLAG; 814 tp->t_lflag = TTYDEF_LFLAG; 815 ttychars(tp); 816 ttsetwater(tp); 817 818 s2 = splserial(); 819 820 /* Clear the input ring, and unblock. */ 821 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 822 sc->sc_rbavail = scif_rbuf_size; 823 scif_iflush(sc); 824 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 825 #if 0 826 /* XXX (msaitoh) */ 827 scif_hwiflow(sc); 828 #endif 829 830 #ifdef SCIF_DEBUG 831 if (scif_debug) 832 scifstatus(sc, "scifopen "); 833 #endif 834 835 splx(s2); 836 } 837 838 splx(s); 839 840 error = ttyopen(tp, SCIFDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 841 if (error) 842 goto bad; 843 844 error = (*tp->t_linesw->l_open)(dev, tp); 845 if (error) 846 goto bad; 847 848 return (0); 849 850 bad: 851 852 return (error); 853 } 854 855 int 856 scifclose(dev_t dev, int flag, int mode, struct proc *p) 857 { 858 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 859 struct tty *tp = sc->sc_tty; 860 861 /* XXX This is for cons.c. */ 862 if (!ISSET(tp->t_state, TS_ISOPEN)) 863 return (0); 864 865 (*tp->t_linesw->l_close)(tp, flag); 866 ttyclose(tp); 867 868 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 869 return (0); 870 871 return (0); 872 } 873 874 int 875 scifread(dev_t dev, struct uio *uio, int flag) 876 { 877 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 878 struct tty *tp = sc->sc_tty; 879 880 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 881 } 882 883 int 884 scifwrite(dev_t dev, struct uio *uio, int flag) 885 { 886 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 887 struct tty *tp = sc->sc_tty; 888 889 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 890 } 891 892 int 893 scifpoll(dev_t dev, int events, struct proc *p) 894 { 895 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 896 struct tty *tp = sc->sc_tty; 897 898 return ((*tp->t_linesw->l_poll)(tp, events, p)); 899 } 900 901 struct tty * 902 sciftty(dev_t dev) 903 { 904 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 905 struct tty *tp = sc->sc_tty; 906 907 return (tp); 908 } 909 910 int 911 scifioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p) 912 { 913 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 914 struct tty *tp = sc->sc_tty; 915 int error; 916 int s; 917 918 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 919 return (EIO); 920 921 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 922 if (error != EPASSTHROUGH) 923 return (error); 924 925 error = ttioctl(tp, cmd, data, flag, p); 926 if (error != EPASSTHROUGH) 927 return (error); 928 929 error = 0; 930 931 s = splserial(); 932 933 switch (cmd) { 934 case TIOCSBRK: 935 scif_break(sc, 1); 936 break; 937 938 case TIOCCBRK: 939 scif_break(sc, 0); 940 break; 941 942 case TIOCGFLAGS: 943 *(int *)data = sc->sc_swflags; 944 break; 945 946 case TIOCSFLAGS: 947 error = suser(p->p_ucred, &p->p_acflag); 948 if (error) 949 break; 950 sc->sc_swflags = *(int *)data; 951 break; 952 953 default: 954 error = EPASSTHROUGH; 955 break; 956 } 957 958 splx(s); 959 960 return (error); 961 } 962 963 integrate void 964 scif_schedrx(struct scif_softc *sc) 965 { 966 967 sc->sc_rx_ready = 1; 968 969 /* Wake up the poller. */ 970 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 971 softintr_schedule(sc->sc_si); 972 #else 973 #ifndef __NO_SOFT_SERIAL_INTERRUPT 974 setsoftserial(); 975 #else 976 if (!scif_softintr_scheduled) { 977 scif_softintr_scheduled = 1; 978 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 979 } 980 #endif 981 #endif 982 } 983 984 void 985 scif_break(struct scif_softc *sc, int onoff) 986 { 987 988 if (onoff) 989 scif_ssr_write(scif_ssr_read() & ~SCSSR2_TDFE); 990 else 991 scif_ssr_write(scif_ssr_read() | SCSSR2_TDFE); 992 993 #if 0 /* XXX */ 994 if (!sc->sc_heldchange) { 995 if (sc->sc_tx_busy) { 996 sc->sc_heldtbc = sc->sc_tbc; 997 sc->sc_tbc = 0; 998 sc->sc_heldchange = 1; 999 } else 1000 scif_loadchannelregs(sc); 1001 } 1002 #endif 1003 } 1004 1005 /* 1006 * Stop output, e.g., for ^S or output flush. 1007 */ 1008 void 1009 scifstop(struct tty *tp, int flag) 1010 { 1011 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 1012 int s; 1013 1014 s = splserial(); 1015 if (ISSET(tp->t_state, TS_BUSY)) { 1016 /* Stop transmitting at the next chunk. */ 1017 sc->sc_tbc = 0; 1018 sc->sc_heldtbc = 0; 1019 if (!ISSET(tp->t_state, TS_TTSTOP)) 1020 SET(tp->t_state, TS_FLUSH); 1021 } 1022 splx(s); 1023 } 1024 1025 void 1026 scif_intr_init() 1027 { 1028 /* XXX */ 1029 } 1030 1031 void 1032 scifdiag(void *arg) 1033 { 1034 struct scif_softc *sc = arg; 1035 int overflows, floods; 1036 int s; 1037 1038 s = splserial(); 1039 overflows = sc->sc_overflows; 1040 sc->sc_overflows = 0; 1041 floods = sc->sc_floods; 1042 sc->sc_floods = 0; 1043 sc->sc_errors = 0; 1044 splx(s); 1045 1046 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1047 sc->sc_dev.dv_xname, 1048 overflows, overflows == 1 ? "" : "s", 1049 floods, floods == 1 ? "" : "s"); 1050 } 1051 1052 integrate void 1053 scif_rxsoft(struct scif_softc *sc, struct tty *tp) 1054 { 1055 int (*rint)(int c, struct tty *tp) = tp->t_linesw->l_rint; 1056 u_char *get, *end; 1057 u_int cc, scc; 1058 u_char ssr2; 1059 int code; 1060 int s; 1061 1062 end = sc->sc_ebuf; 1063 get = sc->sc_rbget; 1064 scc = cc = scif_rbuf_size - sc->sc_rbavail; 1065 1066 if (cc == scif_rbuf_size) { 1067 sc->sc_floods++; 1068 if (sc->sc_errors++ == 0) 1069 callout_reset(&sc->sc_diag_ch, 60 * hz, scifdiag, sc); 1070 } 1071 1072 while (cc) { 1073 code = get[0]; 1074 ssr2 = get[1]; 1075 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) { 1076 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER)) 1077 SET(code, TTY_FE); 1078 if (ISSET(ssr2, SCSSR2_PER)) 1079 SET(code, TTY_PE); 1080 } 1081 if ((*rint)(code, tp) == -1) { 1082 /* 1083 * The line discipline's buffer is out of space. 1084 */ 1085 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1086 /* 1087 * We're either not using flow control, or the 1088 * line discipline didn't tell us to block for 1089 * some reason. Either way, we have no way to 1090 * know when there's more space available, so 1091 * just drop the rest of the data. 1092 */ 1093 get += cc << 1; 1094 if (get >= end) 1095 get -= scif_rbuf_size << 1; 1096 cc = 0; 1097 } else { 1098 /* 1099 * Don't schedule any more receive processing 1100 * until the line discipline tells us there's 1101 * space available (through scifhwiflow()). 1102 * Leave the rest of the data in the input 1103 * buffer. 1104 */ 1105 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1106 } 1107 break; 1108 } 1109 get += 2; 1110 if (get >= end) 1111 get = sc->sc_rbuf; 1112 cc--; 1113 } 1114 1115 if (cc != scc) { 1116 sc->sc_rbget = get; 1117 s = splserial(); 1118 cc = sc->sc_rbavail += scc - cc; 1119 /* Buffers should be ok again, release possible block. */ 1120 if (cc >= sc->sc_r_lowat) { 1121 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1122 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1123 scif_scr_write(scif_scr_read() | SCSCR2_RIE); 1124 } 1125 #if 0 1126 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1127 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1128 scif_hwiflow(sc); 1129 } 1130 #endif 1131 } 1132 splx(s); 1133 } 1134 } 1135 1136 integrate void 1137 scif_txsoft(struct scif_softc *sc, struct tty *tp) 1138 { 1139 1140 CLR(tp->t_state, TS_BUSY); 1141 if (ISSET(tp->t_state, TS_FLUSH)) 1142 CLR(tp->t_state, TS_FLUSH); 1143 else 1144 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1145 (*tp->t_linesw->l_start)(tp); 1146 } 1147 1148 integrate void 1149 scif_stsoft(struct scif_softc *sc, struct tty *tp) 1150 { 1151 #if 0 1152 /* XXX (msaitoh) */ 1153 u_char msr, delta; 1154 int s; 1155 1156 s = splserial(); 1157 msr = sc->sc_msr; 1158 delta = sc->sc_msr_delta; 1159 sc->sc_msr_delta = 0; 1160 splx(s); 1161 1162 if (ISSET(delta, sc->sc_msr_dcd)) { 1163 /* 1164 * Inform the tty layer that carrier detect changed. 1165 */ 1166 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1167 } 1168 1169 if (ISSET(delta, sc->sc_msr_cts)) { 1170 /* Block or unblock output according to flow control. */ 1171 if (ISSET(msr, sc->sc_msr_cts)) { 1172 sc->sc_tx_stopped = 0; 1173 (*tp->t_linesw->l_start)(tp); 1174 } else { 1175 sc->sc_tx_stopped = 1; 1176 } 1177 } 1178 1179 #ifdef SCIF_DEBUG 1180 if (scif_debug) 1181 scifstatus(sc, "scif_stsoft"); 1182 #endif 1183 #endif 1184 } 1185 1186 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1187 void 1188 scifsoft(void *arg) 1189 { 1190 struct scif_softc *sc = arg; 1191 struct tty *tp; 1192 1193 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1194 return; 1195 1196 { 1197 #else 1198 void 1199 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1200 scifsoft() 1201 #else 1202 scifsoft(void *arg) 1203 #endif 1204 { 1205 struct scif_softc *sc; 1206 struct tty *tp; 1207 int unit; 1208 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1209 int s; 1210 1211 s = splsoftserial(); 1212 scif_softintr_scheduled = 0; 1213 #endif 1214 1215 for (unit = 0; unit < scif_cd.cd_ndevs; unit++) { 1216 sc = scif_cd.cd_devs[unit]; 1217 if (sc == NULL || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK)) 1218 continue; 1219 1220 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1221 continue; 1222 1223 tp = sc->sc_tty; 1224 if (tp == NULL) 1225 continue; 1226 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 1227 continue; 1228 #endif 1229 tp = sc->sc_tty; 1230 1231 if (sc->sc_rx_ready) { 1232 sc->sc_rx_ready = 0; 1233 scif_rxsoft(sc, tp); 1234 } 1235 1236 #if 0 1237 if (sc->sc_st_check) { 1238 sc->sc_st_check = 0; 1239 scif_stsoft(sc, tp); 1240 } 1241 #endif 1242 1243 if (sc->sc_tx_done) { 1244 sc->sc_tx_done = 0; 1245 scif_txsoft(sc, tp); 1246 } 1247 } 1248 1249 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1250 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1251 splx(s); 1252 #endif 1253 #endif 1254 } 1255 1256 int 1257 scifintr(void *arg) 1258 { 1259 struct scif_softc *sc = arg; 1260 u_char *put, *end; 1261 u_int cc; 1262 u_short ssr2; 1263 int count; 1264 1265 if (ISSET(sc->sc_dev.dv_flags, DVF_ACTIVE) == 0) 1266 return (0); 1267 1268 end = sc->sc_ebuf; 1269 put = sc->sc_rbput; 1270 cc = sc->sc_rbavail; 1271 1272 do { 1273 ssr2 = scif_ssr_read(); 1274 if (ISSET(ssr2, SCSSR2_BRK)) { 1275 scif_ssr_write(scif_ssr_read() 1276 & ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR)); 1277 #ifdef DDB 1278 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 1279 console_debugger(); 1280 } 1281 #endif /* DDB */ 1282 #ifdef KGDB 1283 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) { 1284 kgdb_connect(1); 1285 } 1286 #endif /* KGDB */ 1287 } 1288 count = scif_fdr_read() & SCFDR2_RECVCNT; 1289 if (count != 0) { 1290 for (;;) { 1291 u_char c = scif_frdr_read(); 1292 u_char err = (u_char)(scif_ssr_read() & 0x00ff); 1293 1294 scif_ssr_write(scif_ssr_read() 1295 & ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR)); 1296 #ifdef SH4 1297 if (CPU_IS_SH4) 1298 scif_lsr_write(scif_lsr_read() 1299 & ~SCLSR2_ORER); 1300 #endif 1301 if ((cc > 0) && (count > 0)) { 1302 put[0] = c; 1303 put[1] = err; 1304 put += 2; 1305 if (put >= end) 1306 put = sc->sc_rbuf; 1307 cc--; 1308 count--; 1309 } else 1310 break; 1311 } 1312 1313 /* 1314 * Current string of incoming characters ended because 1315 * no more data was available or we ran out of space. 1316 * Schedule a receive event if any data was received. 1317 * If we're out of space, turn off receive interrupts. 1318 */ 1319 sc->sc_rbput = put; 1320 sc->sc_rbavail = cc; 1321 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1322 sc->sc_rx_ready = 1; 1323 1324 /* 1325 * See if we are in danger of overflowing a buffer. If 1326 * so, use hardware flow control to ease the pressure. 1327 */ 1328 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1329 cc < sc->sc_r_hiwat) { 1330 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1331 #if 0 1332 scif_hwiflow(sc); 1333 #endif 1334 } 1335 1336 /* 1337 * If we're out of space, disable receive interrupts 1338 * until the queue has drained a bit. 1339 */ 1340 if (!cc) { 1341 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1342 scif_scr_write(scif_scr_read() & ~SCSCR2_RIE); 1343 } 1344 } else { 1345 if (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR)) { 1346 scif_scr_write(scif_scr_read() 1347 & ~(SCSCR2_TIE | SCSCR2_RIE)); 1348 delay(10); 1349 scif_scr_write(scif_scr_read() 1350 | SCSCR2_TIE | SCSCR2_RIE); 1351 continue; 1352 } 1353 } 1354 } while (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR)); 1355 1356 #if 0 1357 msr = bus_space_read_1(iot, ioh, scif_msr); 1358 delta = msr ^ sc->sc_msr; 1359 sc->sc_msr = msr; 1360 if (ISSET(delta, sc->sc_msr_mask)) { 1361 SET(sc->sc_msr_delta, delta); 1362 1363 /* 1364 * Pulse-per-second clock signal on edge of DCD? 1365 */ 1366 if (ISSET(delta, sc->sc_ppsmask)) { 1367 struct timeval tv; 1368 if (ISSET(msr, sc->sc_ppsmask) == 1369 sc->sc_ppsassert) { 1370 /* XXX nanotime() */ 1371 microtime(&tv); 1372 TIMEVAL_TO_TIMESPEC(&tv, 1373 &sc->ppsinfo.assert_timestamp); 1374 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 1375 timespecadd(&sc->ppsinfo.assert_timestamp, 1376 &sc->ppsparam.assert_offset, 1377 &sc->ppsinfo.assert_timestamp); 1378 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp); 1379 } 1380 1381 #ifdef PPS_SYNC 1382 if (sc->ppsparam.mode & PPS_HARDPPSONASSERT) 1383 hardpps(&tv, tv.tv_usec); 1384 #endif 1385 sc->ppsinfo.assert_sequence++; 1386 sc->ppsinfo.current_mode = 1387 sc->ppsparam.mode; 1388 1389 } else if (ISSET(msr, sc->sc_ppsmask) == 1390 sc->sc_ppsclear) { 1391 /* XXX nanotime() */ 1392 microtime(&tv); 1393 TIMEVAL_TO_TIMESPEC(&tv, 1394 &sc->ppsinfo.clear_timestamp); 1395 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 1396 timespecadd(&sc->ppsinfo.clear_timestamp, 1397 &sc->ppsparam.clear_offset, 1398 &sc->ppsinfo.clear_timestamp); 1399 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp); 1400 } 1401 1402 #ifdef PPS_SYNC 1403 if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR) 1404 hardpps(&tv, tv.tv_usec); 1405 #endif 1406 sc->ppsinfo.clear_sequence++; 1407 sc->ppsinfo.current_mode = 1408 sc->ppsparam.mode; 1409 } 1410 } 1411 1412 /* 1413 * Stop output immediately if we lose the output 1414 * flow control signal or carrier detect. 1415 */ 1416 if (ISSET(~msr, sc->sc_msr_mask)) { 1417 sc->sc_tbc = 0; 1418 sc->sc_heldtbc = 0; 1419 #ifdef SCIF_DEBUG 1420 if (scif_debug) 1421 scifstatus(sc, "scifintr "); 1422 #endif 1423 } 1424 1425 sc->sc_st_check = 1; 1426 } 1427 #endif 1428 1429 /* 1430 * Done handling any receive interrupts. See if data can be 1431 * transmitted as well. Schedule tx done event if no data left 1432 * and tty was marked busy. 1433 */ 1434 if (((scif_fdr_read() & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */ 1435 /* 1436 * If we've delayed a parameter change, do it now, and restart 1437 * output. 1438 */ 1439 if (sc->sc_heldchange) { 1440 sc->sc_heldchange = 0; 1441 sc->sc_tbc = sc->sc_heldtbc; 1442 sc->sc_heldtbc = 0; 1443 } 1444 1445 /* Output the next chunk of the contiguous buffer, if any. */ 1446 if (sc->sc_tbc > 0) { 1447 int n; 1448 int max; 1449 int i; 1450 1451 n = sc->sc_tbc; 1452 max = sc->sc_fifolen - 1453 ((scif_fdr_read() & SCFDR2_TXCNT) >> 8); 1454 if (n > max) 1455 n = max; 1456 1457 for (i = 0; i < n; i++) { 1458 scif_putc(*(sc->sc_tba)); 1459 sc->sc_tba++; 1460 } 1461 sc->sc_tbc -= n; 1462 } else { 1463 /* Disable transmit completion interrupts if necessary. */ 1464 #if 0 1465 if (ISSET(sc->sc_ier, IER_ETXRDY)) 1466 #endif 1467 scif_scr_write(scif_scr_read() & ~SCSCR2_TIE); 1468 1469 if (sc->sc_tx_busy) { 1470 sc->sc_tx_busy = 0; 1471 sc->sc_tx_done = 1; 1472 } 1473 } 1474 } 1475 1476 /* Wake up the poller. */ 1477 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1478 softintr_schedule(sc->sc_si); 1479 #else 1480 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1481 setsoftserial(); 1482 #else 1483 if (!scif_softintr_scheduled) { 1484 scif_softintr_scheduled = 1; 1485 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 1486 } 1487 #endif 1488 #endif 1489 1490 #if NRND > 0 && defined(RND_SCIF) 1491 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1492 #endif 1493 1494 return (1); 1495 } 1496 1497 void 1498 scifcnprobe(struct consdev *cp) 1499 { 1500 int maj; 1501 1502 /* locate the major number */ 1503 maj = cdevsw_lookup_major(&scif_cdevsw); 1504 1505 /* Initialize required fields. */ 1506 cp->cn_dev = makedev(maj, 0); 1507 #ifdef SCIFCONSOLE 1508 cp->cn_pri = CN_REMOTE; 1509 #else 1510 cp->cn_pri = CN_NORMAL; 1511 #endif 1512 } 1513 1514 void 1515 scifcninit(struct consdev *cp) 1516 { 1517 1518 InitializeScif(scifcn_speed); 1519 scifisconsole = 1; 1520 } 1521 1522 int 1523 scifcngetc(dev_t dev) 1524 { 1525 int c; 1526 int s; 1527 1528 s = splserial(); 1529 c = scif_getc(); 1530 splx(s); 1531 1532 return (c); 1533 } 1534 1535 void 1536 scifcnputc(dev_t dev, int c) 1537 { 1538 int s; 1539 1540 s = splserial(); 1541 scif_putc((u_char)c); 1542 splx(s); 1543 } 1544 1545 #ifdef KGDB 1546 int 1547 scif_kgdb_init() 1548 { 1549 1550 if (strcmp(kgdb_devname, "scif") != 0) 1551 return (1); 1552 1553 if (scifisconsole) 1554 return (1); /* can't share with console */ 1555 1556 InitializeScif(kgdb_rate); 1557 1558 kgdb_attach((int (*)(void *))scifcngetc, 1559 (void (*)(void *, int))scifcnputc, NULL); 1560 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 1561 kgdb_attached = 1; 1562 1563 return (0); 1564 } 1565 #endif /* KGDB */ 1566
Indexes created Thu Sep 25 14:09:45 GMT 2025