scif.c revision 1.47
1 /* $NetBSD: scif.c,v 1.47 2006/07/23 22:06:06 ad Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Charles M. Hannum. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the NetBSD 47 * Foundation, Inc. and its contributors. 48 * 4. Neither the name of The NetBSD Foundation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 53 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 54 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * Copyright (c) 1991 The Regents of the University of California. 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. Neither the name of the University nor the names of its contributors 78 * may be used to endorse or promote products derived from this software 79 * without specific prior written permission. 80 * 81 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 82 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 83 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 84 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 85 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 86 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 87 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 88 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 89 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 90 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 91 * SUCH DAMAGE. 92 * 93 * @(#)com.c 7.5 (Berkeley) 5/16/91 94 */ 95 96 /* 97 * SH internal serial driver 98 * 99 * This code is derived from both z8530tty.c and com.c 100 */ 101 102 #include <sys/cdefs.h> 103 __KERNEL_RCSID(0, "$NetBSD: scif.c,v 1.47 2006/07/23 22:06:06 ad Exp $"); 104 105 #include "opt_kgdb.h" 106 #include "opt_scif.h" 107 108 #include <sys/param.h> 109 #include <sys/systm.h> 110 #include <sys/tty.h> 111 #include <sys/proc.h> 112 #include <sys/conf.h> 113 #include <sys/file.h> 114 #include <sys/syslog.h> 115 #include <sys/kernel.h> 116 #include <sys/device.h> 117 #include <sys/malloc.h> 118 #include <sys/kgdb.h> 119 #include <sys/kauth.h> 120 121 #include <dev/cons.h> 122 123 #include <sh3/clock.h> 124 #include <sh3/exception.h> 125 #include <sh3/scifreg.h> 126 #include <machine/intr.h> 127 128 #include <sh3/dev/scifvar.h> 129 130 #include "locators.h" 131 132 static void scifstart(struct tty *); 133 static int scifparam(struct tty *, struct termios *); 134 static int kgdb_attached; 135 136 void scifcnprobe(struct consdev *); 137 void scifcninit(struct consdev *); 138 void scifcnputc(dev_t, int); 139 int scifcngetc(dev_t); 140 void scifcnpoolc(dev_t, int); 141 void scif_intr_init(void); 142 int scifintr(void *); 143 144 struct scif_softc { 145 struct device sc_dev; /* boilerplate */ 146 struct tty *sc_tty; 147 void *sc_si; 148 149 struct callout sc_diag_ch; 150 151 #if 0 152 bus_space_tag_t sc_iot; /* ISA i/o space identifier */ 153 bus_space_handle_t sc_ioh; /* ISA io handle */ 154 155 int sc_drq; 156 157 int sc_frequency; 158 #endif 159 160 u_int sc_overflows, 161 sc_floods, 162 sc_errors; /* number of retries so far */ 163 u_char sc_status[7]; /* copy of registers */ 164 165 int sc_hwflags; 166 int sc_swflags; 167 u_int sc_fifolen; 168 169 u_int sc_r_hiwat, 170 sc_r_lowat; 171 u_char *volatile sc_rbget, 172 *volatile sc_rbput; 173 volatile u_int sc_rbavail; 174 u_char *sc_rbuf, 175 *sc_ebuf; 176 177 u_char *sc_tba; /* transmit buffer address */ 178 u_int sc_tbc, /* transmit byte count */ 179 sc_heldtbc; 180 181 volatile u_char sc_rx_flags, 182 #define RX_TTY_BLOCKED 0x01 183 #define RX_TTY_OVERFLOWED 0x02 184 #define RX_IBUF_BLOCKED 0x04 185 #define RX_IBUF_OVERFLOWED 0x08 186 #define RX_ANY_BLOCK 0x0f 187 sc_tx_busy, /* working on an output chunk */ 188 sc_tx_done, /* done with one output chunk */ 189 sc_tx_stopped, /* H/W level stop (lost CTS) */ 190 sc_st_check, /* got a status interrupt */ 191 sc_rx_ready; 192 193 volatile u_char sc_heldchange; 194 }; 195 196 /* controller driver configuration */ 197 static int scif_match(struct device *, struct cfdata *, void *); 198 static void scif_attach(struct device *, struct device *, void *); 199 200 void scif_break(struct scif_softc *, int); 201 void scif_iflush(struct scif_softc *); 202 203 #define integrate static inline 204 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 205 void scifsoft(void *); 206 #else 207 #ifndef __NO_SOFT_SERIAL_INTERRUPT 208 void scifsoft(void); 209 #else 210 void scifsoft(void *); 211 #endif 212 #endif 213 integrate void scif_rxsoft(struct scif_softc *, struct tty *); 214 integrate void scif_txsoft(struct scif_softc *, struct tty *); 215 integrate void scif_stsoft(struct scif_softc *, struct tty *); 216 integrate void scif_schedrx(struct scif_softc *); 217 void scifdiag(void *); 218 219 220 #define SCIFUNIT_MASK 0x7ffff 221 #define SCIFDIALOUT_MASK 0x80000 222 223 #define SCIFUNIT(x) (minor(x) & SCIFUNIT_MASK) 224 #define SCIFDIALOUT(x) (minor(x) & SCIFDIALOUT_MASK) 225 226 /* Hardware flag masks */ 227 #define SCIF_HW_NOIEN 0x01 228 #define SCIF_HW_FIFO 0x02 229 #define SCIF_HW_FLOW 0x08 230 #define SCIF_HW_DEV_OK 0x20 231 #define SCIF_HW_CONSOLE 0x40 232 #define SCIF_HW_KGDB 0x80 233 234 /* Buffer size for character buffer */ 235 #define SCIF_RING_SIZE 2048 236 237 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 238 u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4; 239 u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4; 240 241 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 242 int scifconscflag = CONMODE; 243 int scifisconsole = 0; 244 245 #ifdef SCIFCN_SPEED 246 unsigned int scifcn_speed = SCIFCN_SPEED; 247 #else 248 unsigned int scifcn_speed = 9600; 249 #endif 250 251 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 252 253 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 254 #ifdef __NO_SOFT_SERIAL_INTERRUPT 255 volatile int scif_softintr_scheduled; 256 struct callout scif_soft_ch = CALLOUT_INITIALIZER; 257 #endif 258 #endif 259 260 u_int scif_rbuf_size = SCIF_RING_SIZE; 261 262 CFATTACH_DECL(scif, sizeof(struct scif_softc), 263 scif_match, scif_attach, NULL, NULL); 264 265 extern struct cfdriver scif_cd; 266 267 static int scif_attached; 268 269 dev_type_open(scifopen); 270 dev_type_close(scifclose); 271 dev_type_read(scifread); 272 dev_type_write(scifwrite); 273 dev_type_ioctl(scifioctl); 274 dev_type_stop(scifstop); 275 dev_type_tty(sciftty); 276 dev_type_poll(scifpoll); 277 278 const struct cdevsw scif_cdevsw = { 279 scifopen, scifclose, scifread, scifwrite, scifioctl, 280 scifstop, sciftty, scifpoll, nommap, ttykqfilter, D_TTY 281 }; 282 283 void InitializeScif (unsigned int); 284 285 /* 286 * following functions are debugging prupose only 287 */ 288 #define CR 0x0D 289 #define USART_ON (unsigned int)~0x08 290 291 void scif_putc(unsigned char); 292 unsigned char scif_getc(void); 293 int ScifErrCheck(void); 294 295 296 /* XXX: uwe 297 * Prepare for bus_spacification. The difference in access widths is 298 * still handled by the magic definitions in scifreg.h 299 */ 300 #define scif_smr_read() SHREG_SCSMR2 301 #define scif_smr_write(v) (SHREG_SCSMR2 = (v)) 302 303 #define scif_brr_read() SHREG_SCBRR2 304 #define scif_brr_write(v) (SHREG_SCBRR2 = (v)) 305 306 #define scif_scr_read() SHREG_SCSCR2 307 #define scif_scr_write(v) (SHREG_SCSCR2 = (v)) 308 309 #define scif_ftdr_write(v) (SHREG_SCFTDR2 = (v)) 310 311 #define scif_ssr_read() SHREG_SCSSR2 312 #define scif_ssr_write(v) (SHREG_SCSSR2 = (v)) 313 314 #define scif_frdr_read() SHREG_SCFRDR2 315 316 #define scif_fcr_read() SHREG_SCFCR2 317 #define scif_fcr_write(v) (SHREG_SCFCR2 = (v)) 318 319 #define scif_fdr_read() SHREG_SCFDR2 320 321 #ifdef SH4 /* additional registers in sh4 */ 322 323 #define scif_sptr_read() SHREG_SCSPTR2 324 #define scif_sptr_write(v) (SHREG_SCSPTR2 = (v)) 325 326 #define scif_lsr_read() SHREG_SCLSR2 327 #define scif_lsr_write(v) (SHREG_SCLSR2 = (v)) 328 329 #endif /* SH4 */ 330 331 332 /* 333 * InitializeScif 334 * : unsigned int bps; 335 * : SCIF(Serial Communication Interface) 336 */ 337 338 void 339 InitializeScif(unsigned int bps) 340 { 341 342 /* Initialize SCR */ 343 scif_scr_write(0x00); 344 345 #if 0 346 scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE); 347 #else 348 scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST); 349 #endif 350 /* Serial Mode Register */ 351 scif_smr_write(0x00); /* 8bit,NonParity,Even,1Stop */ 352 353 /* Bit Rate Register */ 354 scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * bps) - 1); 355 356 /* 357 * wait 2m Sec, because Send/Recv must begin 1 bit period after 358 * BRR is set. 359 */ 360 delay(2000); 361 362 #if 0 363 scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE); 364 #else 365 scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1); 366 #endif 367 368 /* Send permission, Receive permission ON */ 369 scif_scr_write(SCSCR2_TE | SCSCR2_RE); 370 371 /* Serial Status Register */ 372 scif_ssr_write(scif_ssr_read() & SCSSR2_TDFE); /* Clear Status */ 373 } 374 375 376 /* 377 * scif_putc 378 * : unsigned char c; 379 */ 380 381 void 382 scif_putc(unsigned char c) 383 { 384 385 /* wait for ready */ 386 while ((scif_fdr_read() & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) 387 continue; 388 389 /* write send data to send register */ 390 scif_ftdr_write(c); 391 392 /* clear ready flag */ 393 scif_ssr_write(scif_ssr_read() & ~(SCSSR2_TDFE | SCSSR2_TEND)); 394 } 395 396 /* 397 * : ScifErrCheck 398 * 0x80 = error 399 * 0x08 = frame error 400 * 0x04 = parity error 401 */ 402 int 403 ScifErrCheck(void) 404 { 405 406 return (scif_ssr_read() & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)); 407 } 408 409 /* 410 * scif_getc 411 */ 412 unsigned char 413 scif_getc(void) 414 { 415 unsigned char c, err_c; 416 #ifdef SH4 417 unsigned short err_c2 = 0; /* XXXGCC: -Wuninitialized */ 418 #endif 419 420 for (;;) { 421 /* wait for ready */ 422 while ((scif_fdr_read() & SCFDR2_RECVCNT) == 0) 423 continue; 424 425 c = scif_frdr_read(); 426 err_c = scif_ssr_read(); 427 scif_ssr_write(scif_ssr_read() 428 & ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF | SCSSR2_DR)); 429 #ifdef SH4 430 if (CPU_IS_SH4) { 431 err_c2 = scif_lsr_read(); 432 scif_lsr_write(scif_lsr_read() & ~SCLSR2_ORER); 433 } 434 #endif 435 if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER 436 | SCSSR2_PER)) == 0) { 437 #ifdef SH4 438 if (CPU_IS_SH4 && ((err_c2 & SCLSR2_ORER) == 0)) 439 #endif 440 return(c); 441 } 442 } 443 444 } 445 446 static int 447 scif_match(struct device *parent, struct cfdata *cfp, void *aux) 448 { 449 450 if (strcmp(cfp->cf_name, "scif") || scif_attached) 451 return 0; 452 453 return 1; 454 } 455 456 static void 457 scif_attach(struct device *parent, struct device *self, void *aux) 458 { 459 struct scif_softc *sc = (struct scif_softc *)self; 460 struct tty *tp; 461 462 scif_attached = 1; 463 464 sc->sc_hwflags = 0; /* XXX */ 465 sc->sc_swflags = 0; /* XXX */ 466 sc->sc_fifolen = 16; 467 468 if (scifisconsole || kgdb_attached) { 469 /* InitializeScif(scifcn_speed); */ 470 SET(sc->sc_hwflags, SCIF_HW_CONSOLE); 471 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 472 if (kgdb_attached) { 473 SET(sc->sc_hwflags, SCIF_HW_KGDB); 474 printf("\n%s: kgdb\n", sc->sc_dev.dv_xname); 475 } else { 476 printf("\n%s: console\n", sc->sc_dev.dv_xname); 477 } 478 } else { 479 InitializeScif(9600); 480 printf("\n"); 481 } 482 483 callout_init(&sc->sc_diag_ch); 484 #ifdef SH4 485 intc_intr_establish(SH4_INTEVT_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 486 scifintr, sc); 487 intc_intr_establish(SH4_INTEVT_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 488 scifintr, sc); 489 intc_intr_establish(SH4_INTEVT_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 490 scifintr, sc); 491 intc_intr_establish(SH4_INTEVT_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 492 scifintr, sc); 493 #else 494 intc_intr_establish(SH7709_INTEVT2_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 495 scifintr, sc); 496 intc_intr_establish(SH7709_INTEVT2_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 497 scifintr, sc); 498 intc_intr_establish(SH7709_INTEVT2_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 499 scifintr, sc); 500 intc_intr_establish(SH7709_INTEVT2_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 501 scifintr, sc); 502 #endif 503 504 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 505 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, scifsoft, sc); 506 #endif 507 SET(sc->sc_hwflags, SCIF_HW_DEV_OK); 508 509 tp = ttymalloc(); 510 tp->t_oproc = scifstart; 511 tp->t_param = scifparam; 512 tp->t_hwiflow = NULL; 513 514 sc->sc_tty = tp; 515 sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 516 if (sc->sc_rbuf == NULL) { 517 printf("%s: unable to allocate ring buffer\n", 518 sc->sc_dev.dv_xname); 519 return; 520 } 521 sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1); 522 523 tty_attach(tp); 524 } 525 526 /* 527 * Start or restart transmission. 528 */ 529 static void 530 scifstart(struct tty *tp) 531 { 532 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 533 int s; 534 535 s = spltty(); 536 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 537 goto out; 538 if (sc->sc_tx_stopped) 539 goto out; 540 541 if (tp->t_outq.c_cc <= tp->t_lowat) { 542 if (ISSET(tp->t_state, TS_ASLEEP)) { 543 CLR(tp->t_state, TS_ASLEEP); 544 wakeup(&tp->t_outq); 545 } 546 selwakeup(&tp->t_wsel); 547 if (tp->t_outq.c_cc == 0) 548 goto out; 549 } 550 551 /* Grab the first contiguous region of buffer space. */ 552 { 553 u_char *tba; 554 int tbc; 555 556 tba = tp->t_outq.c_cf; 557 tbc = ndqb(&tp->t_outq, 0); 558 559 (void)splserial(); 560 561 sc->sc_tba = tba; 562 sc->sc_tbc = tbc; 563 } 564 565 SET(tp->t_state, TS_BUSY); 566 sc->sc_tx_busy = 1; 567 568 /* Enable transmit completion interrupts if necessary. */ 569 scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE); 570 571 /* Output the first chunk of the contiguous buffer. */ 572 { 573 int n; 574 int maxchars; 575 int i; 576 577 n = sc->sc_tbc; 578 maxchars = sc->sc_fifolen 579 - ((scif_fdr_read() & SCFDR2_TXCNT) >> 8); 580 if (n > maxchars) 581 n = maxchars; 582 583 for (i = 0; i < n; i++) { 584 scif_putc(*(sc->sc_tba)); 585 sc->sc_tba++; 586 } 587 sc->sc_tbc -= n; 588 } 589 out: 590 splx(s); 591 return; 592 } 593 594 /* 595 * Set SCIF tty parameters from termios. 596 * XXX - Should just copy the whole termios after 597 * making sure all the changes could be done. 598 */ 599 static int 600 scifparam(struct tty *tp, struct termios *t) 601 { 602 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 603 int ospeed = t->c_ospeed; 604 int s; 605 606 if (!device_is_active(&sc->sc_dev)) 607 return (EIO); 608 609 /* Check requested parameters. */ 610 if (ospeed < 0) 611 return (EINVAL); 612 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 613 return (EINVAL); 614 615 /* 616 * For the console, always force CLOCAL and !HUPCL, so that the port 617 * is always active. 618 */ 619 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 620 ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 621 SET(t->c_cflag, CLOCAL); 622 CLR(t->c_cflag, HUPCL); 623 } 624 625 /* 626 * If there were no changes, don't do anything. This avoids dropping 627 * input and improves performance when all we did was frob things like 628 * VMIN and VTIME. 629 */ 630 if (tp->t_ospeed == t->c_ospeed && 631 tp->t_cflag == t->c_cflag) 632 return (0); 633 634 #if 0 635 /* XXX (msaitoh) */ 636 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 637 #endif 638 639 s = splserial(); 640 641 /* 642 * Set the flow control pins depending on the current flow control 643 * mode. 644 */ 645 if (ISSET(t->c_cflag, CRTSCTS)) { 646 scif_fcr_write(scif_fcr_read() | SCFCR2_MCE); 647 } else { 648 scif_fcr_write(scif_fcr_read() & ~SCFCR2_MCE); 649 } 650 651 scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * ospeed) -1); 652 653 /* 654 * Set the FIFO threshold based on the receive speed. 655 * 656 * * If it's a low speed, it's probably a mouse or some other 657 * interactive device, so set the threshold low. 658 * * If it's a high speed, trim the trigger level down to prevent 659 * overflows. 660 * * Otherwise set it a bit higher. 661 */ 662 #if 0 663 /* XXX (msaitoh) */ 664 if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP)) 665 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 666 else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO)) 667 sc->sc_fifo = FIFO_ENABLE | 668 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : 669 t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4); 670 else 671 sc->sc_fifo = 0; 672 #endif 673 674 /* And copy to tty. */ 675 tp->t_ispeed = 0; 676 tp->t_ospeed = t->c_ospeed; 677 tp->t_cflag = t->c_cflag; 678 679 if (!sc->sc_heldchange) { 680 if (sc->sc_tx_busy) { 681 sc->sc_heldtbc = sc->sc_tbc; 682 sc->sc_tbc = 0; 683 sc->sc_heldchange = 1; 684 } 685 #if 0 686 /* XXX (msaitoh) */ 687 else 688 scif_loadchannelregs(sc); 689 #endif 690 } 691 692 if (!ISSET(t->c_cflag, CHWFLOW)) { 693 /* Disable the high water mark. */ 694 sc->sc_r_hiwat = 0; 695 sc->sc_r_lowat = 0; 696 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 697 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 698 scif_schedrx(sc); 699 } 700 } else { 701 sc->sc_r_hiwat = scif_rbuf_hiwat; 702 sc->sc_r_lowat = scif_rbuf_lowat; 703 } 704 705 splx(s); 706 707 #ifdef SCIF_DEBUG 708 if (scif_debug) 709 scifstatus(sc, "scifparam "); 710 #endif 711 712 if (!ISSET(t->c_cflag, CHWFLOW)) { 713 if (sc->sc_tx_stopped) { 714 sc->sc_tx_stopped = 0; 715 scifstart(tp); 716 } 717 } 718 719 return (0); 720 } 721 722 void 723 scif_iflush(struct scif_softc *sc) 724 { 725 int i; 726 unsigned char c; 727 728 i = scif_fdr_read() & SCFDR2_RECVCNT; 729 730 while (i > 0) { 731 c = scif_frdr_read(); 732 scif_ssr_write(scif_ssr_read() & ~(SCSSR2_RDF | SCSSR2_DR)); 733 i--; 734 } 735 } 736 737 int 738 scifopen(dev_t dev, int flag, int mode, struct lwp *l) 739 { 740 int unit = SCIFUNIT(dev); 741 struct scif_softc *sc; 742 struct tty *tp; 743 int s, s2; 744 int error; 745 746 if (unit >= scif_cd.cd_ndevs) 747 return (ENXIO); 748 sc = scif_cd.cd_devs[unit]; 749 if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) || 750 sc->sc_rbuf == NULL) 751 return (ENXIO); 752 753 if (!device_is_active(&sc->sc_dev)) 754 return (ENXIO); 755 756 #ifdef KGDB 757 /* 758 * If this is the kgdb port, no other use is permitted. 759 */ 760 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) 761 return (EBUSY); 762 #endif /* KGDB */ 763 764 tp = sc->sc_tty; 765 766 if (ISSET(tp->t_state, TS_ISOPEN) && 767 ISSET(tp->t_state, TS_XCLUDE) && 768 kauth_authorize_generic(l->l_cred, 769 KAUTH_GENERIC_ISSUSER, &l->l_acflag) != 0) 770 return (EBUSY); 771 772 s = spltty(); 773 774 /* 775 * Do the following iff this is a first open. 776 */ 777 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 778 struct termios t; 779 780 tp->t_dev = dev; 781 782 s2 = splserial(); 783 784 /* Turn on interrupts. */ 785 scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE); 786 787 splx(s2); 788 789 /* 790 * Initialize the termios status to the defaults. Add in the 791 * sticky bits from TIOCSFLAGS. 792 */ 793 t.c_ispeed = 0; 794 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 795 t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */ 796 t.c_cflag = scifconscflag; 797 } else { 798 t.c_ospeed = TTYDEF_SPEED; 799 t.c_cflag = TTYDEF_CFLAG; 800 } 801 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 802 SET(t.c_cflag, CLOCAL); 803 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 804 SET(t.c_cflag, CRTSCTS); 805 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 806 SET(t.c_cflag, MDMBUF); 807 /* Make sure scifparam() will do something. */ 808 tp->t_ospeed = 0; 809 (void) scifparam(tp, &t); 810 tp->t_iflag = TTYDEF_IFLAG; 811 tp->t_oflag = TTYDEF_OFLAG; 812 tp->t_lflag = TTYDEF_LFLAG; 813 ttychars(tp); 814 ttsetwater(tp); 815 816 s2 = splserial(); 817 818 /* Clear the input ring, and unblock. */ 819 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 820 sc->sc_rbavail = scif_rbuf_size; 821 scif_iflush(sc); 822 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 823 #if 0 824 /* XXX (msaitoh) */ 825 scif_hwiflow(sc); 826 #endif 827 828 #ifdef SCIF_DEBUG 829 if (scif_debug) 830 scifstatus(sc, "scifopen "); 831 #endif 832 833 splx(s2); 834 } 835 836 splx(s); 837 838 error = ttyopen(tp, SCIFDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 839 if (error) 840 goto bad; 841 842 error = (*tp->t_linesw->l_open)(dev, tp); 843 if (error) 844 goto bad; 845 846 return (0); 847 848 bad: 849 850 return (error); 851 } 852 853 int 854 scifclose(dev_t dev, int flag, int mode, struct lwp *l) 855 { 856 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 857 struct tty *tp = sc->sc_tty; 858 859 /* XXX This is for cons.c. */ 860 if (!ISSET(tp->t_state, TS_ISOPEN)) 861 return (0); 862 863 (*tp->t_linesw->l_close)(tp, flag); 864 ttyclose(tp); 865 866 if (!device_is_active(&sc->sc_dev)) 867 return (0); 868 869 return (0); 870 } 871 872 int 873 scifread(dev_t dev, struct uio *uio, int flag) 874 { 875 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 876 struct tty *tp = sc->sc_tty; 877 878 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 879 } 880 881 int 882 scifwrite(dev_t dev, struct uio *uio, int flag) 883 { 884 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 885 struct tty *tp = sc->sc_tty; 886 887 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 888 } 889 890 int 891 scifpoll(dev_t dev, int events, struct lwp *l) 892 { 893 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 894 struct tty *tp = sc->sc_tty; 895 896 return ((*tp->t_linesw->l_poll)(tp, events, l)); 897 } 898 899 struct tty * 900 sciftty(dev_t dev) 901 { 902 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 903 struct tty *tp = sc->sc_tty; 904 905 return (tp); 906 } 907 908 int 909 scifioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct lwp *l) 910 { 911 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 912 struct tty *tp = sc->sc_tty; 913 int error; 914 int s; 915 916 if (!device_is_active(&sc->sc_dev)) 917 return (EIO); 918 919 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 920 if (error != EPASSTHROUGH) 921 return (error); 922 923 error = ttioctl(tp, cmd, data, flag, l); 924 if (error != EPASSTHROUGH) 925 return (error); 926 927 error = 0; 928 929 s = splserial(); 930 931 switch (cmd) { 932 case TIOCSBRK: 933 scif_break(sc, 1); 934 break; 935 936 case TIOCCBRK: 937 scif_break(sc, 0); 938 break; 939 940 case TIOCGFLAGS: 941 *(int *)data = sc->sc_swflags; 942 break; 943 944 case TIOCSFLAGS: 945 error = kauth_authorize_generic(l->l_cred, 946 KAUTH_GENERIC_ISSUSER, &l->l_acflag); 947 if (error) 948 break; 949 sc->sc_swflags = *(int *)data; 950 break; 951 952 default: 953 error = EPASSTHROUGH; 954 break; 955 } 956 957 splx(s); 958 959 return (error); 960 } 961 962 integrate void 963 scif_schedrx(struct scif_softc *sc) 964 { 965 966 sc->sc_rx_ready = 1; 967 968 /* Wake up the poller. */ 969 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 970 softintr_schedule(sc->sc_si); 971 #else 972 #ifndef __NO_SOFT_SERIAL_INTERRUPT 973 setsoftserial(); 974 #else 975 if (!scif_softintr_scheduled) { 976 scif_softintr_scheduled = 1; 977 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 978 } 979 #endif 980 #endif 981 } 982 983 void 984 scif_break(struct scif_softc *sc, int onoff) 985 { 986 987 if (onoff) 988 scif_ssr_write(scif_ssr_read() & ~SCSSR2_TDFE); 989 else 990 scif_ssr_write(scif_ssr_read() | SCSSR2_TDFE); 991 992 #if 0 /* XXX */ 993 if (!sc->sc_heldchange) { 994 if (sc->sc_tx_busy) { 995 sc->sc_heldtbc = sc->sc_tbc; 996 sc->sc_tbc = 0; 997 sc->sc_heldchange = 1; 998 } else 999 scif_loadchannelregs(sc); 1000 } 1001 #endif 1002 } 1003 1004 /* 1005 * Stop output, e.g., for ^S or output flush. 1006 */ 1007 void 1008 scifstop(struct tty *tp, int flag) 1009 { 1010 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 1011 int s; 1012 1013 s = splserial(); 1014 if (ISSET(tp->t_state, TS_BUSY)) { 1015 /* Stop transmitting at the next chunk. */ 1016 sc->sc_tbc = 0; 1017 sc->sc_heldtbc = 0; 1018 if (!ISSET(tp->t_state, TS_TTSTOP)) 1019 SET(tp->t_state, TS_FLUSH); 1020 } 1021 splx(s); 1022 } 1023 1024 void 1025 scif_intr_init() 1026 { 1027 /* XXX */ 1028 } 1029 1030 void 1031 scifdiag(void *arg) 1032 { 1033 struct scif_softc *sc = arg; 1034 int overflows, floods; 1035 int s; 1036 1037 s = splserial(); 1038 overflows = sc->sc_overflows; 1039 sc->sc_overflows = 0; 1040 floods = sc->sc_floods; 1041 sc->sc_floods = 0; 1042 sc->sc_errors = 0; 1043 splx(s); 1044 1045 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1046 sc->sc_dev.dv_xname, 1047 overflows, overflows == 1 ? "" : "s", 1048 floods, floods == 1 ? "" : "s"); 1049 } 1050 1051 integrate void 1052 scif_rxsoft(struct scif_softc *sc, struct tty *tp) 1053 { 1054 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1055 u_char *get, *end; 1056 u_int cc, scc; 1057 u_char ssr2; 1058 int code; 1059 int s; 1060 1061 end = sc->sc_ebuf; 1062 get = sc->sc_rbget; 1063 scc = cc = scif_rbuf_size - sc->sc_rbavail; 1064 1065 if (cc == scif_rbuf_size) { 1066 sc->sc_floods++; 1067 if (sc->sc_errors++ == 0) 1068 callout_reset(&sc->sc_diag_ch, 60 * hz, scifdiag, sc); 1069 } 1070 1071 while (cc) { 1072 code = get[0]; 1073 ssr2 = get[1]; 1074 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) { 1075 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER)) 1076 SET(code, TTY_FE); 1077 if (ISSET(ssr2, SCSSR2_PER)) 1078 SET(code, TTY_PE); 1079 } 1080 if ((*rint)(code, tp) == -1) { 1081 /* 1082 * The line discipline's buffer is out of space. 1083 */ 1084 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1085 /* 1086 * We're either not using flow control, or the 1087 * line discipline didn't tell us to block for 1088 * some reason. Either way, we have no way to 1089 * know when there's more space available, so 1090 * just drop the rest of the data. 1091 */ 1092 get += cc << 1; 1093 if (get >= end) 1094 get -= scif_rbuf_size << 1; 1095 cc = 0; 1096 } else { 1097 /* 1098 * Don't schedule any more receive processing 1099 * until the line discipline tells us there's 1100 * space available (through scifhwiflow()). 1101 * Leave the rest of the data in the input 1102 * buffer. 1103 */ 1104 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1105 } 1106 break; 1107 } 1108 get += 2; 1109 if (get >= end) 1110 get = sc->sc_rbuf; 1111 cc--; 1112 } 1113 1114 if (cc != scc) { 1115 sc->sc_rbget = get; 1116 s = splserial(); 1117 cc = sc->sc_rbavail += scc - cc; 1118 /* Buffers should be ok again, release possible block. */ 1119 if (cc >= sc->sc_r_lowat) { 1120 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1121 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1122 scif_scr_write(scif_scr_read() | SCSCR2_RIE); 1123 } 1124 #if 0 1125 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1126 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1127 scif_hwiflow(sc); 1128 } 1129 #endif 1130 } 1131 splx(s); 1132 } 1133 } 1134 1135 integrate void 1136 scif_txsoft(struct scif_softc *sc, struct tty *tp) 1137 { 1138 1139 CLR(tp->t_state, TS_BUSY); 1140 if (ISSET(tp->t_state, TS_FLUSH)) 1141 CLR(tp->t_state, TS_FLUSH); 1142 else 1143 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1144 (*tp->t_linesw->l_start)(tp); 1145 } 1146 1147 integrate void 1148 scif_stsoft(struct scif_softc *sc, struct tty *tp) 1149 { 1150 #if 0 1151 /* XXX (msaitoh) */ 1152 u_char msr, delta; 1153 int s; 1154 1155 s = splserial(); 1156 msr = sc->sc_msr; 1157 delta = sc->sc_msr_delta; 1158 sc->sc_msr_delta = 0; 1159 splx(s); 1160 1161 if (ISSET(delta, sc->sc_msr_dcd)) { 1162 /* 1163 * Inform the tty layer that carrier detect changed. 1164 */ 1165 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1166 } 1167 1168 if (ISSET(delta, sc->sc_msr_cts)) { 1169 /* Block or unblock output according to flow control. */ 1170 if (ISSET(msr, sc->sc_msr_cts)) { 1171 sc->sc_tx_stopped = 0; 1172 (*tp->t_linesw->l_start)(tp); 1173 } else { 1174 sc->sc_tx_stopped = 1; 1175 } 1176 } 1177 1178 #ifdef SCIF_DEBUG 1179 if (scif_debug) 1180 scifstatus(sc, "scif_stsoft"); 1181 #endif 1182 #endif 1183 } 1184 1185 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1186 void 1187 scifsoft(void *arg) 1188 { 1189 struct scif_softc *sc = arg; 1190 struct tty *tp; 1191 1192 if (!device_is_active(&sc->sc_dev)) 1193 return; 1194 1195 { 1196 #else 1197 void 1198 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1199 scifsoft() 1200 #else 1201 scifsoft(void *arg) 1202 #endif 1203 { 1204 struct scif_softc *sc; 1205 struct tty *tp; 1206 int unit; 1207 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1208 int s; 1209 1210 s = splsoftserial(); 1211 scif_softintr_scheduled = 0; 1212 #endif 1213 1214 for (unit = 0; unit < scif_cd.cd_ndevs; unit++) { 1215 sc = scif_cd.cd_devs[unit]; 1216 if (sc == NULL || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK)) 1217 continue; 1218 1219 if (!device_is_active(&sc->sc_dev)) 1220 continue; 1221 1222 tp = sc->sc_tty; 1223 if (tp == NULL) 1224 continue; 1225 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 1226 continue; 1227 #endif 1228 tp = sc->sc_tty; 1229 1230 if (sc->sc_rx_ready) { 1231 sc->sc_rx_ready = 0; 1232 scif_rxsoft(sc, tp); 1233 } 1234 1235 #if 0 1236 if (sc->sc_st_check) { 1237 sc->sc_st_check = 0; 1238 scif_stsoft(sc, tp); 1239 } 1240 #endif 1241 1242 if (sc->sc_tx_done) { 1243 sc->sc_tx_done = 0; 1244 scif_txsoft(sc, tp); 1245 } 1246 } 1247 1248 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1249 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1250 splx(s); 1251 #endif 1252 #endif 1253 } 1254 1255 int 1256 scifintr(void *arg) 1257 { 1258 struct scif_softc *sc = arg; 1259 u_char *put, *end; 1260 u_int cc; 1261 u_short ssr2; 1262 int count; 1263 1264 if (!device_is_active(&sc->sc_dev)) 1265 return (0); 1266 1267 end = sc->sc_ebuf; 1268 put = sc->sc_rbput; 1269 cc = sc->sc_rbavail; 1270 1271 do { 1272 ssr2 = scif_ssr_read(); 1273 if (ISSET(ssr2, SCSSR2_BRK)) { 1274 scif_ssr_write(scif_ssr_read() 1275 & ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR)); 1276 #ifdef DDB 1277 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 1278 console_debugger(); 1279 } 1280 #endif /* DDB */ 1281 #ifdef KGDB 1282 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) { 1283 kgdb_connect(1); 1284 } 1285 #endif /* KGDB */ 1286 } 1287 count = scif_fdr_read() & SCFDR2_RECVCNT; 1288 if (count != 0) { 1289 for (;;) { 1290 u_char c = scif_frdr_read(); 1291 u_char err = (u_char)(scif_ssr_read() & 0x00ff); 1292 1293 scif_ssr_write(scif_ssr_read() 1294 & ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR)); 1295 #ifdef SH4 1296 if (CPU_IS_SH4) 1297 scif_lsr_write(scif_lsr_read() 1298 & ~SCLSR2_ORER); 1299 #endif 1300 if ((cc > 0) && (count > 0)) { 1301 put[0] = c; 1302 put[1] = err; 1303 put += 2; 1304 if (put >= end) 1305 put = sc->sc_rbuf; 1306 cc--; 1307 count--; 1308 } else 1309 break; 1310 } 1311 1312 /* 1313 * Current string of incoming characters ended because 1314 * no more data was available or we ran out of space. 1315 * Schedule a receive event if any data was received. 1316 * If we're out of space, turn off receive interrupts. 1317 */ 1318 sc->sc_rbput = put; 1319 sc->sc_rbavail = cc; 1320 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1321 sc->sc_rx_ready = 1; 1322 1323 /* 1324 * See if we are in danger of overflowing a buffer. If 1325 * so, use hardware flow control to ease the pressure. 1326 */ 1327 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1328 cc < sc->sc_r_hiwat) { 1329 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1330 #if 0 1331 scif_hwiflow(sc); 1332 #endif 1333 } 1334 1335 /* 1336 * If we're out of space, disable receive interrupts 1337 * until the queue has drained a bit. 1338 */ 1339 if (!cc) { 1340 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1341 scif_scr_write(scif_scr_read() & ~SCSCR2_RIE); 1342 } 1343 } else { 1344 if (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR)) { 1345 scif_scr_write(scif_scr_read() 1346 & ~(SCSCR2_TIE | SCSCR2_RIE)); 1347 delay(10); 1348 scif_scr_write(scif_scr_read() 1349 | SCSCR2_TIE | SCSCR2_RIE); 1350 continue; 1351 } 1352 } 1353 } while (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR)); 1354 1355 #if 0 1356 msr = bus_space_read_1(iot, ioh, scif_msr); 1357 delta = msr ^ sc->sc_msr; 1358 sc->sc_msr = msr; 1359 if (ISSET(delta, sc->sc_msr_mask)) { 1360 SET(sc->sc_msr_delta, delta); 1361 1362 /* 1363 * Pulse-per-second clock signal on edge of DCD? 1364 */ 1365 if (ISSET(delta, sc->sc_ppsmask)) { 1366 struct timeval tv; 1367 if (ISSET(msr, sc->sc_ppsmask) == 1368 sc->sc_ppsassert) { 1369 /* XXX nanotime() */ 1370 microtime(&tv); 1371 TIMEVAL_TO_TIMESPEC(&tv, 1372 &sc->ppsinfo.assert_timestamp); 1373 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 1374 timespecadd(&sc->ppsinfo.assert_timestamp, 1375 &sc->ppsparam.assert_offset, 1376 &sc->ppsinfo.assert_timestamp); 1377 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp); 1378 } 1379 1380 #ifdef PPS_SYNC 1381 if (sc->ppsparam.mode & PPS_HARDPPSONASSERT) 1382 hardpps(&tv, tv.tv_usec); 1383 #endif 1384 sc->ppsinfo.assert_sequence++; 1385 sc->ppsinfo.current_mode = 1386 sc->ppsparam.mode; 1387 1388 } else if (ISSET(msr, sc->sc_ppsmask) == 1389 sc->sc_ppsclear) { 1390 /* XXX nanotime() */ 1391 microtime(&tv); 1392 TIMEVAL_TO_TIMESPEC(&tv, 1393 &sc->ppsinfo.clear_timestamp); 1394 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 1395 timespecadd(&sc->ppsinfo.clear_timestamp, 1396 &sc->ppsparam.clear_offset, 1397 &sc->ppsinfo.clear_timestamp); 1398 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp); 1399 } 1400 1401 #ifdef PPS_SYNC 1402 if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR) 1403 hardpps(&tv, tv.tv_usec); 1404 #endif 1405 sc->ppsinfo.clear_sequence++; 1406 sc->ppsinfo.current_mode = 1407 sc->ppsparam.mode; 1408 } 1409 } 1410 1411 /* 1412 * Stop output immediately if we lose the output 1413 * flow control signal or carrier detect. 1414 */ 1415 if (ISSET(~msr, sc->sc_msr_mask)) { 1416 sc->sc_tbc = 0; 1417 sc->sc_heldtbc = 0; 1418 #ifdef SCIF_DEBUG 1419 if (scif_debug) 1420 scifstatus(sc, "scifintr "); 1421 #endif 1422 } 1423 1424 sc->sc_st_check = 1; 1425 } 1426 #endif 1427 1428 /* 1429 * Done handling any receive interrupts. See if data can be 1430 * transmitted as well. Schedule tx done event if no data left 1431 * and tty was marked busy. 1432 */ 1433 if (((scif_fdr_read() & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */ 1434 /* 1435 * If we've delayed a parameter change, do it now, and restart 1436 * output. 1437 */ 1438 if (sc->sc_heldchange) { 1439 sc->sc_heldchange = 0; 1440 sc->sc_tbc = sc->sc_heldtbc; 1441 sc->sc_heldtbc = 0; 1442 } 1443 1444 /* Output the next chunk of the contiguous buffer, if any. */ 1445 if (sc->sc_tbc > 0) { 1446 int n; 1447 int maxchars; 1448 int i; 1449 1450 n = sc->sc_tbc; 1451 maxchars = sc->sc_fifolen - 1452 ((scif_fdr_read() & SCFDR2_TXCNT) >> 8); 1453 if (n > maxchars) 1454 n = maxchars; 1455 1456 for (i = 0; i < n; i++) { 1457 scif_putc(*(sc->sc_tba)); 1458 sc->sc_tba++; 1459 } 1460 sc->sc_tbc -= n; 1461 } else { 1462 /* Disable transmit completion interrupts if necessary. */ 1463 #if 0 1464 if (ISSET(sc->sc_ier, IER_ETXRDY)) 1465 #endif 1466 scif_scr_write(scif_scr_read() & ~SCSCR2_TIE); 1467 1468 if (sc->sc_tx_busy) { 1469 sc->sc_tx_busy = 0; 1470 sc->sc_tx_done = 1; 1471 } 1472 } 1473 } 1474 1475 /* Wake up the poller. */ 1476 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1477 softintr_schedule(sc->sc_si); 1478 #else 1479 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1480 setsoftserial(); 1481 #else 1482 if (!scif_softintr_scheduled) { 1483 scif_softintr_scheduled = 1; 1484 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 1485 } 1486 #endif 1487 #endif 1488 1489 #if NRND > 0 && defined(RND_SCIF) 1490 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1491 #endif 1492 1493 return (1); 1494 } 1495 1496 void 1497 scifcnprobe(struct consdev *cp) 1498 { 1499 int maj; 1500 1501 /* locate the major number */ 1502 maj = cdevsw_lookup_major(&scif_cdevsw); 1503 1504 /* Initialize required fields. */ 1505 cp->cn_dev = makedev(maj, 0); 1506 #ifdef SCIFCONSOLE 1507 cp->cn_pri = CN_REMOTE; 1508 #else 1509 cp->cn_pri = CN_NORMAL; 1510 #endif 1511 } 1512 1513 void 1514 scifcninit(struct consdev *cp) 1515 { 1516 1517 InitializeScif(scifcn_speed); 1518 scifisconsole = 1; 1519 } 1520 1521 int 1522 scifcngetc(dev_t dev) 1523 { 1524 int c; 1525 int s; 1526 1527 s = splserial(); 1528 c = scif_getc(); 1529 splx(s); 1530 1531 return (c); 1532 } 1533 1534 void 1535 scifcnputc(dev_t dev, int c) 1536 { 1537 int s; 1538 1539 s = splserial(); 1540 scif_putc((u_char)c); 1541 splx(s); 1542 } 1543 1544 #ifdef KGDB 1545 int 1546 scif_kgdb_init() 1547 { 1548 1549 if (strcmp(kgdb_devname, "scif") != 0) 1550 return (1); 1551 1552 if (scifisconsole) 1553 return (1); /* can't share with console */ 1554 1555 InitializeScif(kgdb_rate); 1556 1557 kgdb_attach((int (*)(void *))scifcngetc, 1558 (void (*)(void *, int))scifcnputc, NULL); 1559 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 1560 kgdb_attached = 1; 1561 1562 return (0); 1563 } 1564 #endif /* KGDB */ 1565
Indexes created Fri Sep 26 08:10:20 GMT 2025