scif.c revision 1.50
1 /* $NetBSD: scif.c,v 1.50 2007/03/04 06:00:40 christos Exp $ */ 2 3 /*- 4 * Copyright (C) 1999 T.Horiuchi and SAITOH Masanobu. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /*- 30 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 31 * All rights reserved. 32 * 33 * This code is derived from software contributed to The NetBSD Foundation 34 * by Charles M. Hannum. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions 38 * are met: 39 * 1. Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 2. Redistributions in binary form must reproduce the above copyright 42 * notice, this list of conditions and the following disclaimer in the 43 * documentation and/or other materials provided with the distribution. 44 * 3. All advertising materials mentioning features or use of this software 45 * must display the following acknowledgement: 46 * This product includes software developed by the NetBSD 47 * Foundation, Inc. and its contributors. 48 * 4. Neither the name of The NetBSD Foundation nor the names of its 49 * contributors may be used to endorse or promote products derived 50 * from this software without specific prior written permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 53 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 54 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 55 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 56 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 57 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 58 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 59 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 60 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 61 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 62 * POSSIBILITY OF SUCH DAMAGE. 63 */ 64 65 /* 66 * Copyright (c) 1991 The Regents of the University of California. 67 * All rights reserved. 68 * 69 * Redistribution and use in source and binary forms, with or without 70 * modification, are permitted provided that the following conditions 71 * are met: 72 * 1. Redistributions of source code must retain the above copyright 73 * notice, this list of conditions and the following disclaimer. 74 * 2. Redistributions in binary form must reproduce the above copyright 75 * notice, this list of conditions and the following disclaimer in the 76 * documentation and/or other materials provided with the distribution. 77 * 3. Neither the name of the University nor the names of its contributors 78 * may be used to endorse or promote products derived from this software 79 * without specific prior written permission. 80 * 81 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 82 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 83 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 84 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 85 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 86 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 87 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 88 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 89 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 90 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 91 * SUCH DAMAGE. 92 * 93 * @(#)com.c 7.5 (Berkeley) 5/16/91 94 */ 95 96 /* 97 * SH internal serial driver 98 * 99 * This code is derived from both z8530tty.c and com.c 100 */ 101 102 #include <sys/cdefs.h> 103 __KERNEL_RCSID(0, "$NetBSD: scif.c,v 1.50 2007/03/04 06:00:40 christos Exp $"); 104 105 #include "opt_kgdb.h" 106 #include "opt_scif.h" 107 108 #include <sys/param.h> 109 #include <sys/systm.h> 110 #include <sys/tty.h> 111 #include <sys/proc.h> 112 #include <sys/conf.h> 113 #include <sys/file.h> 114 #include <sys/syslog.h> 115 #include <sys/kernel.h> 116 #include <sys/device.h> 117 #include <sys/malloc.h> 118 #include <sys/kgdb.h> 119 #include <sys/kauth.h> 120 121 #include <dev/cons.h> 122 123 #include <sh3/clock.h> 124 #include <sh3/exception.h> 125 #include <sh3/scifreg.h> 126 #include <machine/intr.h> 127 128 #include <sh3/dev/scifvar.h> 129 130 #include "locators.h" 131 132 static void scifstart(struct tty *); 133 static int scifparam(struct tty *, struct termios *); 134 static int kgdb_attached; 135 136 void scifcnprobe(struct consdev *); 137 void scifcninit(struct consdev *); 138 void scifcnputc(dev_t, int); 139 int scifcngetc(dev_t); 140 void scifcnpoolc(dev_t, int); 141 void scif_intr_init(void); 142 int scifintr(void *); 143 144 struct scif_softc { 145 struct device sc_dev; /* boilerplate */ 146 struct tty *sc_tty; 147 void *sc_si; 148 149 struct callout sc_diag_ch; 150 151 #if 0 152 bus_space_tag_t sc_iot; /* ISA i/o space identifier */ 153 bus_space_handle_t sc_ioh; /* ISA io handle */ 154 155 int sc_drq; 156 157 int sc_frequency; 158 #endif 159 160 u_int sc_overflows, 161 sc_floods, 162 sc_errors; /* number of retries so far */ 163 u_char sc_status[7]; /* copy of registers */ 164 165 int sc_hwflags; 166 int sc_swflags; 167 u_int sc_fifolen; 168 169 u_int sc_r_hiwat, 170 sc_r_lowat; 171 u_char *volatile sc_rbget, 172 *volatile sc_rbput; 173 volatile u_int sc_rbavail; 174 u_char *sc_rbuf, 175 *sc_ebuf; 176 177 u_char *sc_tba; /* transmit buffer address */ 178 u_int sc_tbc, /* transmit byte count */ 179 sc_heldtbc; 180 181 volatile u_char sc_rx_flags, 182 #define RX_TTY_BLOCKED 0x01 183 #define RX_TTY_OVERFLOWED 0x02 184 #define RX_IBUF_BLOCKED 0x04 185 #define RX_IBUF_OVERFLOWED 0x08 186 #define RX_ANY_BLOCK 0x0f 187 sc_tx_busy, /* working on an output chunk */ 188 sc_tx_done, /* done with one output chunk */ 189 sc_tx_stopped, /* H/W level stop (lost CTS) */ 190 sc_st_check, /* got a status interrupt */ 191 sc_rx_ready; 192 193 volatile u_char sc_heldchange; 194 }; 195 196 /* controller driver configuration */ 197 static int scif_match(struct device *, struct cfdata *, void *); 198 static void scif_attach(struct device *, struct device *, void *); 199 200 void scif_break(struct scif_softc *, int); 201 void scif_iflush(struct scif_softc *); 202 203 #define integrate static inline 204 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 205 void scifsoft(void *); 206 #else 207 #ifndef __NO_SOFT_SERIAL_INTERRUPT 208 void scifsoft(void); 209 #else 210 void scifsoft(void *); 211 #endif 212 #endif 213 integrate void scif_rxsoft(struct scif_softc *, struct tty *); 214 integrate void scif_txsoft(struct scif_softc *, struct tty *); 215 integrate void scif_stsoft(struct scif_softc *, struct tty *); 216 integrate void scif_schedrx(struct scif_softc *); 217 void scifdiag(void *); 218 219 220 #define SCIFUNIT_MASK 0x7ffff 221 #define SCIFDIALOUT_MASK 0x80000 222 223 #define SCIFUNIT(x) (minor(x) & SCIFUNIT_MASK) 224 #define SCIFDIALOUT(x) (minor(x) & SCIFDIALOUT_MASK) 225 226 /* Hardware flag masks */ 227 #define SCIF_HW_NOIEN 0x01 228 #define SCIF_HW_FIFO 0x02 229 #define SCIF_HW_FLOW 0x08 230 #define SCIF_HW_DEV_OK 0x20 231 #define SCIF_HW_CONSOLE 0x40 232 #define SCIF_HW_KGDB 0x80 233 234 /* Buffer size for character buffer */ 235 #define SCIF_RING_SIZE 2048 236 237 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */ 238 u_int scif_rbuf_hiwat = (SCIF_RING_SIZE * 1) / 4; 239 u_int scif_rbuf_lowat = (SCIF_RING_SIZE * 3) / 4; 240 241 #define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */ 242 int scifconscflag = CONMODE; 243 int scifisconsole = 0; 244 245 #ifdef SCIFCN_SPEED 246 unsigned int scifcn_speed = SCIFCN_SPEED; 247 #else 248 unsigned int scifcn_speed = 9600; 249 #endif 250 251 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */ 252 253 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 254 #ifdef __NO_SOFT_SERIAL_INTERRUPT 255 volatile int scif_softintr_scheduled; 256 struct callout scif_soft_ch = CALLOUT_INITIALIZER; 257 #endif 258 #endif 259 260 u_int scif_rbuf_size = SCIF_RING_SIZE; 261 262 CFATTACH_DECL(scif, sizeof(struct scif_softc), 263 scif_match, scif_attach, NULL, NULL); 264 265 extern struct cfdriver scif_cd; 266 267 static int scif_attached; 268 269 dev_type_open(scifopen); 270 dev_type_close(scifclose); 271 dev_type_read(scifread); 272 dev_type_write(scifwrite); 273 dev_type_ioctl(scifioctl); 274 dev_type_stop(scifstop); 275 dev_type_tty(sciftty); 276 dev_type_poll(scifpoll); 277 278 const struct cdevsw scif_cdevsw = { 279 scifopen, scifclose, scifread, scifwrite, scifioctl, 280 scifstop, sciftty, scifpoll, nommap, ttykqfilter, D_TTY 281 }; 282 283 void InitializeScif (unsigned int); 284 285 /* 286 * following functions are debugging prupose only 287 */ 288 #define CR 0x0D 289 #define USART_ON (unsigned int)~0x08 290 291 void scif_putc(unsigned char); 292 unsigned char scif_getc(void); 293 int ScifErrCheck(void); 294 295 296 /* XXX: uwe 297 * Prepare for bus_spacification. The difference in access widths is 298 * still handled by the magic definitions in scifreg.h 299 */ 300 #define scif_smr_read() SHREG_SCSMR2 301 #define scif_smr_write(v) (SHREG_SCSMR2 = (v)) 302 303 #define scif_brr_read() SHREG_SCBRR2 304 #define scif_brr_write(v) (SHREG_SCBRR2 = (v)) 305 306 #define scif_scr_read() SHREG_SCSCR2 307 #define scif_scr_write(v) (SHREG_SCSCR2 = (v)) 308 309 #define scif_ftdr_write(v) (SHREG_SCFTDR2 = (v)) 310 311 #define scif_ssr_read() SHREG_SCSSR2 312 #define scif_ssr_write(v) (SHREG_SCSSR2 = (v)) 313 314 #define scif_frdr_read() SHREG_SCFRDR2 315 316 #define scif_fcr_read() SHREG_SCFCR2 317 #define scif_fcr_write(v) (SHREG_SCFCR2 = (v)) 318 319 #define scif_fdr_read() SHREG_SCFDR2 320 321 #ifdef SH4 /* additional registers in sh4 */ 322 323 #define scif_sptr_read() SHREG_SCSPTR2 324 #define scif_sptr_write(v) (SHREG_SCSPTR2 = (v)) 325 326 #define scif_lsr_read() SHREG_SCLSR2 327 #define scif_lsr_write(v) (SHREG_SCLSR2 = (v)) 328 329 #endif /* SH4 */ 330 331 332 /* 333 * InitializeScif 334 * : unsigned int bps; 335 * : SCIF(Serial Communication Interface) 336 */ 337 338 void 339 InitializeScif(unsigned int bps) 340 { 341 342 /* Initialize SCR */ 343 scif_scr_write(0x00); 344 345 #if 0 346 scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST | SCFCR2_MCE); 347 #else 348 scif_fcr_write(SCFCR2_TFRST | SCFCR2_RFRST); 349 #endif 350 /* Serial Mode Register */ 351 scif_smr_write(0x00); /* 8bit,NonParity,Even,1Stop */ 352 353 /* Bit Rate Register */ 354 scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * bps) - 1); 355 356 /* 357 * wait 2m Sec, because Send/Recv must begin 1 bit period after 358 * BRR is set. 359 */ 360 delay(2000); 361 362 #if 0 363 scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1 | SCFCR2_MCE); 364 #else 365 scif_fcr_write(FIFO_RCV_TRIGGER_14 | FIFO_XMT_TRIGGER_1); 366 #endif 367 368 /* Send permission, Receive permission ON */ 369 scif_scr_write(SCSCR2_TE | SCSCR2_RE); 370 371 /* Serial Status Register */ 372 scif_ssr_write(scif_ssr_read() & SCSSR2_TDFE); /* Clear Status */ 373 } 374 375 376 /* 377 * scif_putc 378 * : unsigned char c; 379 */ 380 381 void 382 scif_putc(unsigned char c) 383 { 384 385 /* wait for ready */ 386 while ((scif_fdr_read() & SCFDR2_TXCNT) == SCFDR2_TXF_FULL) 387 continue; 388 389 /* write send data to send register */ 390 scif_ftdr_write(c); 391 392 /* clear ready flag */ 393 scif_ssr_write(scif_ssr_read() & ~(SCSSR2_TDFE | SCSSR2_TEND)); 394 } 395 396 /* 397 * : ScifErrCheck 398 * 0x80 = error 399 * 0x08 = frame error 400 * 0x04 = parity error 401 */ 402 int 403 ScifErrCheck(void) 404 { 405 406 return (scif_ssr_read() & (SCSSR2_ER | SCSSR2_FER | SCSSR2_PER)); 407 } 408 409 /* 410 * scif_getc 411 */ 412 unsigned char 413 scif_getc(void) 414 { 415 unsigned char c, err_c; 416 #ifdef SH4 417 unsigned short err_c2 = 0; /* XXXGCC: -Wuninitialized */ 418 #endif 419 420 for (;;) { 421 /* wait for ready */ 422 while ((scif_fdr_read() & SCFDR2_RECVCNT) == 0) 423 continue; 424 425 c = scif_frdr_read(); 426 err_c = scif_ssr_read(); 427 scif_ssr_write(scif_ssr_read() 428 & ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_RDF | SCSSR2_DR)); 429 #ifdef SH4 430 if (CPU_IS_SH4) { 431 err_c2 = scif_lsr_read(); 432 scif_lsr_write(scif_lsr_read() & ~SCLSR2_ORER); 433 } 434 #endif 435 if ((err_c & (SCSSR2_ER | SCSSR2_BRK | SCSSR2_FER 436 | SCSSR2_PER)) == 0) { 437 #ifdef SH4 438 if (CPU_IS_SH4 && ((err_c2 & SCLSR2_ORER) == 0)) 439 #endif 440 return(c); 441 } 442 } 443 444 } 445 446 static int 447 scif_match(struct device *parent, struct cfdata *cfp, void *aux) 448 { 449 450 if (strcmp(cfp->cf_name, "scif") || scif_attached) 451 return 0; 452 453 return 1; 454 } 455 456 static void 457 scif_attach(struct device *parent, struct device *self, void *aux) 458 { 459 struct scif_softc *sc = (struct scif_softc *)self; 460 struct tty *tp; 461 462 scif_attached = 1; 463 464 sc->sc_hwflags = 0; /* XXX */ 465 sc->sc_swflags = 0; /* XXX */ 466 sc->sc_fifolen = 16; 467 468 if (scifisconsole || kgdb_attached) { 469 /* InitializeScif(scifcn_speed); */ 470 SET(sc->sc_hwflags, SCIF_HW_CONSOLE); 471 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR); 472 if (kgdb_attached) { 473 SET(sc->sc_hwflags, SCIF_HW_KGDB); 474 printf("\n%s: kgdb\n", sc->sc_dev.dv_xname); 475 } else { 476 printf("\n%s: console\n", sc->sc_dev.dv_xname); 477 } 478 } else { 479 InitializeScif(9600); 480 printf("\n"); 481 } 482 483 callout_init(&sc->sc_diag_ch); 484 #ifdef SH4 485 intc_intr_establish(SH4_INTEVT_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 486 scifintr, sc); 487 intc_intr_establish(SH4_INTEVT_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 488 scifintr, sc); 489 intc_intr_establish(SH4_INTEVT_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 490 scifintr, sc); 491 intc_intr_establish(SH4_INTEVT_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 492 scifintr, sc); 493 #else 494 intc_intr_establish(SH7709_INTEVT2_SCIF_ERI, IST_LEVEL, IPL_SERIAL, 495 scifintr, sc); 496 intc_intr_establish(SH7709_INTEVT2_SCIF_RXI, IST_LEVEL, IPL_SERIAL, 497 scifintr, sc); 498 intc_intr_establish(SH7709_INTEVT2_SCIF_BRI, IST_LEVEL, IPL_SERIAL, 499 scifintr, sc); 500 intc_intr_establish(SH7709_INTEVT2_SCIF_TXI, IST_LEVEL, IPL_SERIAL, 501 scifintr, sc); 502 #endif 503 504 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 505 sc->sc_si = softintr_establish(IPL_SOFTSERIAL, scifsoft, sc); 506 #endif 507 SET(sc->sc_hwflags, SCIF_HW_DEV_OK); 508 509 tp = ttymalloc(); 510 tp->t_oproc = scifstart; 511 tp->t_param = scifparam; 512 tp->t_hwiflow = NULL; 513 514 sc->sc_tty = tp; 515 sc->sc_rbuf = malloc(scif_rbuf_size << 1, M_DEVBUF, M_NOWAIT); 516 if (sc->sc_rbuf == NULL) { 517 printf("%s: unable to allocate ring buffer\n", 518 sc->sc_dev.dv_xname); 519 return; 520 } 521 sc->sc_ebuf = sc->sc_rbuf + (scif_rbuf_size << 1); 522 523 tty_attach(tp); 524 } 525 526 /* 527 * Start or restart transmission. 528 */ 529 static void 530 scifstart(struct tty *tp) 531 { 532 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 533 int s; 534 535 s = spltty(); 536 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP)) 537 goto out; 538 if (sc->sc_tx_stopped) 539 goto out; 540 541 if (tp->t_outq.c_cc <= tp->t_lowat) { 542 if (ISSET(tp->t_state, TS_ASLEEP)) { 543 CLR(tp->t_state, TS_ASLEEP); 544 wakeup(&tp->t_outq); 545 } 546 selwakeup(&tp->t_wsel); 547 if (tp->t_outq.c_cc == 0) 548 goto out; 549 } 550 551 /* Grab the first contiguous region of buffer space. */ 552 { 553 u_char *tba; 554 int tbc; 555 556 tba = tp->t_outq.c_cf; 557 tbc = ndqb(&tp->t_outq, 0); 558 559 (void)splserial(); 560 561 sc->sc_tba = tba; 562 sc->sc_tbc = tbc; 563 } 564 565 SET(tp->t_state, TS_BUSY); 566 sc->sc_tx_busy = 1; 567 568 /* Enable transmit completion interrupts if necessary. */ 569 scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE); 570 571 /* Output the first chunk of the contiguous buffer. */ 572 { 573 int n; 574 int maxchars; 575 int i; 576 577 n = sc->sc_tbc; 578 maxchars = sc->sc_fifolen 579 - ((scif_fdr_read() & SCFDR2_TXCNT) >> 8); 580 if (n > maxchars) 581 n = maxchars; 582 583 for (i = 0; i < n; i++) { 584 scif_putc(*(sc->sc_tba)); 585 sc->sc_tba++; 586 } 587 sc->sc_tbc -= n; 588 } 589 out: 590 splx(s); 591 return; 592 } 593 594 /* 595 * Set SCIF tty parameters from termios. 596 * XXX - Should just copy the whole termios after 597 * making sure all the changes could be done. 598 */ 599 static int 600 scifparam(struct tty *tp, struct termios *t) 601 { 602 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 603 int ospeed = t->c_ospeed; 604 int s; 605 606 if (!device_is_active(&sc->sc_dev)) 607 return (EIO); 608 609 /* Check requested parameters. */ 610 if (ospeed < 0) 611 return (EINVAL); 612 if (t->c_ispeed && t->c_ispeed != t->c_ospeed) 613 return (EINVAL); 614 615 /* 616 * For the console, always force CLOCAL and !HUPCL, so that the port 617 * is always active. 618 */ 619 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) || 620 ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 621 SET(t->c_cflag, CLOCAL); 622 CLR(t->c_cflag, HUPCL); 623 } 624 625 /* 626 * If there were no changes, don't do anything. This avoids dropping 627 * input and improves performance when all we did was frob things like 628 * VMIN and VTIME. 629 */ 630 if (tp->t_ospeed == t->c_ospeed && 631 tp->t_cflag == t->c_cflag) 632 return (0); 633 634 #if 0 635 /* XXX (msaitoh) */ 636 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag); 637 #endif 638 639 s = splserial(); 640 641 /* 642 * Set the flow control pins depending on the current flow control 643 * mode. 644 */ 645 if (ISSET(t->c_cflag, CRTSCTS)) { 646 scif_fcr_write(scif_fcr_read() | SCFCR2_MCE); 647 } else { 648 scif_fcr_write(scif_fcr_read() & ~SCFCR2_MCE); 649 } 650 651 scif_brr_write(divrnd(sh_clock_get_pclock(), 32 * ospeed) -1); 652 653 /* 654 * Set the FIFO threshold based on the receive speed. 655 * 656 * * If it's a low speed, it's probably a mouse or some other 657 * interactive device, so set the threshold low. 658 * * If it's a high speed, trim the trigger level down to prevent 659 * overflows. 660 * * Otherwise set it a bit higher. 661 */ 662 #if 0 663 /* XXX (msaitoh) */ 664 if (ISSET(sc->sc_hwflags, SCIF_HW_HAYESP)) 665 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8; 666 else if (ISSET(sc->sc_hwflags, SCIF_HW_FIFO)) 667 sc->sc_fifo = FIFO_ENABLE | 668 (t->c_ospeed <= 1200 ? FIFO_TRIGGER_1 : 669 t->c_ospeed <= 38400 ? FIFO_TRIGGER_8 : FIFO_TRIGGER_4); 670 else 671 sc->sc_fifo = 0; 672 #endif 673 674 /* And copy to tty. */ 675 tp->t_ispeed = 0; 676 tp->t_ospeed = t->c_ospeed; 677 tp->t_cflag = t->c_cflag; 678 679 if (!sc->sc_heldchange) { 680 if (sc->sc_tx_busy) { 681 sc->sc_heldtbc = sc->sc_tbc; 682 sc->sc_tbc = 0; 683 sc->sc_heldchange = 1; 684 } 685 #if 0 686 /* XXX (msaitoh) */ 687 else 688 scif_loadchannelregs(sc); 689 #endif 690 } 691 692 if (!ISSET(t->c_cflag, CHWFLOW)) { 693 /* Disable the high water mark. */ 694 sc->sc_r_hiwat = 0; 695 sc->sc_r_lowat = 0; 696 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) { 697 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 698 scif_schedrx(sc); 699 } 700 } else { 701 sc->sc_r_hiwat = scif_rbuf_hiwat; 702 sc->sc_r_lowat = scif_rbuf_lowat; 703 } 704 705 splx(s); 706 707 #ifdef SCIF_DEBUG 708 if (scif_debug) 709 scifstatus(sc, "scifparam "); 710 #endif 711 712 if (!ISSET(t->c_cflag, CHWFLOW)) { 713 if (sc->sc_tx_stopped) { 714 sc->sc_tx_stopped = 0; 715 scifstart(tp); 716 } 717 } 718 719 return (0); 720 } 721 722 void 723 scif_iflush(struct scif_softc *sc) 724 { 725 int i; 726 unsigned char c; 727 728 i = scif_fdr_read() & SCFDR2_RECVCNT; 729 730 while (i > 0) { 731 c = scif_frdr_read(); 732 scif_ssr_write(scif_ssr_read() & ~(SCSSR2_RDF | SCSSR2_DR)); 733 i--; 734 } 735 } 736 737 int 738 scifopen(dev_t dev, int flag, int mode, struct lwp *l) 739 { 740 int unit = SCIFUNIT(dev); 741 struct scif_softc *sc; 742 struct tty *tp; 743 int s, s2; 744 int error; 745 746 if (unit >= scif_cd.cd_ndevs) 747 return (ENXIO); 748 sc = scif_cd.cd_devs[unit]; 749 if (sc == 0 || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK) || 750 sc->sc_rbuf == NULL) 751 return (ENXIO); 752 753 if (!device_is_active(&sc->sc_dev)) 754 return (ENXIO); 755 756 #ifdef KGDB 757 /* 758 * If this is the kgdb port, no other use is permitted. 759 */ 760 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) 761 return (EBUSY); 762 #endif /* KGDB */ 763 764 tp = sc->sc_tty; 765 766 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 767 return (EBUSY); 768 769 s = spltty(); 770 771 /* 772 * Do the following iff this is a first open. 773 */ 774 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) { 775 struct termios t; 776 777 tp->t_dev = dev; 778 779 s2 = splserial(); 780 781 /* Turn on interrupts. */ 782 scif_scr_write(scif_scr_read() | SCSCR2_TIE | SCSCR2_RIE); 783 784 splx(s2); 785 786 /* 787 * Initialize the termios status to the defaults. Add in the 788 * sticky bits from TIOCSFLAGS. 789 */ 790 t.c_ispeed = 0; 791 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 792 t.c_ospeed = scifcn_speed; /* XXX (msaitoh) */ 793 t.c_cflag = scifconscflag; 794 } else { 795 t.c_ospeed = TTYDEF_SPEED; 796 t.c_cflag = TTYDEF_CFLAG; 797 } 798 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL)) 799 SET(t.c_cflag, CLOCAL); 800 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS)) 801 SET(t.c_cflag, CRTSCTS); 802 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF)) 803 SET(t.c_cflag, MDMBUF); 804 /* Make sure scifparam() will do something. */ 805 tp->t_ospeed = 0; 806 (void) scifparam(tp, &t); 807 tp->t_iflag = TTYDEF_IFLAG; 808 tp->t_oflag = TTYDEF_OFLAG; 809 tp->t_lflag = TTYDEF_LFLAG; 810 ttychars(tp); 811 ttsetwater(tp); 812 813 s2 = splserial(); 814 815 /* Clear the input ring, and unblock. */ 816 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf; 817 sc->sc_rbavail = scif_rbuf_size; 818 scif_iflush(sc); 819 CLR(sc->sc_rx_flags, RX_ANY_BLOCK); 820 #if 0 821 /* XXX (msaitoh) */ 822 scif_hwiflow(sc); 823 #endif 824 825 #ifdef SCIF_DEBUG 826 if (scif_debug) 827 scifstatus(sc, "scifopen "); 828 #endif 829 830 splx(s2); 831 } 832 833 splx(s); 834 835 error = ttyopen(tp, SCIFDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 836 if (error) 837 goto bad; 838 839 error = (*tp->t_linesw->l_open)(dev, tp); 840 if (error) 841 goto bad; 842 843 return (0); 844 845 bad: 846 847 return (error); 848 } 849 850 int 851 scifclose(dev_t dev, int flag, int mode, struct lwp *l) 852 { 853 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 854 struct tty *tp = sc->sc_tty; 855 856 /* XXX This is for cons.c. */ 857 if (!ISSET(tp->t_state, TS_ISOPEN)) 858 return (0); 859 860 (*tp->t_linesw->l_close)(tp, flag); 861 ttyclose(tp); 862 863 if (!device_is_active(&sc->sc_dev)) 864 return (0); 865 866 return (0); 867 } 868 869 int 870 scifread(dev_t dev, struct uio *uio, int flag) 871 { 872 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 873 struct tty *tp = sc->sc_tty; 874 875 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 876 } 877 878 int 879 scifwrite(dev_t dev, struct uio *uio, int flag) 880 { 881 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 882 struct tty *tp = sc->sc_tty; 883 884 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 885 } 886 887 int 888 scifpoll(dev_t dev, int events, struct lwp *l) 889 { 890 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 891 struct tty *tp = sc->sc_tty; 892 893 return ((*tp->t_linesw->l_poll)(tp, events, l)); 894 } 895 896 struct tty * 897 sciftty(dev_t dev) 898 { 899 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 900 struct tty *tp = sc->sc_tty; 901 902 return (tp); 903 } 904 905 int 906 scifioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 907 { 908 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(dev)]; 909 struct tty *tp = sc->sc_tty; 910 int error; 911 int s; 912 913 if (!device_is_active(&sc->sc_dev)) 914 return (EIO); 915 916 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 917 if (error != EPASSTHROUGH) 918 return (error); 919 920 error = ttioctl(tp, cmd, data, flag, l); 921 if (error != EPASSTHROUGH) 922 return (error); 923 924 error = 0; 925 926 s = splserial(); 927 928 switch (cmd) { 929 case TIOCSBRK: 930 scif_break(sc, 1); 931 break; 932 933 case TIOCCBRK: 934 scif_break(sc, 0); 935 break; 936 937 case TIOCGFLAGS: 938 *(int *)data = sc->sc_swflags; 939 break; 940 941 case TIOCSFLAGS: 942 error = kauth_authorize_device_tty(l->l_cred, 943 KAUTH_DEVICE_TTY_PRIVSET, tp); 944 if (error) 945 break; 946 sc->sc_swflags = *(int *)data; 947 break; 948 949 default: 950 error = EPASSTHROUGH; 951 break; 952 } 953 954 splx(s); 955 956 return (error); 957 } 958 959 integrate void 960 scif_schedrx(struct scif_softc *sc) 961 { 962 963 sc->sc_rx_ready = 1; 964 965 /* Wake up the poller. */ 966 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 967 softintr_schedule(sc->sc_si); 968 #else 969 #ifndef __NO_SOFT_SERIAL_INTERRUPT 970 setsoftserial(); 971 #else 972 if (!scif_softintr_scheduled) { 973 scif_softintr_scheduled = 1; 974 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 975 } 976 #endif 977 #endif 978 } 979 980 void 981 scif_break(struct scif_softc *sc, int onoff) 982 { 983 984 if (onoff) 985 scif_ssr_write(scif_ssr_read() & ~SCSSR2_TDFE); 986 else 987 scif_ssr_write(scif_ssr_read() | SCSSR2_TDFE); 988 989 #if 0 /* XXX */ 990 if (!sc->sc_heldchange) { 991 if (sc->sc_tx_busy) { 992 sc->sc_heldtbc = sc->sc_tbc; 993 sc->sc_tbc = 0; 994 sc->sc_heldchange = 1; 995 } else 996 scif_loadchannelregs(sc); 997 } 998 #endif 999 } 1000 1001 /* 1002 * Stop output, e.g., for ^S or output flush. 1003 */ 1004 void 1005 scifstop(struct tty *tp, int flag) 1006 { 1007 struct scif_softc *sc = scif_cd.cd_devs[SCIFUNIT(tp->t_dev)]; 1008 int s; 1009 1010 s = splserial(); 1011 if (ISSET(tp->t_state, TS_BUSY)) { 1012 /* Stop transmitting at the next chunk. */ 1013 sc->sc_tbc = 0; 1014 sc->sc_heldtbc = 0; 1015 if (!ISSET(tp->t_state, TS_TTSTOP)) 1016 SET(tp->t_state, TS_FLUSH); 1017 } 1018 splx(s); 1019 } 1020 1021 void 1022 scif_intr_init() 1023 { 1024 /* XXX */ 1025 } 1026 1027 void 1028 scifdiag(void *arg) 1029 { 1030 struct scif_softc *sc = arg; 1031 int overflows, floods; 1032 int s; 1033 1034 s = splserial(); 1035 overflows = sc->sc_overflows; 1036 sc->sc_overflows = 0; 1037 floods = sc->sc_floods; 1038 sc->sc_floods = 0; 1039 sc->sc_errors = 0; 1040 splx(s); 1041 1042 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n", 1043 sc->sc_dev.dv_xname, 1044 overflows, overflows == 1 ? "" : "s", 1045 floods, floods == 1 ? "" : "s"); 1046 } 1047 1048 integrate void 1049 scif_rxsoft(struct scif_softc *sc, struct tty *tp) 1050 { 1051 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint; 1052 u_char *get, *end; 1053 u_int cc, scc; 1054 u_char ssr2; 1055 int code; 1056 int s; 1057 1058 end = sc->sc_ebuf; 1059 get = sc->sc_rbget; 1060 scc = cc = scif_rbuf_size - sc->sc_rbavail; 1061 1062 if (cc == scif_rbuf_size) { 1063 sc->sc_floods++; 1064 if (sc->sc_errors++ == 0) 1065 callout_reset(&sc->sc_diag_ch, 60 * hz, scifdiag, sc); 1066 } 1067 1068 while (cc) { 1069 code = get[0]; 1070 ssr2 = get[1]; 1071 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER | SCSSR2_PER)) { 1072 if (ISSET(ssr2, SCSSR2_BRK | SCSSR2_FER)) 1073 SET(code, TTY_FE); 1074 if (ISSET(ssr2, SCSSR2_PER)) 1075 SET(code, TTY_PE); 1076 } 1077 if ((*rint)(code, tp) == -1) { 1078 /* 1079 * The line discipline's buffer is out of space. 1080 */ 1081 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) { 1082 /* 1083 * We're either not using flow control, or the 1084 * line discipline didn't tell us to block for 1085 * some reason. Either way, we have no way to 1086 * know when there's more space available, so 1087 * just drop the rest of the data. 1088 */ 1089 get += cc << 1; 1090 if (get >= end) 1091 get -= scif_rbuf_size << 1; 1092 cc = 0; 1093 } else { 1094 /* 1095 * Don't schedule any more receive processing 1096 * until the line discipline tells us there's 1097 * space available (through scifhwiflow()). 1098 * Leave the rest of the data in the input 1099 * buffer. 1100 */ 1101 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED); 1102 } 1103 break; 1104 } 1105 get += 2; 1106 if (get >= end) 1107 get = sc->sc_rbuf; 1108 cc--; 1109 } 1110 1111 if (cc != scc) { 1112 sc->sc_rbget = get; 1113 s = splserial(); 1114 cc = sc->sc_rbavail += scc - cc; 1115 /* Buffers should be ok again, release possible block. */ 1116 if (cc >= sc->sc_r_lowat) { 1117 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) { 1118 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1119 scif_scr_write(scif_scr_read() | SCSCR2_RIE); 1120 } 1121 #if 0 1122 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) { 1123 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1124 scif_hwiflow(sc); 1125 } 1126 #endif 1127 } 1128 splx(s); 1129 } 1130 } 1131 1132 integrate void 1133 scif_txsoft(struct scif_softc *sc, struct tty *tp) 1134 { 1135 1136 CLR(tp->t_state, TS_BUSY); 1137 if (ISSET(tp->t_state, TS_FLUSH)) 1138 CLR(tp->t_state, TS_FLUSH); 1139 else 1140 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf)); 1141 (*tp->t_linesw->l_start)(tp); 1142 } 1143 1144 integrate void 1145 scif_stsoft(struct scif_softc *sc, struct tty *tp) 1146 { 1147 #if 0 1148 /* XXX (msaitoh) */ 1149 u_char msr, delta; 1150 int s; 1151 1152 s = splserial(); 1153 msr = sc->sc_msr; 1154 delta = sc->sc_msr_delta; 1155 sc->sc_msr_delta = 0; 1156 splx(s); 1157 1158 if (ISSET(delta, sc->sc_msr_dcd)) { 1159 /* 1160 * Inform the tty layer that carrier detect changed. 1161 */ 1162 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD)); 1163 } 1164 1165 if (ISSET(delta, sc->sc_msr_cts)) { 1166 /* Block or unblock output according to flow control. */ 1167 if (ISSET(msr, sc->sc_msr_cts)) { 1168 sc->sc_tx_stopped = 0; 1169 (*tp->t_linesw->l_start)(tp); 1170 } else { 1171 sc->sc_tx_stopped = 1; 1172 } 1173 } 1174 1175 #ifdef SCIF_DEBUG 1176 if (scif_debug) 1177 scifstatus(sc, "scif_stsoft"); 1178 #endif 1179 #endif 1180 } 1181 1182 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1183 void 1184 scifsoft(void *arg) 1185 { 1186 struct scif_softc *sc = arg; 1187 struct tty *tp; 1188 1189 if (!device_is_active(&sc->sc_dev)) 1190 return; 1191 1192 { 1193 #else 1194 void 1195 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1196 scifsoft() 1197 #else 1198 scifsoft(void *arg) 1199 #endif 1200 { 1201 struct scif_softc *sc; 1202 struct tty *tp; 1203 int unit; 1204 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1205 int s; 1206 1207 s = splsoftserial(); 1208 scif_softintr_scheduled = 0; 1209 #endif 1210 1211 for (unit = 0; unit < scif_cd.cd_ndevs; unit++) { 1212 sc = scif_cd.cd_devs[unit]; 1213 if (sc == NULL || !ISSET(sc->sc_hwflags, SCIF_HW_DEV_OK)) 1214 continue; 1215 1216 if (!device_is_active(&sc->sc_dev)) 1217 continue; 1218 1219 tp = sc->sc_tty; 1220 if (tp == NULL) 1221 continue; 1222 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) 1223 continue; 1224 #endif 1225 tp = sc->sc_tty; 1226 1227 if (sc->sc_rx_ready) { 1228 sc->sc_rx_ready = 0; 1229 scif_rxsoft(sc, tp); 1230 } 1231 1232 #if 0 1233 if (sc->sc_st_check) { 1234 sc->sc_st_check = 0; 1235 scif_stsoft(sc, tp); 1236 } 1237 #endif 1238 1239 if (sc->sc_tx_done) { 1240 sc->sc_tx_done = 0; 1241 scif_txsoft(sc, tp); 1242 } 1243 } 1244 1245 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1246 #ifdef __NO_SOFT_SERIAL_INTERRUPT 1247 splx(s); 1248 #endif 1249 #endif 1250 } 1251 1252 int 1253 scifintr(void *arg) 1254 { 1255 struct scif_softc *sc = arg; 1256 u_char *put, *end; 1257 u_int cc; 1258 u_short ssr2; 1259 int count; 1260 1261 if (!device_is_active(&sc->sc_dev)) 1262 return (0); 1263 1264 end = sc->sc_ebuf; 1265 put = sc->sc_rbput; 1266 cc = sc->sc_rbavail; 1267 1268 do { 1269 ssr2 = scif_ssr_read(); 1270 if (ISSET(ssr2, SCSSR2_BRK)) { 1271 scif_ssr_write(scif_ssr_read() 1272 & ~(SCSSR2_ER | SCSSR2_BRK | SCSSR2_DR)); 1273 #ifdef DDB 1274 if (ISSET(sc->sc_hwflags, SCIF_HW_CONSOLE)) { 1275 console_debugger(); 1276 } 1277 #endif /* DDB */ 1278 #ifdef KGDB 1279 if (ISSET(sc->sc_hwflags, SCIF_HW_KGDB)) { 1280 kgdb_connect(1); 1281 } 1282 #endif /* KGDB */ 1283 } 1284 count = scif_fdr_read() & SCFDR2_RECVCNT; 1285 if (count != 0) { 1286 for (;;) { 1287 u_char c = scif_frdr_read(); 1288 u_char err = (u_char)(scif_ssr_read() & 0x00ff); 1289 1290 scif_ssr_write(scif_ssr_read() 1291 & ~(SCSSR2_ER | SCSSR2_RDF | SCSSR2_DR)); 1292 #ifdef SH4 1293 if (CPU_IS_SH4) 1294 scif_lsr_write(scif_lsr_read() 1295 & ~SCLSR2_ORER); 1296 #endif 1297 if ((cc > 0) && (count > 0)) { 1298 put[0] = c; 1299 put[1] = err; 1300 put += 2; 1301 if (put >= end) 1302 put = sc->sc_rbuf; 1303 cc--; 1304 count--; 1305 } else 1306 break; 1307 } 1308 1309 /* 1310 * Current string of incoming characters ended because 1311 * no more data was available or we ran out of space. 1312 * Schedule a receive event if any data was received. 1313 * If we're out of space, turn off receive interrupts. 1314 */ 1315 sc->sc_rbput = put; 1316 sc->sc_rbavail = cc; 1317 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) 1318 sc->sc_rx_ready = 1; 1319 1320 /* 1321 * See if we are in danger of overflowing a buffer. If 1322 * so, use hardware flow control to ease the pressure. 1323 */ 1324 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) && 1325 cc < sc->sc_r_hiwat) { 1326 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED); 1327 #if 0 1328 scif_hwiflow(sc); 1329 #endif 1330 } 1331 1332 /* 1333 * If we're out of space, disable receive interrupts 1334 * until the queue has drained a bit. 1335 */ 1336 if (!cc) { 1337 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED); 1338 scif_scr_write(scif_scr_read() & ~SCSCR2_RIE); 1339 } 1340 } else { 1341 if (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR)) { 1342 scif_scr_write(scif_scr_read() 1343 & ~(SCSCR2_TIE | SCSCR2_RIE)); 1344 delay(10); 1345 scif_scr_write(scif_scr_read() 1346 | SCSCR2_TIE | SCSCR2_RIE); 1347 continue; 1348 } 1349 } 1350 } while (scif_ssr_read() & (SCSSR2_RDF | SCSSR2_DR)); 1351 1352 #if 0 1353 msr = bus_space_read_1(iot, ioh, scif_msr); 1354 delta = msr ^ sc->sc_msr; 1355 sc->sc_msr = msr; 1356 if (ISSET(delta, sc->sc_msr_mask)) { 1357 SET(sc->sc_msr_delta, delta); 1358 1359 /* 1360 * Pulse-per-second clock signal on edge of DCD? 1361 */ 1362 if (ISSET(delta, sc->sc_ppsmask)) { 1363 struct timeval tv; 1364 if (ISSET(msr, sc->sc_ppsmask) == 1365 sc->sc_ppsassert) { 1366 /* XXX nanotime() */ 1367 microtime(&tv); 1368 TIMEVAL_TO_TIMESPEC(&tv, 1369 &sc->ppsinfo.assert_timestamp); 1370 if (sc->ppsparam.mode & PPS_OFFSETASSERT) { 1371 timespecadd(&sc->ppsinfo.assert_timestamp, 1372 &sc->ppsparam.assert_offset, 1373 &sc->ppsinfo.assert_timestamp); 1374 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.assert_timestamp); 1375 } 1376 1377 #ifdef PPS_SYNC 1378 if (sc->ppsparam.mode & PPS_HARDPPSONASSERT) 1379 hardpps(&tv, tv.tv_usec); 1380 #endif 1381 sc->ppsinfo.assert_sequence++; 1382 sc->ppsinfo.current_mode = 1383 sc->ppsparam.mode; 1384 1385 } else if (ISSET(msr, sc->sc_ppsmask) == 1386 sc->sc_ppsclear) { 1387 /* XXX nanotime() */ 1388 microtime(&tv); 1389 TIMEVAL_TO_TIMESPEC(&tv, 1390 &sc->ppsinfo.clear_timestamp); 1391 if (sc->ppsparam.mode & PPS_OFFSETCLEAR) { 1392 timespecadd(&sc->ppsinfo.clear_timestamp, 1393 &sc->ppsparam.clear_offset, 1394 &sc->ppsinfo.clear_timestamp); 1395 TIMESPEC_TO_TIMEVAL(&tv, &sc->ppsinfo.clear_timestamp); 1396 } 1397 1398 #ifdef PPS_SYNC 1399 if (sc->ppsparam.mode & PPS_HARDPPSONCLEAR) 1400 hardpps(&tv, tv.tv_usec); 1401 #endif 1402 sc->ppsinfo.clear_sequence++; 1403 sc->ppsinfo.current_mode = 1404 sc->ppsparam.mode; 1405 } 1406 } 1407 1408 /* 1409 * Stop output immediately if we lose the output 1410 * flow control signal or carrier detect. 1411 */ 1412 if (ISSET(~msr, sc->sc_msr_mask)) { 1413 sc->sc_tbc = 0; 1414 sc->sc_heldtbc = 0; 1415 #ifdef SCIF_DEBUG 1416 if (scif_debug) 1417 scifstatus(sc, "scifintr "); 1418 #endif 1419 } 1420 1421 sc->sc_st_check = 1; 1422 } 1423 #endif 1424 1425 /* 1426 * Done handling any receive interrupts. See if data can be 1427 * transmitted as well. Schedule tx done event if no data left 1428 * and tty was marked busy. 1429 */ 1430 if (((scif_fdr_read() & SCFDR2_TXCNT) >> 8) != 16) { /* XXX (msaitoh) */ 1431 /* 1432 * If we've delayed a parameter change, do it now, and restart 1433 * output. 1434 */ 1435 if (sc->sc_heldchange) { 1436 sc->sc_heldchange = 0; 1437 sc->sc_tbc = sc->sc_heldtbc; 1438 sc->sc_heldtbc = 0; 1439 } 1440 1441 /* Output the next chunk of the contiguous buffer, if any. */ 1442 if (sc->sc_tbc > 0) { 1443 int n; 1444 int maxchars; 1445 int i; 1446 1447 n = sc->sc_tbc; 1448 maxchars = sc->sc_fifolen - 1449 ((scif_fdr_read() & SCFDR2_TXCNT) >> 8); 1450 if (n > maxchars) 1451 n = maxchars; 1452 1453 for (i = 0; i < n; i++) { 1454 scif_putc(*(sc->sc_tba)); 1455 sc->sc_tba++; 1456 } 1457 sc->sc_tbc -= n; 1458 } else { 1459 /* Disable transmit completion interrupts if necessary. */ 1460 #if 0 1461 if (ISSET(sc->sc_ier, IER_ETXRDY)) 1462 #endif 1463 scif_scr_write(scif_scr_read() & ~SCSCR2_TIE); 1464 1465 if (sc->sc_tx_busy) { 1466 sc->sc_tx_busy = 0; 1467 sc->sc_tx_done = 1; 1468 } 1469 } 1470 } 1471 1472 /* Wake up the poller. */ 1473 #ifdef __HAVE_GENERIC_SOFT_INTERRUPTS 1474 softintr_schedule(sc->sc_si); 1475 #else 1476 #ifndef __NO_SOFT_SERIAL_INTERRUPT 1477 setsoftserial(); 1478 #else 1479 if (!scif_softintr_scheduled) { 1480 scif_softintr_scheduled = 1; 1481 callout_reset(&scif_soft_ch, 1, scifsoft, NULL); 1482 } 1483 #endif 1484 #endif 1485 1486 #if NRND > 0 && defined(RND_SCIF) 1487 rnd_add_uint32(&sc->rnd_source, iir | lsr); 1488 #endif 1489 1490 return (1); 1491 } 1492 1493 void 1494 scifcnprobe(struct consdev *cp) 1495 { 1496 int maj; 1497 1498 /* locate the major number */ 1499 maj = cdevsw_lookup_major(&scif_cdevsw); 1500 1501 /* Initialize required fields. */ 1502 cp->cn_dev = makedev(maj, 0); 1503 #ifdef SCIFCONSOLE 1504 cp->cn_pri = CN_REMOTE; 1505 #else 1506 cp->cn_pri = CN_NORMAL; 1507 #endif 1508 } 1509 1510 void 1511 scifcninit(struct consdev *cp) 1512 { 1513 1514 InitializeScif(scifcn_speed); 1515 scifisconsole = 1; 1516 } 1517 1518 int 1519 scifcngetc(dev_t dev) 1520 { 1521 int c; 1522 int s; 1523 1524 s = splserial(); 1525 c = scif_getc(); 1526 splx(s); 1527 1528 return (c); 1529 } 1530 1531 void 1532 scifcnputc(dev_t dev, int c) 1533 { 1534 int s; 1535 1536 s = splserial(); 1537 scif_putc((u_char)c); 1538 splx(s); 1539 } 1540 1541 #ifdef KGDB 1542 int 1543 scif_kgdb_init() 1544 { 1545 1546 if (strcmp(kgdb_devname, "scif") != 0) 1547 return (1); 1548 1549 if (scifisconsole) 1550 return (1); /* can't share with console */ 1551 1552 InitializeScif(kgdb_rate); 1553 1554 kgdb_attach((int (*)(void *))scifcngetc, 1555 (void (*)(void *, int))scifcnputc, NULL); 1556 kgdb_dev = 123; /* unneeded, only to satisfy some tests */ 1557 kgdb_attached = 1; 1558 1559 return (0); 1560 } 1561 #endif /* KGDB */ 1562
Indexes created Sun Sep 28 12:09:53 GMT 2025