1 /* $NetBSD: cache_sh4.h,v 1.12 2008/04/28 20:23:35 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * SH4: SH7750 SH7750S SH7750R SH7751 SH7751R 34 */ 35 36 #ifndef _SH3_CACHE_SH4_H_ 37 #define _SH3_CACHE_SH4_H_ 38 #include <sh3/devreg.h> 39 #ifdef _KERNEL 40 41 #define SH4_ICACHE_SIZE 8192 42 #define SH4_DCACHE_SIZE 16384 43 #define SH4_EMODE_ICACHE_SIZE 16384 44 #define SH4_EMODE_DCACHE_SIZE 32768 45 #define SH4_CACHE_LINESZ 32 46 47 #define SH4_CCR 0xff00001c 48 #define SH4_CCR_EMODE 0x80000000 49 #define SH4_CCR_IIX 0x00008000 50 #define SH4_CCR_ICI 0x00000800 51 #define SH4_CCR_ICE 0x00000100 52 #define SH4_CCR_OIX 0x00000080 53 #define SH4_CCR_ORA 0x00000020 54 #define SH4_CCR_OCI 0x00000008 55 #define SH4_CCR_CB 0x00000004 56 #define SH4_CCR_WT 0x00000002 57 #define SH4_CCR_OCE 0x00000001 58 59 #define SH4_QACR0 0xff000038 60 #define SH4_QACR1 0xff00003c 61 #define SH4_QACR_AREA_SHIFT 2 62 #define SH4_QACR_AREA_MASK 0x0000001c 63 64 /* I-cache address/data array */ 65 #define SH4_CCIA 0xf0000000 66 /* address specification */ 67 #define CCIA_A 0x00000008 /* associate bit */ 68 #define CCIA_ENTRY_SHIFT 5 /* line size 32B */ 69 #define CCIA_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */ 70 #define CCIA_EMODE_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */ 71 /* data specification */ 72 #define CCIA_V 0x00000001 73 #define CCIA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 74 75 #define SH4_CCID 0xf1000000 76 /* address specification */ 77 #define CCID_L_SHIFT 2 78 #define CCID_L_MASK 0x1c /* line-size is 32B */ 79 #define CCID_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */ 80 81 /* D-cache address/data array */ 82 #define SH4_CCDA 0xf4000000 83 /* address specification */ 84 #define CCDA_A 0x00000008 /* associate bit */ 85 #define CCDA_ENTRY_SHIFT 5 /* line size 32B */ 86 #define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */ 87 /* data specification */ 88 #define CCDA_V 0x00000001 89 #define CCDA_U 0x00000002 90 #define CCDA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 91 92 #define SH4_CCDD 0xf5000000 93 94 /* Store Queue */ 95 #define SH4_SQ 0xe0000000 96 97 /* 98 * cache flush macro for locore level code. 99 */ 100 #define SH4_CACHE_FLUSH() \ 101 do { \ 102 uint32_t __e, __a; \ 103 \ 104 /* D-cache */ \ 105 for (__e = 0; __e < (SH4_DCACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\ 106 __a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \ 107 (*(volatile uint32_t *)__a) &= ~(CCDA_U | CCDA_V); \ 108 } \ 109 /* I-cache */ \ 110 for (__e = 0; __e < (SH4_ICACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\ 111 __a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \ 112 (*(volatile uint32_t *)__a) &= ~(CCIA_V); \ 113 } \ 114 } while(/*CONSTCOND*/0) 115 116 #define SH4_EMODE_CACHE_FLUSH() \ 117 do { \ 118 uint32_t __e, __a; \ 119 \ 120 /* D-cache */ \ 121 for (__e = 0;__e < (SH4_EMODE_DCACHE_SIZE / SH4_CACHE_LINESZ);__e++) {\ 122 __a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \ 123 (*(volatile uint32_t *)__a) &= ~(CCDA_U | CCDA_V); \ 124 } \ 125 /* I-cache */ \ 126 for (__e = 0;__e < (SH4_EMODE_ICACHE_SIZE / SH4_CACHE_LINESZ);__e++) {\ 127 __a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \ 128 (*(volatile uint32_t *)__a) &= ~(CCIA_V); \ 129 } \ 130 } while(/*CONSTCOND*/0) 131 132 #define SH7750_CACHE_FLUSH() SH4_CACHE_FLUSH() 133 #define SH7750S_CACHE_FLUSH() SH4_CACHE_FLUSH() 134 #define SH7751_CACHE_FLUSH() SH4_CACHE_FLUSH() 135 #if defined(SH4_CACHE_DISABLE_EMODE) 136 #define SH7750R_CACHE_FLUSH() SH4_CACHE_FLUSH() 137 #define SH7751R_CACHE_FLUSH() SH4_CACHE_FLUSH() 138 #else 139 #define SH7750R_CACHE_FLUSH() SH4_EMODE_CACHE_FLUSH() 140 #define SH7751R_CACHE_FLUSH() SH4_EMODE_CACHE_FLUSH() 141 #endif 142 143 #ifndef _LOCORE 144 extern void sh4_cache_config(void); 145 #endif 146 #endif /* _KERNEL */ 147 #endif /* !_SH3_CACHE_SH4_H_ */ 148
Indexes created Sat Sep 20 22:09:52 GMT 2025