cache_sh4.h revision 1.10
1 /* $NetBSD: cache_sh4.h,v 1.10 2005/12/24 23:24:02 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * SH4: SH7750 SH7750S SH7750R SH7751 SH7751R 41 */ 42 43 #ifndef _SH3_CACHE_SH4_H_ 44 #define _SH3_CACHE_SH4_H_ 45 #include <sh3/devreg.h> 46 #ifdef _KERNEL 47 48 #define SH4_ICACHE_SIZE 8192 49 #define SH4_DCACHE_SIZE 16384 50 #define SH4_EMODE_ICACHE_SIZE 16384 51 #define SH4_EMODE_DCACHE_SIZE 32768 52 #define SH4_CACHE_LINESZ 32 53 54 #define SH4_CCR 0xff00001c 55 #define SH4_CCR_EMODE 0x80000000 56 #define SH4_CCR_IIX 0x00008000 57 #define SH4_CCR_ICI 0x00000800 58 #define SH4_CCR_ICE 0x00000100 59 #define SH4_CCR_OIX 0x00000080 60 #define SH4_CCR_ORA 0x00000020 61 #define SH4_CCR_OCI 0x00000008 62 #define SH4_CCR_CB 0x00000004 63 #define SH4_CCR_WT 0x00000002 64 #define SH4_CCR_OCE 0x00000001 65 66 #define SH4_QACR0 0xff000038 67 #define SH4_QACR1 0xff00003c 68 #define SH4_QACR_AREA_SHIFT 2 69 #define SH4_QACR_AREA_MASK 0x0000001c 70 71 /* I-cache address/data array */ 72 #define SH4_CCIA 0xf0000000 73 /* address specification */ 74 #define CCIA_A 0x00000008 /* associate bit */ 75 #define CCIA_ENTRY_SHIFT 5 /* line size 32B */ 76 #define CCIA_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */ 77 #define CCIA_EMODE_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */ 78 /* data specification */ 79 #define CCIA_V 0x00000001 80 #define CCIA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 81 82 #define SH4_CCID 0xf1000000 83 /* address specification */ 84 #define CCID_L_SHIFT 2 85 #define CCID_L_MASK 0x1c /* line-size is 32B */ 86 #define CCID_ENTRY_MASK 0x00001fe0 /* [12:5] 256-entries */ 87 88 /* D-cache address/data array */ 89 #define SH4_CCDA 0xf4000000 90 /* address specification */ 91 #define CCDA_A 0x00000008 /* associate bit */ 92 #define CCDA_ENTRY_SHIFT 5 /* line size 32B */ 93 #define CCDA_ENTRY_MASK 0x00003fe0 /* [13:5] 512-entries */ 94 /* data specification */ 95 #define CCDA_V 0x00000001 96 #define CCDA_U 0x00000002 97 #define CCDA_TAGADDR_MASK 0xfffffc00 /* [31:10] */ 98 99 #define SH4_CCDD 0xf5000000 100 101 /* Store Queue */ 102 #define SH4_SQ 0xe0000000 103 104 /* 105 * cache flush macro for locore level code. 106 */ 107 #define SH4_CACHE_FLUSH() \ 108 do { \ 109 u_int32_t __e, __a; \ 110 \ 111 /* D-cache */ \ 112 for (__e = 0; __e < (SH4_DCACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\ 113 __a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \ 114 (*(volatile uint32_t *)__a) &= ~(CCDA_U | CCDA_V); \ 115 } \ 116 /* I-cache */ \ 117 for (__e = 0; __e < (SH4_ICACHE_SIZE / SH4_CACHE_LINESZ); __e++) {\ 118 __a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \ 119 (*(volatile uint32_t *)__a) &= ~(CCIA_V); \ 120 } \ 121 } while(/*CONSTCOND*/0) 122 123 #define SH4_EMODE_CACHE_FLUSH() \ 124 do { \ 125 uint32_t __e, __a; \ 126 \ 127 /* D-cache */ \ 128 for (__e = 0;__e < (SH4_EMODE_DCACHE_SIZE / SH4_CACHE_LINESZ);__e++) {\ 129 __a = SH4_CCDA | (__e << CCDA_ENTRY_SHIFT); \ 130 (*(volatile uint32_t *)__a) &= ~(CCDA_U | CCDA_V); \ 131 } \ 132 /* I-cache */ \ 133 for (__e = 0;__e < (SH4_EMODE_ICACHE_SIZE / SH4_CACHE_LINESZ);__e++) {\ 134 __a = SH4_CCIA | (__e << CCIA_ENTRY_SHIFT); \ 135 (*(volatile uint32_t *)__a) &= ~(CCIA_V); \ 136 } \ 137 } while(/*CONSTCOND*/0) 138 139 #define SH7750_CACHE_FLUSH() SH4_CACHE_FLUSH() 140 #define SH7750S_CACHE_FLUSH() SH4_CACHE_FLUSH() 141 #define SH7751_CACHE_FLUSH() SH4_CACHE_FLUSH() 142 #if defined(SH4_CACHE_DISABLE_EMODE) 143 #define SH7750R_CACHE_FLUSH() SH4_CACHE_FLUSH() 144 #define SH7751R_CACHE_FLUSH() SH4_CACHE_FLUSH() 145 #else 146 #define SH7750R_CACHE_FLUSH() SH4_EMODE_CACHE_FLUSH() 147 #define SH7751R_CACHE_FLUSH() SH4_EMODE_CACHE_FLUSH() 148 #endif 149 150 #ifndef _LOCORE 151 extern void sh4_cache_config(void); 152 #endif 153 #endif /* _KERNEL */ 154 #endif /* !_SH3_CACHE_SH4_H_ */ 155
Indexes created Sun Sep 28 07:09:56 GMT 2025