exception.h revision 1.1.2.2
1 1.1.2.2 nathanw /* $NetBSD: exception.h,v 1.1.2.2 2002/06/20 03:40:52 nathanw Exp $ */ 2 1.1 uch 3 1.1 uch /*- 4 1.1 uch * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 1.1 uch * All rights reserved. 6 1.1 uch * 7 1.1 uch * Redistribution and use in source and binary forms, with or without 8 1.1 uch * modification, are permitted provided that the following conditions 9 1.1 uch * are met: 10 1.1 uch * 1. Redistributions of source code must retain the above copyright 11 1.1 uch * notice, this list of conditions and the following disclaimer. 12 1.1 uch * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 uch * notice, this list of conditions and the following disclaimer in the 14 1.1 uch * documentation and/or other materials provided with the distribution. 15 1.1 uch * 3. All advertising materials mentioning features or use of this software 16 1.1 uch * must display the following acknowledgement: 17 1.1 uch * This product includes software developed by the NetBSD 18 1.1 uch * Foundation, Inc. and its contributors. 19 1.1 uch * 4. Neither the name of The NetBSD Foundation nor the names of its 20 1.1 uch * contributors may be used to endorse or promote products derived 21 1.1 uch * from this software without specific prior written permission. 22 1.1 uch * 23 1.1 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 24 1.1 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 25 1.1 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 26 1.1 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 27 1.1 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 1.1 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 1.1 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 1.1 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 1.1 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 1.1 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 1.1 uch * POSSIBILITY OF SUCH DAMAGE. 34 1.1 uch */ 35 1.1 uch 36 1.1 uch #ifndef _SH3_EXCEPTION_H_ 37 1.1 uch #define _SH3_EXCEPTION_H_ 38 1.1.2.2 nathanw /* 39 1.1.2.2 nathanw * SH3/SH4 Exception handling. 40 1.1.2.2 nathanw */ 41 1.1 uch #include <sh3/devreg.h> 42 1.1 uch 43 1.1.2.2 nathanw #ifdef _KERNEL 44 1.1.2.2 nathanw #define SH3_TRA 0xffffffd0 /* 32bit */ 45 1.1.2.2 nathanw #define SH3_EXPEVT 0xffffffd4 /* 32bit */ 46 1.1.2.2 nathanw #define SH3_INTEVT 0xffffffd8 /* 32bit */ 47 1.1.2.2 nathanw #define SH7709_INTEVT2 0xa4000000 /* 32bit */ 48 1.1.2.2 nathanw 49 1.1.2.2 nathanw #define SH4_TRA 0xff000020 /* 32bit */ 50 1.1.2.2 nathanw #define SH4_EXPEVT 0xff000024 /* 32bit */ 51 1.1.2.2 nathanw #define SH4_INTEVT 0xff000028 /* 32bit */ 52 1.1.2.2 nathanw 53 1.1.2.2 nathanw /* 54 1.1.2.2 nathanw * EXPEVT 55 1.1.2.2 nathanw */ 56 1.1.2.2 nathanw /* Reset exception */ 57 1.1.2.2 nathanw #define EXPEVT_RESET_POWER 0x000 /* Power-On reset */ 58 1.1.2.2 nathanw #define EXPEVT_RESET_MANUAL 0x020 /* Manual reset */ 59 1.1.2.2 nathanw #define EXPEVT_RESET_TLB_MULTI_HIT 0x140 /* SH4 only */ 60 1.1.2.2 nathanw 61 1.1.2.2 nathanw /* General exception */ 62 1.1.2.2 nathanw #define EXPEVT_TLB_MISS_LD 0x040 /* TLB miss (load) */ 63 1.1.2.2 nathanw #define EXPEVT_TLB_MISS_ST 0x060 /* TLB miss (store) */ 64 1.1.2.2 nathanw #define EXPEVT_TLB_MOD 0x080 /* Initial page write */ 65 1.1.2.2 nathanw #define EXPEVT_TLB_PROT_LD 0x0a0 /* Protection violation (load) */ 66 1.1.2.2 nathanw #define EXPEVT_TLB_PROT_ST 0x0c0 /* Protection violation (store)*/ 67 1.1.2.2 nathanw #define EXPEVT_ADDR_ERR_LD 0x0e0 /* Address error (load) */ 68 1.1.2.2 nathanw #define EXPEVT_ADDR_ERR_ST 0x100 /* Address error (store) */ 69 1.1.2.2 nathanw #define EXPEVT_FPU 0x120 /* FPU exception */ 70 1.1.2.2 nathanw #define EXPEVT_TRAPA 0x160 /* Unconditional trap (TRAPA) */ 71 1.1.2.2 nathanw #define EXPEVT_RES_INST 0x180 /* Illegal instruction */ 72 1.1.2.2 nathanw #define EXPEVT_SLOT_INST 0x1a0 /* Illegal slot instruction */ 73 1.1.2.2 nathanw #define EXPEVT_BREAK 0x1e0 /* User break */ 74 1.1.2.2 nathanw #define EXPEVT_FPU_DISABLE 0x800 /* FPU disabled */ 75 1.1.2.2 nathanw #define EXPEVT_FPU_SLOT_DISABLE 0x820 /* Slot FPU disabled */ 76 1.1.2.2 nathanw 77 1.1.2.2 nathanw /* Software bit */ 78 1.1.2.2 nathanw #define EXP_USER 0x001 /* exception from user-mode */ 79 1.1.2.2 nathanw 80 1.1.2.2 nathanw #define _SH_TRA_BREAK 0xc3 /* magic number for debugger */ 81 1.1 uch 82 1.1.2.2 nathanw /* 83 1.1.2.2 nathanw * INTEVT/INTEVT2 84 1.1.2.2 nathanw */ 85 1.1.2.2 nathanw /* External interrupt */ 86 1.1 uch #define SH_INTEVT_NMI 0x1c0 87 1.1 uch 88 1.1 uch #define SH_INTEVT_TMU0_TUNI0 0x400 89 1.1 uch #define SH_INTEVT_TMU1_TUNI1 0x420 90 1.1 uch #define SH_INTEVT_TMU2_TUNI2 0x440 91 1.1 uch #define SH_INTEVT_TMU2_TICPI2 0x460 92 1.1 uch 93 1.1 uch #define SH_INTEVT_SCI_ERI 0x4e0 94 1.1 uch #define SH_INTEVT_SCI_RXI 0x500 95 1.1 uch #define SH_INTEVT_SCI_TXI 0x520 96 1.1 uch #define SH_INTEVT_SCI_TEI 0x540 97 1.1 uch 98 1.1 uch #define SH_INTEVT_WDT_ITI 0x560 99 1.1 uch 100 1.1 uch #define SH_INTEVT_IRL9 0x320 101 1.1 uch #define SH_INTEVT_IRL11 0x360 102 1.1 uch #define SH_INTEVT_IRL13 0x3a0 103 1.1 uch 104 1.1 uch #define SH4_INTEVT_SCIF_ERI 0x700 105 1.1 uch #define SH4_INTEVT_SCIF_RXI 0x720 106 1.1 uch #define SH4_INTEVT_SCIF_BRI 0x740 107 1.1 uch #define SH4_INTEVT_SCIF_TXI 0x760 108 1.1 uch 109 1.1 uch #define SH7709_INTEVT2_SCIF_ERI 0x900 110 1.1 uch #define SH7709_INTEVT2_SCIF_RXI 0x920 111 1.1 uch #define SH7709_INTEVT2_SCIF_BRI 0x940 112 1.1 uch #define SH7709_INTEVT2_SCIF_TXI 0x960 113 1.1 uch 114 1.1 uch #define SH7709_INTEVT2_IRQ4 0x680 115 1.1 uch 116 1.1 uch #ifndef _LOCORE 117 1.1 uch #if defined(SH3) && defined(SH4) 118 1.1 uch extern u_int32_t __sh_TRA; 119 1.1 uch extern u_int32_t __sh_EXPEVT; 120 1.1 uch extern u_int32_t __sh_INTEVT; 121 1.1 uch #endif /* SH3 && SH4 */ 122 1.1 uch #endif /* !_LOCORE */ 123 1.1.2.2 nathanw #endif /* _KERNEL */ 124 1.1 uch #endif /* !_SH3_EXCEPTION_H_ */ 125
Indexes created Wed Oct 01 19:09:53 GMT 2025