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      1 /*	$NetBSD: ubcreg.h,v 1.5 2008/06/06 03:17:28 uwe Exp $	*/
      2 
      3 /*-
      4  * Copyright (C) 1999 SAITOH Masanobu.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. The name of the author may not be used to endorse or promote products
     15  *    derived from this software without specific prior written permission.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
     26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _SH3_UBCREG_H_
     30 #define	_SH3_UBCREG_H_
     31 #include <sh3/devreg.h>
     32 
     33 /*
     34  * User Break Controller
     35  */
     36 
     37 /* Channel A */
     38 #define	SH3_BARA		0xffffffb0 /* 32: address */
     39 #define	SH3_BAMRA		0xffffffb4 /* 32: address mask */
     40 #define	SH3_BASRA		0xffffffe4 /* 16: ASID */
     41 #define	SH3_BBRA		0xffffffb8 /* 16: bus cycle */
     42 /* Channel B */
     43 #define	SH3_BARB		0xffffffa0 /* 32: address */
     44 #define	SH3_BAMRB		0xffffffa4 /* 32: address mask */
     45 #define	SH3_BDRB		0xffffff90 /* 32: data */
     46 #define	SH3_BDMRB		0xffffff94 /* 32: data mask */
     47 #define	SH3_BASRB		0xffffffe8 /* 16: asid */
     48 #define	SH3_BBRB		0xffffffa8 /* 16: bus cycle */
     49 /* Common */
     50 #define	SH3_BRCR		0xffffff98 /* 32: control */
     51 
     52 
     53 /* Channel A */
     54 #define	SH4_BARA		0xff200000 /* 32: address */
     55 #define	SH4_BAMRA		0xff200004 /*  8: address/asid mask */
     56 #define	SH4_BASRA		0xff000014 /*  8: ASID */
     57 #define	SH4_BBRA		0xff200008 /* 16: bus cycle */
     58 
     59 /* Channel B */
     60 #define	SH4_BARB		0xff20000c /* 32: address */
     61 #define	SH4_BAMRB		0xff200010 /*  8: address/asid mask */
     62 #define	SH4_BASRB		0xff000018 /*  8: ASID */
     63 #define	SH4_BDRB		0xff200018 /* 32: data */
     64 #define	SH4_BDMRB		0xff20001c /* 32: data mask */
     65 #define	SH4_BBRB		0xff200014 /* 16: bus cycle */
     66 /* common */
     67 #define	SH4_BRCR		0xff200020 /* 16: control */
     68 
     69 
     70 /* SH4_BAMRx bits (sh3 uses plain 32-bit address mask) */
     71 #define SH4_UBC_MASK_ASID	0x04 		/* ignore BASRx */
     72 #define SH4_UBC_MASK_MASK	0x0b		/* mask BARx: */
     73 #define SH4_UBC_MASK_NONE		0x00	/* - compare all bits */
     74 #define SH4_UBC_MASK_10			0x01	/* - mask lower 10 bits */
     75 #define SH4_UBC_MASK_12			0x02	/* - mask lower 12 bits */
     76 #define SH4_UBC_MASK_ALL		0x03	/* - mask all bits */
     77 #define SH4_UBC_MASK_16			0x08	/* - mask lower 16 bits */
     78 #define SH4_UBC_MASK_20			0x09	/* - mask lower 20 bits */
     79 
     80 /* BBRx bits */
     81 #define SH3_UBC_CYCLE_SZ_MASK	0x03 /* exclusive */
     82 #define SH4_UBC_CYCLE_SZ_MASK	0x43
     83 #define UBC_CYCLE_8			0x01
     84 #define UBC_CYCLE_16			0x02
     85 #define UBC_CYCLE_32			0x03
     86 #define SH4_UBC_CYCLE_64		0x40
     87 #define UBC_CYCLE_RW_MASK	0x0c /* can be combined */
     88 #define UBC_CYCLE_READ			0x04
     89 #define UBC_CYCLE_WRITE			0x08
     90 #define UBC_CYCLE_ID_MASK	0x30 /* can be combined */
     91 #define UBC_CYCLE_INSN			0x10
     92 #define UBC_CYCLE_DATA			0x20
     93 #define SH3_UBC_CYCLE_CD_MASK	0xc0 /* exclusive */
     94 #define SH3_UBC_CYCLE_CPU		0x40
     95 #define SH3_UBC_CYCLE_DMAC		0x80
     96 
     97 /* BRCR bits */
     98 #define UBC_CTL_SEQ			0x0008 /* A||B vs A&&B */
     99 #define UBC_CTL_B_AFTER_INSN		0x0040 /* B: before/after execution */
    100 #define UBC_CTL_B_DATA			0x0080 /* B: match BDRB/BDMRB */
    101 #define UBC_CTL_A_AFTER_INSN		0x0400 /* A: before/after execution */
    102 #define UBC_CTL_B_MATCH			0x4000 /* B matched (sh3: cpu) */
    103 #define UBC_CTL_A_MATCH			0x8000 /* A matched (sh3: cpu) */
    104 #define SH3_UBC_CTL_B_MASK_ASID	    0x00100000 /* ignore BASRB */
    105 #define SH3_UBC_CTL_A_MASK_ASID	    0x00200000 /* ignore BASRA */
    106 
    107 
    108 #ifndef _LOCORE
    109 #if defined(SH3) && defined(SH4)
    110 extern uint32_t __sh_BARA;
    111 extern uint32_t __sh_BAMRA;
    112 extern uint32_t __sh_BASRA;
    113 extern uint32_t __sh_BBRA;
    114 extern uint32_t __sh_BARB;
    115 extern uint32_t __sh_BAMRB;
    116 extern uint32_t __sh_BASRB;
    117 extern uint32_t __sh_BBRB;
    118 extern uint32_t __sh_BDRB;
    119 extern uint32_t __sh_BDMRB;
    120 extern uint32_t __sh_BRCR;
    121 #endif /* SH3 && SH4 */
    122 #endif /* !_LOCORE */
    123 
    124 #endif	/* !_SH3_UBCREG_H_ */
    125