Home | History | Annotate | Line # | Download | only in isa
      1 /*	$NetBSD: isa_io_asm.S,v 1.4 2008/04/28 20:23:35 martin Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1997 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Mark Brinicombe.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * Copyright 1997
     34  * Digital Equipment Corporation. All rights reserved.
     35  *
     36  * This software is furnished under license and may be used and
     37  * copied only in accordance with the following terms and conditions.
     38  * Subject to these conditions, you may download, copy, install,
     39  * use, modify and distribute this software in source and/or binary
     40  * form. No title or ownership is transferred hereby.
     41  *
     42  * 1) Any source code used, modified or distributed must reproduce
     43  *    and retain this copyright notice and list of conditions as
     44  *    they appear in the source file.
     45  *
     46  * 2) No right is granted to use any trade name, trademark, or logo of
     47  *    Digital Equipment Corporation. Neither the "Digital Equipment
     48  *    Corporation" name nor any trademark or logo of Digital Equipment
     49  *    Corporation may be used to endorse or promote products derived
     50  *    from this software without the prior written permission of
     51  *    Digital Equipment Corporation.
     52  *
     53  * 3) This software is provided "AS-IS" and any express or implied
     54  *    warranties, including but not limited to, any implied warranties
     55  *    of merchantability, fitness for a particular purpose, or
     56  *    non-infringement are disclaimed. In no event shall DIGITAL be
     57  *    liable for any damages whatsoever, and in particular, DIGITAL
     58  *    shall not be liable for special, indirect, consequential, or
     59  *    incidental damages or damages for lost profits, loss of
     60  *    revenue or loss of use, whether such damages arise in contract,
     61  *    negligence, tort, under statute, in equity, at law or otherwise,
     62  *    even if advised of the possibility of such damage.
     63  */
     64 
     65 /*
     66  * bus_space I/O functions for isa
     67  */
     68 
     69 #include <machine/asm.h>
     70 
     71 #ifdef GPROF
     72 #define	PAUSE	nop ; nop ; nop ; nop ; nop
     73 #else
     74 #define	PAUSE
     75 #endif
     76 
     77 /*
     78  * Note these functions use ARM Architecture V4 instructions as
     79  * all current systems with ISA will be using processors that support
     80  * V4 or later architectures (SHARK & CATS)
     81  */
     82 
     83 /*
     84  * read single
     85  */
     86 
     87 ENTRY(isa_bs_r_1)
     88 	ldrb	r0, [r1, r2]
     89 	PAUSE
     90 	mov	pc, lr
     91 
     92 ENTRY(isa_bs_r_2)
     93 	ldrh	r0, [r1, r2]	/*.word	0xe19100b2*/
     94 	PAUSE
     95 	mov	pc, lr
     96 
     97 ENTRY(isa_bs_r_4)
     98 	ldr	r0, [r1, r2]
     99 	PAUSE
    100 	mov	pc, lr
    101 
    102 /*
    103  * read multiple.
    104  */
    105 
    106 ENTRY(isa_bs_rm_1)
    107 	add	r0, r1, r2
    108 	mov	r1, r3
    109 	ldr	r2, [sp, #0]
    110 	teq	r2, #0
    111 	moveq	pc, lr
    112 
    113 Lisa_rm_1_loop:
    114 	ldrb	r3, [r0]
    115 	strb	r3, [r1], #1
    116 	subs	r2, r2, #1
    117 	bne	Lisa_rm_1_loop
    118 
    119 	mov	pc, lr
    120 
    121 ENTRY(isa_bs_rm_2)
    122 	add	r0, r1, r2
    123 	mov	r1, r3
    124 	ldr	r2, [sp, #0]
    125 	teq	r2, #0
    126 	moveq	pc, lr
    127 
    128 Lisa_rm_2_loop:
    129 	ldrh	r3, [r0]	/*.word 0xe1d030b0*/
    130 	strh	r3, [r1], #2	/*.word 0xe0c130b2*/
    131 	subs	r2, r2, #1
    132 	bne	Lisa_rm_2_loop
    133 
    134 	mov	pc, lr
    135 
    136 ENTRY(isa_bs_rm_4)
    137 	add	r0, r1, r2
    138 	mov	r1, r3
    139 	ldr	r2, [sp, #0]
    140 	teq	r2, #0
    141 	moveq	pc, lr
    142 
    143 Lisa_rm_4_loop:
    144 	ldr	r3, [r0]
    145 	str	r3, [r1], #4
    146 	subs	r2, r2, #1
    147 	bne	Lisa_rm_4_loop
    148 
    149 	mov	pc, lr
    150 
    151 /*
    152  * read region.
    153  */
    154 
    155 ENTRY(isa_bs_rr_1)
    156 	add	r0, r1, r2
    157 	mov	r1, r3
    158 	ldr	r2, [sp, #0]
    159 	teq	r2, #0
    160 	moveq	pc, lr
    161 
    162 Lisa_rr_1_loop:
    163 	ldrb	r3, [r0], #1
    164 	strb	r3, [r1], #1
    165 	subs	r2, r2, #1
    166 	bne	Lisa_rr_1_loop
    167 
    168 	mov	pc, lr
    169 
    170 ENTRY(isa_bs_rr_2)
    171 	add	r0, r1, r2
    172 	mov	r1, r3
    173 	ldr	r2, [sp, #0]
    174 	teq	r2, #0
    175 	moveq	pc, lr
    176 
    177 Lisa_rr_2_loop:
    178 	ldrh	r3, [r0], #2
    179 	strh	r3, [r1], #2	/*.word 0xe0c130b2*/
    180 	subs	r2, r2, #1
    181 	bne	Lisa_rr_2_loop
    182 
    183 	mov	pc, lr
    184 
    185 ENTRY(isa_bs_rr_4)
    186 	add	r0, r1, r2
    187 	mov	r1, r3
    188 	ldr	r2, [sp, #0]
    189 	teq	r2, #0
    190 	moveq	pc, lr
    191 
    192 Lisa_rr_4_loop:
    193 	ldr	r3, [r0], #4
    194 	str	r3, [r1], #4
    195 	subs	r2, r2, #1
    196 	bne	Lisa_rr_4_loop
    197 
    198 	mov	pc, lr
    199 
    200 /*
    201  * write single
    202  */
    203 
    204 ENTRY(isa_bs_w_1)
    205 	strb	r3, [r1, r2]
    206 	PAUSE
    207 	mov	pc, lr
    208 
    209 ENTRY(isa_bs_w_2)
    210 	strh	r3, [r1, r2]	/*.word 0xe18130b2*/
    211 	PAUSE
    212 	mov	pc, lr
    213 
    214 ENTRY(isa_bs_w_4)
    215 	str	r3, [r1, r2]
    216 	PAUSE
    217 	mov	pc, lr
    218 
    219 /*
    220  * write multiple
    221  */
    222 
    223 ENTRY(isa_bs_wm_1)
    224 	add	r0, r1, r2
    225 	mov	r1, r3
    226 	ldr	r2, [sp, #0]
    227 	teq	r2, #0
    228 	moveq	pc, lr
    229 
    230 Lisa_wm_1_loop:
    231 	ldrb	r3, [r1], #1
    232 	strb	r3, [r0]
    233 	subs	r2, r2, #1
    234 	bne	Lisa_wm_1_loop
    235 
    236 	mov	pc, lr
    237 
    238 ENTRY(isa_bs_wm_2)
    239 	add	r0, r1, r2
    240 	mov	r1, r3
    241 	ldr	r2, [sp, #0]
    242 	teq	r2, #0
    243 	moveq	pc, lr
    244 
    245 Lisa_wm_2_loop:
    246 	ldrh	r3, [r1], #2	/*.word 0xe0d130b2*/
    247 	strh	r3, [r0]	/*.word 0xe1c030b0*/
    248 	subs	r2, r2, #1
    249 	bne	Lisa_wm_2_loop
    250 
    251 	mov	pc, lr
    252 
    253 ENTRY(isa_bs_wm_4)
    254 	add	r0, r1, r2
    255 	mov	r1, r3
    256 	ldr	r2, [sp, #0]
    257 	teq	r2, #0
    258 	moveq	pc, lr
    259 
    260 Lisa_wm_4_loop:
    261 	ldr	r3, [r1], #4
    262 	str	r3, [r0]
    263 	subs	r2, r2, #1
    264 	bne	Lisa_wm_4_loop
    265 
    266 	mov	pc, lr
    267 
    268 
    269 /*
    270  * write region.
    271  */
    272 
    273 ENTRY(isa_bs_wr_1)
    274 	add	r0, r1, r2
    275 	mov	r1, r3
    276 	ldr	r2, [sp, #0]
    277 	teq	r2, #0
    278 	moveq	pc, lr
    279 
    280 Lisa_wr_1_loop:
    281 	ldrb	r3, [r1], #1
    282 	strb	r3, [r0], #1
    283 	subs	r2, r2, #1
    284 	bne	Lisa_wr_1_loop
    285 
    286 	mov	pc, lr
    287 
    288 ENTRY(isa_bs_wr_2)
    289 	add	r0, r1, r2
    290 	mov	r1, r3
    291 	ldr	r2, [sp, #0]
    292 	teq	r2, #0
    293 	moveq	pc, lr
    294 
    295 Lisa_wr_2_loop:
    296 	ldrh	r3, [r1], #2	/*.word 0xe0d130b2*/
    297 	strh	r3, [r0], #2
    298 	subs	r2, r2, #1
    299 	bne	Lisa_wr_2_loop
    300 
    301 	mov	pc, lr
    302 
    303 ENTRY(isa_bs_wr_4)
    304 	add	r0, r1, r2
    305 	mov	r1, r3
    306 	ldr	r2, [sp, #0]
    307 	teq	r2, #0
    308 	moveq	pc, lr
    309 
    310 Lisa_wr_4_loop:
    311 	ldr	r3, [r1], #4
    312 	str	r3, [r0], #4
    313 	subs	r2, r2, #1
    314 	bne	Lisa_wr_4_loop
    315 
    316 	mov	pc, lr
    317 
    318 /*
    319  * Set region
    320  */
    321 
    322 ENTRY(isa_bs_sr_2)
    323 	add	r0, r1, r2
    324 	mov	r1, r3
    325 	ldr	r2, [sp, #0]
    326 	teq	r2, #0
    327 	moveq	pc, lr
    328 
    329 Lisa_bs_sr_2_loop:
    330 	strh	r1, [r0], #2		/*.word e0c010b2*/
    331 	subs	r2, r2, #1
    332 	bne	Lisa_bs_sr_2_loop
    333 
    334 	mov	pc, lr
    335 
    336 /*
    337  * Copy region
    338  */
    339 
    340 ENTRY(isa_bs_c_2)
    341 	add	r0, r1, r2
    342 	ldr	r2, [sp, #0]
    343 	add	r1, r2, r3
    344 	ldr	r2, [sp, #4]
    345 	teq	r2, #0
    346 	moveq	pc, lr
    347 
    348 	cmp	r0, r1
    349 	blt	2f
    350 
    351 1:	ldrh	r3, [r0], #2
    352 	strh	r3, [r1], #2
    353 	subs	r2, r2, #1
    354 	bne	1b
    355 
    356 	mov	pc, lr
    357 
    358 2:	add	r0, r0, r2, lsl #1
    359 	add	r1, r1, r2, lsl #1
    360 	sub	r0, r0, #2
    361 	sub	r1, r1, #2
    362 
    363 3:	ldrh	r3, [r0], #-2
    364 	strh	r3, [r1], #-2
    365 	subs	r2, r2, #1
    366 	bne	3b
    367 
    368 	mov	pc, lr
    369