isa_io_asm.S revision 1.1
1 /* $NetBSD: isa_io_asm.S,v 1.1 2002/02/10 01:57:53 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Mark Brinicombe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright 1997 41 * Digital Equipment Corporation. All rights reserved. 42 * 43 * This software is furnished under license and may be used and 44 * copied only in accordance with the following terms and conditions. 45 * Subject to these conditions, you may download, copy, install, 46 * use, modify and distribute this software in source and/or binary 47 * form. No title or ownership is transferred hereby. 48 * 49 * 1) Any source code used, modified or distributed must reproduce 50 * and retain this copyright notice and list of conditions as 51 * they appear in the source file. 52 * 53 * 2) No right is granted to use any trade name, trademark, or logo of 54 * Digital Equipment Corporation. Neither the "Digital Equipment 55 * Corporation" name nor any trademark or logo of Digital Equipment 56 * Corporation may be used to endorse or promote products derived 57 * from this software without the prior written permission of 58 * Digital Equipment Corporation. 59 * 60 * 3) This software is provided "AS-IS" and any express or implied 61 * warranties, including but not limited to, any implied warranties 62 * of merchantability, fitness for a particular purpose, or 63 * non-infringement are disclaimed. In no event shall DIGITAL be 64 * liable for any damages whatsoever, and in particular, DIGITAL 65 * shall not be liable for special, indirect, consequential, or 66 * incidental damages or damages for lost profits, loss of 67 * revenue or loss of use, whether such damages arise in contract, 68 * negligence, tort, under statute, in equity, at law or otherwise, 69 * even if advised of the possibility of such damage. 70 */ 71 72 /* 73 * bus_space I/O functions for isa 74 */ 75 76 #include <machine/asm.h> 77 78 #ifdef GPROF 79 #define PAUSE nop ; nop ; nop ; nop ; nop 80 #else 81 #define PAUSE 82 #endif 83 84 /* 85 * Note these functions use ARM Architecture V4 instructions as 86 * all current systems with ISA will be using processors that support 87 * V4 or later architectures (SHARK & CATS) 88 */ 89 90 /* 91 * read single 92 */ 93 94 ENTRY(isa_bs_r_1) 95 ldrb r0, [r1, r2] 96 PAUSE 97 mov pc, lr 98 99 ENTRY(isa_bs_r_2) 100 ldrh r0, [r1, r2] /*.word 0xe19100b2*/ 101 PAUSE 102 mov pc, lr 103 104 ENTRY(isa_bs_r_4) 105 ldr r0, [r1, r2] 106 PAUSE 107 mov pc, lr 108 109 /* 110 * read multiple. 111 */ 112 113 ENTRY(isa_bs_rm_1) 114 add r0, r1, r2 115 mov r1, r3 116 ldr r2, [sp, #0] 117 teq r2, #0 118 moveq pc, lr 119 120 Lisa_rm_1_loop: 121 ldrb r3, [r0] 122 strb r3, [r1], #1 123 subs r2, r2, #1 124 bne Lisa_rm_1_loop 125 126 mov pc, lr 127 128 ENTRY(isa_bs_rm_2) 129 add r0, r1, r2 130 mov r1, r3 131 ldr r2, [sp, #0] 132 teq r2, #0 133 moveq pc, lr 134 135 Lisa_rm_2_loop: 136 ldrh r3, [r0] /*.word 0xe1d030b0*/ 137 strh r3, [r1], #2 /*.word 0xe0c130b2*/ 138 subs r2, r2, #1 139 bne Lisa_rm_2_loop 140 141 mov pc, lr 142 143 ENTRY(isa_bs_rm_4) 144 add r0, r1, r2 145 mov r1, r3 146 ldr r2, [sp, #0] 147 teq r2, #0 148 moveq pc, lr 149 150 Lisa_rm_4_loop: 151 ldr r3, [r0] 152 str r3, [r1], #4 153 subs r2, r2, #1 154 bne Lisa_rm_4_loop 155 156 mov pc, lr 157 158 /* 159 * read region. 160 */ 161 162 ENTRY(isa_bs_rr_1) 163 add r0, r1, r2 164 mov r1, r3 165 ldr r2, [sp, #0] 166 teq r2, #0 167 moveq pc, lr 168 169 Lisa_rr_1_loop: 170 ldrb r3, [r0], #1 171 strb r3, [r1], #1 172 subs r2, r2, #1 173 bne Lisa_rr_1_loop 174 175 mov pc, lr 176 177 ENTRY(isa_bs_rr_2) 178 add r0, r1, r2 179 mov r1, r3 180 ldr r2, [sp, #0] 181 teq r2, #0 182 moveq pc, lr 183 184 Lisa_rr_2_loop: 185 ldrh r3, [r0], #2 186 strh r3, [r1], #2 /*.word 0xe0c130b2*/ 187 subs r2, r2, #1 188 bne Lisa_rr_2_loop 189 190 mov pc, lr 191 192 ENTRY(isa_bs_rr_4) 193 add r0, r1, r2 194 mov r1, r3 195 ldr r2, [sp, #0] 196 teq r2, #0 197 moveq pc, lr 198 199 Lisa_rr_4_loop: 200 ldr r3, [r0], #4 201 str r3, [r1], #4 202 subs r2, r2, #1 203 bne Lisa_rr_4_loop 204 205 mov pc, lr 206 207 /* 208 * write single 209 */ 210 211 ENTRY(isa_bs_w_1) 212 strb r3, [r1, r2] 213 PAUSE 214 mov pc, lr 215 216 ENTRY(isa_bs_w_2) 217 strh r3, [r1, r2] /*.word 0xe18130b2*/ 218 PAUSE 219 mov pc, lr 220 221 ENTRY(isa_bs_w_4) 222 str r3, [r1, r2] 223 PAUSE 224 mov pc, lr 225 226 /* 227 * write multiple 228 */ 229 230 ENTRY(isa_bs_wm_1) 231 add r0, r1, r2 232 mov r1, r3 233 ldr r2, [sp, #0] 234 teq r2, #0 235 moveq pc, lr 236 237 Lisa_wm_1_loop: 238 ldrb r3, [r1], #1 239 strb r3, [r0] 240 subs r2, r2, #1 241 bne Lisa_wm_1_loop 242 243 mov pc, lr 244 245 ENTRY(isa_bs_wm_2) 246 add r0, r1, r2 247 mov r1, r3 248 ldr r2, [sp, #0] 249 teq r2, #0 250 moveq pc, lr 251 252 Lisa_wm_2_loop: 253 ldrh r3, [r1], #2 /*.word 0xe0d130b2*/ 254 strh r3, [r0] /*.word 0xe1c030b0*/ 255 subs r2, r2, #1 256 bne Lisa_wm_2_loop 257 258 mov pc, lr 259 260 ENTRY(isa_bs_wm_4) 261 add r0, r1, r2 262 mov r1, r3 263 ldr r2, [sp, #0] 264 teq r2, #0 265 moveq pc, lr 266 267 Lisa_wm_4_loop: 268 ldr r3, [r1], #4 269 str r3, [r0] 270 subs r2, r2, #1 271 bne Lisa_wm_4_loop 272 273 mov pc, lr 274 275 276 /* 277 * write region. 278 */ 279 280 ENTRY(isa_bs_wr_1) 281 add r0, r1, r2 282 mov r1, r3 283 ldr r2, [sp, #0] 284 teq r2, #0 285 moveq pc, lr 286 287 Lisa_wr_1_loop: 288 ldrb r3, [r1], #1 289 strb r3, [r0], #1 290 subs r2, r2, #1 291 bne Lisa_wr_1_loop 292 293 mov pc, lr 294 295 ENTRY(isa_bs_wr_2) 296 add r0, r1, r2 297 mov r1, r3 298 ldr r2, [sp, #0] 299 teq r2, #0 300 moveq pc, lr 301 302 Lisa_wr_2_loop: 303 ldrh r3, [r1], #2 /*.word 0xe0d130b2*/ 304 strh r3, [r0], #2 305 subs r2, r2, #1 306 bne Lisa_wr_2_loop 307 308 mov pc, lr 309 310 ENTRY(isa_bs_wr_4) 311 add r0, r1, r2 312 mov r1, r3 313 ldr r2, [sp, #0] 314 teq r2, #0 315 moveq pc, lr 316 317 Lisa_wr_4_loop: 318 ldr r3, [r1], #4 319 str r3, [r0], #4 320 subs r2, r2, #1 321 bne Lisa_wr_4_loop 322 323 mov pc, lr 324 325 /* 326 * Set region 327 */ 328 329 ENTRY(isa_bs_sr_2) 330 add r0, r1, r2 331 mov r1, r3 332 ldr r2, [sp, #0] 333 teq r2, #0 334 moveq pc, lr 335 336 Lisa_bs_sr_2_loop: 337 strh r1, [r0], #2 /*.word e0c010b2*/ 338 subs r2, r2, #1 339 bne Lisa_bs_sr_2_loop 340 341 mov pc, lr 342
Indexes created Tue Sep 30 20:09:53 GMT 2025