isa_irq.S revision 1.1.2.3
1 1.1.2.3 nathanw /* $NetBSD: isa_irq.S,v 1.1.2.3 2002/10/18 02:39:47 nathanw Exp $ */ 2 1.1.2.2 nathanw 3 1.1.2.2 nathanw /* 4 1.1.2.2 nathanw * Copyright 1997 5 1.1.2.2 nathanw * Digital Equipment Corporation. All rights reserved. 6 1.1.2.2 nathanw * 7 1.1.2.2 nathanw * This software is furnished under license and may be used and 8 1.1.2.2 nathanw * copied only in accordance with the following terms and conditions. 9 1.1.2.2 nathanw * Subject to these conditions, you may download, copy, install, 10 1.1.2.2 nathanw * use, modify and distribute this software in source and/or binary 11 1.1.2.2 nathanw * form. No title or ownership is transferred hereby. 12 1.1.2.2 nathanw * 13 1.1.2.2 nathanw * 1) Any source code used, modified or distributed must reproduce 14 1.1.2.2 nathanw * and retain this copyright notice and list of conditions as 15 1.1.2.2 nathanw * they appear in the source file. 16 1.1.2.2 nathanw * 17 1.1.2.2 nathanw * 2) No right is granted to use any trade name, trademark, or logo of 18 1.1.2.2 nathanw * Digital Equipment Corporation. Neither the "Digital Equipment 19 1.1.2.2 nathanw * Corporation" name nor any trademark or logo of Digital Equipment 20 1.1.2.2 nathanw * Corporation may be used to endorse or promote products derived 21 1.1.2.2 nathanw * from this software without the prior written permission of 22 1.1.2.2 nathanw * Digital Equipment Corporation. 23 1.1.2.2 nathanw * 24 1.1.2.2 nathanw * 3) This software is provided "AS-IS" and any express or implied 25 1.1.2.2 nathanw * warranties, including but not limited to, any implied warranties 26 1.1.2.2 nathanw * of merchantability, fitness for a particular purpose, or 27 1.1.2.2 nathanw * non-infringement are disclaimed. In no event shall DIGITAL be 28 1.1.2.2 nathanw * liable for any damages whatsoever, and in particular, DIGITAL 29 1.1.2.2 nathanw * shall not be liable for special, indirect, consequential, or 30 1.1.2.2 nathanw * incidental damages or damages for lost profits, loss of 31 1.1.2.2 nathanw * revenue or loss of use, whether such damages arise in contract, 32 1.1.2.2 nathanw * negligence, tort, under statute, in equity, at law or otherwise, 33 1.1.2.2 nathanw * even if advised of the possibility of such damage. 34 1.1.2.2 nathanw */ 35 1.1.2.2 nathanw 36 1.1.2.2 nathanw /* 37 1.1.2.2 nathanw * Copyright (c) 1994-1998 Mark Brinicombe. 38 1.1.2.2 nathanw * Copyright (c) 1994 Brini. 39 1.1.2.2 nathanw * All rights reserved. 40 1.1.2.2 nathanw * 41 1.1.2.2 nathanw * This code is derived from software written for Brini by Mark Brinicombe 42 1.1.2.2 nathanw * 43 1.1.2.2 nathanw * Redistribution and use in source and binary forms, with or without 44 1.1.2.2 nathanw * modification, are permitted provided that the following conditions 45 1.1.2.2 nathanw * are met: 46 1.1.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 47 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer. 48 1.1.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 49 1.1.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 50 1.1.2.2 nathanw * documentation and/or other materials provided with the distribution. 51 1.1.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 52 1.1.2.2 nathanw * must display the following acknowledgement: 53 1.1.2.2 nathanw * This product includes software developed by Mark Brinicombe 54 1.1.2.2 nathanw * for the NetBSD Project. 55 1.1.2.2 nathanw * 4. The name of the company nor the name of the author may be used to 56 1.1.2.2 nathanw * endorse or promote products derived from this software without specific 57 1.1.2.2 nathanw * prior written permission. 58 1.1.2.2 nathanw * 59 1.1.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 1.1.2.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 1.1.2.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 1.1.2.2 nathanw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 1.1.2.2 nathanw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 1.1.2.2 nathanw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 1.1.2.2 nathanw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 1.1.2.2 nathanw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 1.1.2.2 nathanw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 1.1.2.2 nathanw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 1.1.2.2 nathanw * 70 1.1.2.2 nathanw * from: irq.S 71 1.1.2.2 nathanw * 72 1.1.2.2 nathanw * Low level irq and fiq handlers 73 1.1.2.2 nathanw * 74 1.1.2.2 nathanw * Created : 27/09/94 75 1.1.2.2 nathanw */ 76 1.1.2.2 nathanw 77 1.1.2.2 nathanw #include "opt_irqstats.h" 78 1.1.2.2 nathanw 79 1.1.2.2 nathanw #include "assym.h" 80 1.1.2.2 nathanw #include <machine/asm.h> 81 1.1.2.2 nathanw #include <machine/cpu.h> 82 1.1.2.2 nathanw #include <machine/frame.h> 83 1.1.2.2 nathanw #include <dev/isa/isareg.h> 84 1.1.2.2 nathanw #include <shark/isa/icu.h> 85 1.1.2.2 nathanw #include <machine/irqhandler.h> 86 1.1.2.2 nathanw 87 1.1.2.2 nathanw .text 88 1.1.2.2 nathanw .align 0 89 1.1.2.2 nathanw 90 1.1.2.2 nathanw /* 91 1.1.2.2 nathanw * 92 1.1.2.2 nathanw * irq_entry 93 1.1.2.2 nathanw * 94 1.1.2.2 nathanw * Main entry point for the IRQ vector 95 1.1.2.2 nathanw * 96 1.1.2.2 nathanw * This function reads the irq request bits in the IOMD registers 97 1.1.2.2 nathanw * IRQRQA, IRQRQB and DMARQ 98 1.1.2.2 nathanw * It then calls an installed handler for each bit that is set. 99 1.1.2.2 nathanw * The function stray_irqhandler is called if a handler is not defined 100 1.1.2.2 nathanw * for a particular interrupt. 101 1.1.2.2 nathanw * If a interrupt handler is found then it is called with r0 containing 102 1.1.2.2 nathanw * the argument defined in the handler structure. If the field ih_arg 103 1.1.2.2 nathanw * is zero then a pointer to the IRQ frame on the stack is passed instead. 104 1.1.2.2 nathanw */ 105 1.1.2.2 nathanw 106 1.1.2.2 nathanw Ldisabled_mask: 107 1.1.2.2 nathanw .word _C_LABEL(disabled_mask) 108 1.1.2.2 nathanw 109 1.1.2.2 nathanw Lcurrent_spl_level: 110 1.1.2.2 nathanw .word _C_LABEL(current_spl_level) 111 1.1.2.2 nathanw 112 1.1.2.2 nathanw Lcurrent_intr_depth: 113 1.1.2.2 nathanw .word _C_LABEL(current_intr_depth) 114 1.1.2.2 nathanw 115 1.1.2.2 nathanw Lvam_io_data: 116 1.1.2.2 nathanw .word _C_LABEL(isa_io_bs_tag) 117 1.1.2.2 nathanw 118 1.1.2.2 nathanw Lspl_masks: 119 1.1.2.2 nathanw .word _C_LABEL(spl_masks) 120 1.1.2.2 nathanw 121 1.1.2.2 nathanw /* 122 1.1.2.2 nathanw * Register usage 123 1.1.2.2 nathanw * 124 1.1.2.2 nathanw * r6 - Address of current handler 125 1.1.2.2 nathanw * r7 - Pointer to handler pointer list 126 1.1.2.2 nathanw * r8 - Current IRQ requests. 127 1.1.2.2 nathanw * r9 - Used to count through possible IRQ bits. 128 1.1.2.2 nathanw * r10 - Base address of IOMD 129 1.1.2.2 nathanw */ 130 1.1.2.2 nathanw 131 1.1.2.2 nathanw /* Some documentation is in isa_machdep.c */ 132 1.1.2.2 nathanw ASENTRY_NP(irq_entry) 133 1.1.2.2 nathanw sub lr, lr, #0x00000004 /* Adjust the lr */ 134 1.1.2.2 nathanw 135 1.1.2.2 nathanw PUSHFRAMEINSVC /* Push an interrupt frame */ 136 1.1.2.2 nathanw 137 1.1.2.2 nathanw /* Load r8 with the ISA 8259 irqs */ 138 1.1.2.2 nathanw /* r8 <- irq's pending [15:0] */ 139 1.1.2.2 nathanw 140 1.1.2.2 nathanw /* address of 8259 #1 */ 141 1.1.2.2 nathanw ldr r0, Lvam_io_data 142 1.1.2.2 nathanw ldr r0, [r0] 143 1.1.2.2 nathanw ldrb r8, [r0, #IO_ICU1] /* ocw3 = irr */ 144 1.1.2.2 nathanw 145 1.1.2.2 nathanw /* clear the IRR bits that are currently masked. */ 146 1.1.2.2 nathanw ldr r2, Li8259_mask 147 1.1.2.2 nathanw ldr r2, [r2] 148 1.1.2.2 nathanw mvn r2, r2 /* disabled -> enabled */ 149 1.1.2.2 nathanw 150 1.1.2.2 nathanw /* address of 8259 #2 */ 151 1.1.2.2 nathanw tst r2, #(1 << IRQ_SLAVE) /* if slave is enabled */ 152 1.1.2.2 nathanw tstne r8, #(1 << IRQ_SLAVE) /* anything from slave? */ 153 1.1.2.2 nathanw ldrneb r1, [r0, #IO_ICU2] /* ocw3 = irr */ 154 1.1.2.2 nathanw orrne r8, r8, r1, lsl #8 155 1.1.2.2 nathanw 156 1.1.2.2 nathanw and r8, r8, r2 /* clear disabled */ 157 1.1.2.2 nathanw 158 1.1.2.2 nathanw /* clear IRQ 2, which is only used for slave 8259 */ 159 1.1.2.2 nathanw bic r8, r8, #(1 << IRQ_SLAVE) 160 1.1.2.2 nathanw 161 1.1.2.2 nathanw /* 162 1.1.2.2 nathanw * Note that we have entered the IRQ handler. 163 1.1.2.2 nathanw * We are in SVC mode so we cannot use the processor mode 164 1.1.2.2 nathanw * to determine if we are in an IRQ. Instead we will count the 165 1.1.2.2 nathanw * each time the interrupt handler is nested. 166 1.1.2.2 nathanw */ 167 1.1.2.2 nathanw 168 1.1.2.2 nathanw ldr r0, Lcurrent_intr_depth 169 1.1.2.2 nathanw ldr r1, [r0] 170 1.1.2.2 nathanw add r1, r1, #1 171 1.1.2.2 nathanw str r1, [r0] 172 1.1.2.2 nathanw 173 1.1.2.2 nathanw /* Block the current requested interrupts */ 174 1.1.2.2 nathanw 175 1.1.2.2 nathanw ldr r1, Ldisabled_mask 176 1.1.2.2 nathanw ldr r0, [r1] 177 1.1.2.2 nathanw stmfd sp!, {r0} 178 1.1.2.2 nathanw orr r0, r0, r8 179 1.1.2.2 nathanw 180 1.1.2.2 nathanw /* 181 1.1.2.2 nathanw * Need to block all interrupts at the IPL or lower for 182 1.1.2.2 nathanw * all asserted interrupts. 183 1.1.2.2 nathanw * This basically emulates hardware interrupt priority levels. 184 1.1.2.2 nathanw * Means we need to go through the interrupt mask and for 185 1.1.2.2 nathanw * every asserted interrupt we need to mask out all other 186 1.1.2.2 nathanw * interrupts at the same or lower IPL. 187 1.1.2.2 nathanw * If only we could wait until the main loop but we need to sort 188 1.1.2.2 nathanw * this out first so interrupts can be re-enabled. 189 1.1.2.2 nathanw * 190 1.1.2.2 nathanw * This would benefit from a special ffs type routine 191 1.1.2.2 nathanw */ 192 1.1.2.2 nathanw 193 1.1.2.2 nathanw mov r9, #(_SPL_LEVELS - 1) 194 1.1.2.2 nathanw ldr r7, Lspl_masks 195 1.1.2.2 nathanw 196 1.1.2.2 nathanw Lfind_highest_ipl: 197 1.1.2.2 nathanw ldr r2, [r7, r9, lsl #2] 198 1.1.2.2 nathanw tst r8, r2 199 1.1.2.2 nathanw subeq r9, r9, #1 200 1.1.2.2 nathanw beq Lfind_highest_ipl 201 1.1.2.2 nathanw 202 1.1.2.2 nathanw /* r9 = SPL level of highest priority interrupt */ 203 1.1.2.2 nathanw add r9, r9, #1 204 1.1.2.2 nathanw ldr r2, [r7, r9, lsl #2] 205 1.1.2.2 nathanw mvn r2, r2 206 1.1.2.2 nathanw orr r0, r0, r2 207 1.1.2.2 nathanw 208 1.1.2.2 nathanw str r0, [r1] 209 1.1.2.2 nathanw 210 1.1.2.2 nathanw ldr r0, Lcurrent_spl_level 211 1.1.2.2 nathanw ldr r1, [r0] 212 1.1.2.2 nathanw str r9, [r0] 213 1.1.2.2 nathanw stmfd sp!, {r1} 214 1.1.2.2 nathanw 215 1.1.2.2 nathanw /* Update the IOMD irq masks */ 216 1.1.2.2 nathanw bl _C_LABEL(irq_setmasks) 217 1.1.2.2 nathanw 218 1.1.2.2 nathanw mrs r0, cpsr_all /* Enable IRQ's */ 219 1.1.2.2 nathanw bic r0, r0, #I32_bit 220 1.1.2.2 nathanw msr cpsr_all, r0 221 1.1.2.2 nathanw 222 1.1.2.3 nathanw ldr r7, Lirqhandlers 223 1.1.2.2 nathanw mov r9, #0x00000001 224 1.1.2.2 nathanw 225 1.1.2.2 nathanw irqloop: 226 1.1.2.2 nathanw /* This would benefit from a special ffs type routine */ 227 1.1.2.2 nathanw tst r8, r9 /* Is a bit set ? */ 228 1.1.2.2 nathanw beq nextirq /* No ? try next bit */ 229 1.1.2.2 nathanw 230 1.1.2.2 nathanw ldr r6, [r7] /* Get address of first handler structure */ 231 1.1.2.2 nathanw 232 1.1.2.2 nathanw teq r6, #0x00000000 /* Do we have a handler */ 233 1.1.2.2 nathanw moveq r0, r8 /* IRQ requests as arg 0 */ 234 1.1.2.2 nathanw beq _C_LABEL(stray_irqhandler) /* call special handler */ 235 1.1.2.2 nathanw 236 1.1.2.2 nathanw ldr r0, Lcnt 237 1.1.2.2 nathanw ldr r1, [r0, #(V_INTR)] 238 1.1.2.2 nathanw add r1, r1, #0x00000001 239 1.1.2.2 nathanw str r1, [r0, #(V_INTR)] 240 1.1.2.2 nathanw 241 1.1.2.2 nathanw /* 242 1.1.2.2 nathanw * XXX: Should stats be accumlated for every interrupt routine called 243 1.1.2.2 nathanw * or for every physical interrupt that is serviced. 244 1.1.2.2 nathanw */ 245 1.1.2.2 nathanw 246 1.1.2.2 nathanw #ifdef IRQSTATS 247 1.1.2.2 nathanw ldr r0, Lintrcnt 248 1.1.2.2 nathanw ldr r1, [r6, #(IH_NUM)] 249 1.1.2.2 nathanw 250 1.1.2.2 nathanw add r0, r0, r1, lsl #2 251 1.1.2.2 nathanw ldr r1, [r0] 252 1.1.2.2 nathanw add r1, r1, #0x00000001 253 1.1.2.2 nathanw str r1, [r0] 254 1.1.2.2 nathanw #endif /* IRQSTATS */ 255 1.1.2.2 nathanw 256 1.1.2.2 nathanw irqchainloop: 257 1.1.2.2 nathanw ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */ 258 1.1.2.2 nathanw teq r0, #0x00000000 /* If arg is zero pass stack frame */ 259 1.1.2.2 nathanw addeq r0, sp, #8 /* ... stack frame */ 260 1.1.2.3 nathanw mov lr, pc /* return address */ 261 1.1.2.2 nathanw ldr pc, [r6, #(IH_FUNC)] /* Call handler */ 262 1.1.2.2 nathanw 263 1.1.2.2 nathanw teq r0, #0x00000001 /* Was the irq serviced ? */ 264 1.1.2.2 nathanw beq irqdone 265 1.1.2.2 nathanw 266 1.1.2.2 nathanw ldr r6, [r6, #(IH_NEXT)] 267 1.1.2.2 nathanw teq r6, #0x00000000 268 1.1.2.2 nathanw bne irqchainloop 269 1.1.2.2 nathanw 270 1.1.2.2 nathanw irqdone: 271 1.1.2.2 nathanw nextirq: 272 1.1.2.2 nathanw add r7, r7, #0x00000004 /* update pointer to handlers */ 273 1.1.2.2 nathanw mov r9, r9, lsl #1 /* move on to next bit */ 274 1.1.2.2 nathanw teq r9, #(1 << 16) /* done the last bit ? */ 275 1.1.2.2 nathanw bne irqloop /* no - loop back. */ 276 1.1.2.2 nathanw 277 1.1.2.2 nathanw ldmfd sp!, {r2} 278 1.1.2.2 nathanw ldr r1, Lcurrent_spl_level 279 1.1.2.2 nathanw str r2, [r1] 280 1.1.2.2 nathanw 281 1.1.2.2 nathanw /* Restore previous disabled mask */ 282 1.1.2.2 nathanw ldmfd sp!, {r2} 283 1.1.2.2 nathanw ldr r1, Ldisabled_mask 284 1.1.2.2 nathanw str r2, [r1] 285 1.1.2.2 nathanw bl _C_LABEL(irq_setmasks) 286 1.1.2.2 nathanw 287 1.1.2.2 nathanw bl _C_LABEL(dosoftints) /* Handle the soft interrupts */ 288 1.1.2.2 nathanw 289 1.1.2.2 nathanw /* Manage AST's. Maybe this should be done as a soft interrupt ? */ 290 1.1.2.2 nathanw ldr r0, [sp] /* Get the SPSR from stack */ 291 1.1.2.2 nathanw 292 1.1.2.2 nathanw and r0, r0, #(PSR_MODE) /* Test for USR32 mode before the IRQ */ 293 1.1.2.2 nathanw teq r0, #(PSR_USR32_MODE) 294 1.1.2.2 nathanw ldreq r0, Lastpending /* Do we have an AST pending ? */ 295 1.1.2.2 nathanw ldreq r1, [r0] 296 1.1.2.2 nathanw teqeq r1, #0x00000001 297 1.1.2.2 nathanw 298 1.1.2.2 nathanw beq irqast /* call the AST handler */ 299 1.1.2.2 nathanw 300 1.1.2.2 nathanw /* Kill IRQ's in preparation for exit */ 301 1.1.2.2 nathanw mrs r0, cpsr_all 302 1.1.2.2 nathanw orr r0, r0, #(I32_bit) 303 1.1.2.2 nathanw msr cpsr_all, r0 304 1.1.2.2 nathanw 305 1.1.2.2 nathanw /* Decrement the nest count */ 306 1.1.2.2 nathanw ldr r0, Lcurrent_intr_depth 307 1.1.2.2 nathanw ldr r1, [r0] 308 1.1.2.2 nathanw sub r1, r1, #1 309 1.1.2.2 nathanw str r1, [r0] 310 1.1.2.2 nathanw 311 1.1.2.2 nathanw PULLFRAMEFROMSVCANDEXIT 312 1.1.2.2 nathanw 313 1.1.2.2 nathanw /* NOT REACHED */ 314 1.1.2.2 nathanw b . - 8 315 1.1.2.2 nathanw 316 1.1.2.2 nathanw /* 317 1.1.2.2 nathanw * Ok, snag with current intr depth ... 318 1.1.2.2 nathanw * If ast() calls mi_sleep() the current_intr_depth will not be 319 1.1.2.2 nathanw * decremented until the process is woken up. This can result 320 1.1.2.2 nathanw * in the system believing it is still in the interrupt handler. 321 1.1.2.2 nathanw * If we are calling ast() then correct the current_intr_depth 322 1.1.2.2 nathanw * before the call. 323 1.1.2.2 nathanw */ 324 1.1.2.2 nathanw irqast: 325 1.1.2.2 nathanw mov r1, #0x00000000 /* Clear ast_pending */ 326 1.1.2.2 nathanw str r1, [r0] 327 1.1.2.2 nathanw 328 1.1.2.2 nathanw /* Kill IRQ's so we atomically decrement current_intr_depth */ 329 1.1.2.2 nathanw mrs r2, cpsr_all 330 1.1.2.2 nathanw orr r3, r2, #(I32_bit) 331 1.1.2.2 nathanw msr cpsr_all, r3 332 1.1.2.2 nathanw 333 1.1.2.2 nathanw /* Decrement the nest count */ 334 1.1.2.2 nathanw ldr r0, Lcurrent_intr_depth 335 1.1.2.2 nathanw ldr r1, [r0] 336 1.1.2.2 nathanw sub r1, r1, #1 337 1.1.2.2 nathanw str r1, [r0] 338 1.1.2.2 nathanw 339 1.1.2.2 nathanw /* Restore IRQ's */ 340 1.1.2.2 nathanw msr cpsr_all, r2 341 1.1.2.2 nathanw 342 1.1.2.2 nathanw mov r0, sp 343 1.1.2.2 nathanw bl _C_LABEL(ast) 344 1.1.2.2 nathanw 345 1.1.2.2 nathanw /* Kill IRQ's in preparation for exit */ 346 1.1.2.2 nathanw mrs r0, cpsr_all 347 1.1.2.2 nathanw orr r0, r0, #(I32_bit) 348 1.1.2.2 nathanw msr cpsr_all, r0 349 1.1.2.2 nathanw 350 1.1.2.2 nathanw PULLFRAMEFROMSVCANDEXIT 351 1.1.2.2 nathanw 352 1.1.2.2 nathanw /* NOT REACHED */ 353 1.1.2.2 nathanw b . - 8 354 1.1.2.2 nathanw 355 1.1.2.2 nathanw 356 1.1.2.2 nathanw Lspl_mask: 357 1.1.2.2 nathanw .word _C_LABEL(spl_mask) /* irq's allowed at current spl level */ 358 1.1.2.2 nathanw 359 1.1.2.2 nathanw Lcurrent_mask: 360 1.1.2.2 nathanw .word _C_LABEL(current_mask) /* irq's that are usable */ 361 1.1.2.2 nathanw 362 1.1.2.2 nathanw ENTRY(irq_setmasks) 363 1.1.2.2 nathanw /* Disable interrupts */ 364 1.1.2.2 nathanw mrs r3, cpsr_all 365 1.1.2.2 nathanw orr r1, r3, #(I32_bit) 366 1.1.2.2 nathanw msr cpsr_all, r1 367 1.1.2.2 nathanw 368 1.1.2.2 nathanw /* Calculate interrupt mask */ 369 1.1.2.2 nathanw ldr r1, Lcurrent_mask /* All the enabled interrupts */ 370 1.1.2.2 nathanw ldrh r1, [r1] /* get hardware bits of mask */ 371 1.1.2.2 nathanw /* .word 0xe0d110b0 */ /* hand-assembled ldrh r1, [r1] */ 372 1.1.2.2 nathanw ldr r2, Lspl_mask /* Block due to current spl level */ 373 1.1.2.2 nathanw ldr r2, [r2] 374 1.1.2.2 nathanw and r1, r1, r2 375 1.1.2.2 nathanw ldr r2, Ldisabled_mask /* Block due to active interrupts */ 376 1.1.2.2 nathanw ldr r2, [r2] 377 1.1.2.2 nathanw bic r1, r1, r2 378 1.1.2.2 nathanw 379 1.1.2.2 nathanw /* since 8259's are so slow to access, this code does everything 380 1.1.2.2 nathanw possible to avoid them */ 381 1.1.2.2 nathanw 382 1.1.2.2 nathanw /* get current mask: these are the bits */ 383 1.1.2.2 nathanw ldr r0, Li8259_mask 384 1.1.2.2 nathanw ldr r2, [r0] 385 1.1.2.2 nathanw /* r2 = 0000.0000.0000.0000.ZZZZ.ZZZZ.ZZZZ.ZZZZ */ 386 1.1.2.2 nathanw 387 1.1.2.2 nathanw /* see if there's anything enabled on 8259 #2 */ 388 1.1.2.2 nathanw tst r1, #0xff00 389 1.1.2.2 nathanw 390 1.1.2.2 nathanw biceq r1, r1, #(1 << IRQ_SLAVE) /* no, so disable it */ 391 1.1.2.2 nathanw orrne r1, r1, #(1 << IRQ_SLAVE) /* yes, so enable it */ 392 1.1.2.2 nathanw /* eq => r1 = 0000.0000.0000.0000.0000.0000.MMMM.M0MM 393 1.1.2.2 nathanw ne => r1 = 0000.0000.0000.0000.MMMM.MMMM.MMMM.M1MM */ 394 1.1.2.2 nathanw 395 1.1.2.2 nathanw /* 8259 bit high => disable */ 396 1.1.2.2 nathanw mvn r1, r1 397 1.1.2.2 nathanw /* eq => r1 = 1111.1111.1111.1111.1111.1111.YYYY.Y1YY 398 1.1.2.2 nathanw ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY 399 1.1.2.2 nathanw (for each bit position Y = !M) */ 400 1.1.2.2 nathanw 401 1.1.2.2 nathanw orreq r1, r2, r1, lsl #16 402 1.1.2.2 nathanw /* eq => r1 = 1111.1111.YYYY.Y1YY.ZZZZ.ZZZZ.ZZZZ.ZZZZ 403 1.1.2.2 nathanw ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY */ 404 1.1.2.2 nathanw orreq r1, r1, #0x000000FF 405 1.1.2.2 nathanw /* eq => r1 = 1111.1111.YYYY.Y1YY.ZZZZ.ZZZZ.1111.1111 406 1.1.2.2 nathanw ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY */ 407 1.1.2.2 nathanw and r1, r1, r1, lsr #16 408 1.1.2.2 nathanw /* eq => r1 = 0000.0000.0000.0000.ZZZZ.ZZZZ.YYYY.Y1YY 409 1.1.2.2 nathanw ne => r1 = 0000.0000.0000.0000.YYYY.YYYY.YYYY.Y0YY */ 410 1.1.2.2 nathanw 411 1.1.2.2 nathanw /* if old = new, don't bother to set again. 412 1.1.2.2 nathanw fast path to exit, since 8259's are so slow anyway */ 413 1.1.2.2 nathanw eors r2, r1, r2 /* which bits are different? */ 414 1.1.2.2 nathanw msreq cpsr_all, r3 /* no bits are different, return */ 415 1.1.2.2 nathanw moveq pc, lr 416 1.1.2.2 nathanw 417 1.1.2.2 nathanw /* have to set at least one of the 8259's, store new mask */ 418 1.1.2.2 nathanw str r1, [r0] 419 1.1.2.2 nathanw ldr r0, Lvam_io_data 420 1.1.2.2 nathanw ldr r0, [r0] 421 1.1.2.2 nathanw 422 1.1.2.2 nathanw /* see if there's any change for 8259 #1 (master) */ 423 1.1.2.2 nathanw tst r2, #0x00FF /* bottom 8 bits different? */ 424 1.1.2.2 nathanw strneb r1, [r0, #(IO_ICU1 + 1)] /* icu1 / ocw1 */ 425 1.1.2.2 nathanw 426 1.1.2.2 nathanw /* anything for 8259 #2? */ 427 1.1.2.2 nathanw tst r2, #0xFF00 428 1.1.2.2 nathanw mov r1, r1, lsr #8 /* next byte */ 429 1.1.2.2 nathanw strneb r1, [r0, #(IO_ICU2 + 1)] /* icu2 / ocw1 */ 430 1.1.2.2 nathanw 431 1.1.2.2 nathanw /* Restore old cpsr and exit */ 432 1.1.2.2 nathanw msr cpsr_all, r3 433 1.1.2.2 nathanw mov pc, lr 434 1.1.2.2 nathanw 435 1.1.2.2 nathanw Lcnt: 436 1.1.2.2 nathanw .word _C_LABEL(uvmexp) 437 1.1.2.2 nathanw 438 1.1.2.2 nathanw Lintrcnt: 439 1.1.2.2 nathanw .word _C_LABEL(intrcnt) 440 1.1.2.2 nathanw 441 1.1.2.2 nathanw Li8259_mask: 442 1.1.2.2 nathanw .word _C_LABEL(i8259_mask) 443 1.1.2.2 nathanw 444 1.1.2.2 nathanw Lirqhandlers: 445 1.1.2.2 nathanw .word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */ 446 1.1.2.2 nathanw 447 1.1.2.2 nathanw Lastpending: 448 1.1.2.2 nathanw .word _C_LABEL(astpending) 449 1.1.2.2 nathanw 450 1.1.2.2 nathanw #ifdef IRQSTATS 451 1.1.2.2 nathanw /* These symbols are used by vmstat */ 452 1.1.2.2 nathanw 453 1.1.2.2 nathanw .text 454 1.1.2.2 nathanw .global _C_LABEL(_intrnames) 455 1.1.2.2 nathanw _C_LABEL(_intrnames): 456 1.1.2.2 nathanw .word _C_LABEL(intrnames) 457 1.1.2.2 nathanw 458 1.1.2.2 nathanw .data 459 1.1.2.2 nathanw 460 1.1.2.2 nathanw /* XXX fix */ 461 1.1.2.2 nathanw .globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(sintrcnt), _C_LABEL(eintrcnt) 462 1.1.2.2 nathanw _C_LABEL(intrnames): 463 1.1.2.2 nathanw .asciz "interrupt 0 " 464 1.1.2.2 nathanw .asciz "interrupt 1 " 465 1.1.2.2 nathanw .asciz "interrupt 2 " 466 1.1.2.2 nathanw .asciz "interrupt 3 " 467 1.1.2.2 nathanw .asciz "interrupt 4 " 468 1.1.2.2 nathanw .asciz "interrupt 5 " 469 1.1.2.2 nathanw .asciz "interrupt 6 " 470 1.1.2.2 nathanw .asciz "interrupt 7 " 471 1.1.2.2 nathanw .asciz "interrupt 8 " 472 1.1.2.2 nathanw .asciz "interrupt 9 " 473 1.1.2.2 nathanw .asciz "interrupt 10 " 474 1.1.2.2 nathanw .asciz "interrupt 11 " 475 1.1.2.2 nathanw .asciz "interrupt 12 " 476 1.1.2.2 nathanw .asciz "interrupt 13 " 477 1.1.2.2 nathanw .asciz "interrupt 14 " 478 1.1.2.2 nathanw .asciz "interrupt 15 " 479 1.1.2.2 nathanw .asciz "interrupt 16 " 480 1.1.2.2 nathanw .asciz "interrupt 17 " 481 1.1.2.2 nathanw .asciz "interrupt 18 " 482 1.1.2.2 nathanw .asciz "interrupt 19 " 483 1.1.2.2 nathanw .asciz "interrupt 20 " 484 1.1.2.2 nathanw .asciz "interrupt 21 " 485 1.1.2.2 nathanw .asciz "interrupt 22 " 486 1.1.2.2 nathanw .asciz "interrupt 23 " 487 1.1.2.2 nathanw .asciz "interrupt 24 " 488 1.1.2.2 nathanw .asciz "interrupt 25 " 489 1.1.2.2 nathanw .asciz "interrupt 26 " 490 1.1.2.2 nathanw .asciz "interrupt 27 " 491 1.1.2.2 nathanw .asciz "interrupt 28 " 492 1.1.2.2 nathanw .asciz "interrupt 29 " 493 1.1.2.2 nathanw .asciz "interrupt 30 " 494 1.1.2.2 nathanw .asciz "interrupt 31 " 495 1.1.2.2 nathanw 496 1.1.2.2 nathanw _C_LABEL(sintrnames): 497 1.1.2.2 nathanw .asciz "soft int 0 " 498 1.1.2.2 nathanw .asciz "soft int 1 " 499 1.1.2.2 nathanw .asciz "soft int 2 " 500 1.1.2.2 nathanw .asciz "soft int 3 " 501 1.1.2.2 nathanw .asciz "soft int 4 " 502 1.1.2.2 nathanw .asciz "soft int 5 " 503 1.1.2.2 nathanw .asciz "soft int 6 " 504 1.1.2.2 nathanw .asciz "soft int 7 " 505 1.1.2.2 nathanw .asciz "soft int 8 " 506 1.1.2.2 nathanw .asciz "soft int 9 " 507 1.1.2.2 nathanw .asciz "soft int 10 " 508 1.1.2.2 nathanw .asciz "soft int 11 " 509 1.1.2.2 nathanw .asciz "soft int 12 " 510 1.1.2.2 nathanw .asciz "soft int 13 " 511 1.1.2.2 nathanw .asciz "soft int 14 " 512 1.1.2.2 nathanw .asciz "soft int 15 " 513 1.1.2.2 nathanw .asciz "soft int 16 " 514 1.1.2.2 nathanw .asciz "soft int 17 " 515 1.1.2.2 nathanw .asciz "soft int 18 " 516 1.1.2.2 nathanw .asciz "soft int 19 " 517 1.1.2.2 nathanw .asciz "soft int 20 " 518 1.1.2.2 nathanw .asciz "soft int 21 " 519 1.1.2.2 nathanw .asciz "soft int 22 " 520 1.1.2.2 nathanw .asciz "soft int 23 " 521 1.1.2.2 nathanw .asciz "soft int 24 " 522 1.1.2.2 nathanw .asciz "soft int 25 " 523 1.1.2.2 nathanw .asciz "soft int 26 " 524 1.1.2.2 nathanw .asciz "soft int 27 " 525 1.1.2.2 nathanw .asciz "soft int 28 " 526 1.1.2.2 nathanw .asciz "soft int 29 " 527 1.1.2.2 nathanw .asciz "soft int 30 " 528 1.1.2.2 nathanw .asciz "soft int 31 " 529 1.1.2.2 nathanw _C_LABEL(eintrnames): 530 1.1.2.2 nathanw 531 1.1.2.2 nathanw .bss 532 1.1.2.2 nathanw .align 0 533 1.1.2.2 nathanw _C_LABEL(intrcnt): 534 1.1.2.2 nathanw .space 32*4 /* XXX Should be linked to number of interrupts */ 535 1.1.2.2 nathanw _C_LABEL(sintrcnt): 536 1.1.2.2 nathanw .space 32*4 /* XXX Should be linked to number of soft ints */ 537 1.1.2.2 nathanw _C_LABEL(eintrcnt): 538 1.1.2.2 nathanw 539 1.1.2.2 nathanw #else /* IRQSTATS */ 540 1.1.2.2 nathanw /* Dummy entries to keep vmstat happy */ 541 1.1.2.2 nathanw 542 1.1.2.2 nathanw .text 543 1.1.2.2 nathanw .globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(eintrcnt) 544 1.1.2.2 nathanw _C_LABEL(intrnames): 545 1.1.2.2 nathanw .long 0 546 1.1.2.2 nathanw _C_LABEL(eintrnames): 547 1.1.2.2 nathanw 548 1.1.2.2 nathanw _C_LABEL(intrcnt): 549 1.1.2.2 nathanw .long 0 550 1.1.2.2 nathanw _C_LABEL(eintrcnt): 551 1.1.2.2 nathanw #endif /* IRQSTATS */ 552
Indexes created Tue Oct 14 11:09:46 GMT 2025