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isa_irq.S revision 1.1
      1 /*	$NetBSD: isa_irq.S,v 1.1 2002/02/10 01:57:54 thorpej Exp $	*/
      2 
      3 /*
      4  * Copyright 1997
      5  * Digital Equipment Corporation. All rights reserved.
      6  *
      7  * This software is furnished under license and may be used and
      8  * copied only in accordance with the following terms and conditions.
      9  * Subject to these conditions, you may download, copy, install,
     10  * use, modify and distribute this software in source and/or binary
     11  * form. No title or ownership is transferred hereby.
     12  *
     13  * 1) Any source code used, modified or distributed must reproduce
     14  *    and retain this copyright notice and list of conditions as
     15  *    they appear in the source file.
     16  *
     17  * 2) No right is granted to use any trade name, trademark, or logo of
     18  *    Digital Equipment Corporation. Neither the "Digital Equipment
     19  *    Corporation" name nor any trademark or logo of Digital Equipment
     20  *    Corporation may be used to endorse or promote products derived
     21  *    from this software without the prior written permission of
     22  *    Digital Equipment Corporation.
     23  *
     24  * 3) This software is provided "AS-IS" and any express or implied
     25  *    warranties, including but not limited to, any implied warranties
     26  *    of merchantability, fitness for a particular purpose, or
     27  *    non-infringement are disclaimed. In no event shall DIGITAL be
     28  *    liable for any damages whatsoever, and in particular, DIGITAL
     29  *    shall not be liable for special, indirect, consequential, or
     30  *    incidental damages or damages for lost profits, loss of
     31  *    revenue or loss of use, whether such damages arise in contract,
     32  *    negligence, tort, under statute, in equity, at law or otherwise,
     33  *    even if advised of the possibility of such damage.
     34  */
     35 
     36 /*
     37  * Copyright (c) 1994-1998 Mark Brinicombe.
     38  * Copyright (c) 1994 Brini.
     39  * All rights reserved.
     40  *
     41  * This code is derived from software written for Brini by Mark Brinicombe
     42  *
     43  * Redistribution and use in source and binary forms, with or without
     44  * modification, are permitted provided that the following conditions
     45  * are met:
     46  * 1. Redistributions of source code must retain the above copyright
     47  *    notice, this list of conditions and the following disclaimer.
     48  * 2. Redistributions in binary form must reproduce the above copyright
     49  *    notice, this list of conditions and the following disclaimer in the
     50  *    documentation and/or other materials provided with the distribution.
     51  * 3. All advertising materials mentioning features or use of this software
     52  *    must display the following acknowledgement:
     53  *	This product includes software developed by Mark Brinicombe
     54  *	for the NetBSD Project.
     55  * 4. The name of the company nor the name of the author may be used to
     56  *    endorse or promote products derived from this software without specific
     57  *    prior written permission.
     58  *
     59  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     60  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     61  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     62  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     63  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     64  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     65  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     66  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     67  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     68  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     69  *
     70  * 	from: irq.S
     71  *
     72  * Low level irq and fiq handlers
     73  *
     74  * Created      : 27/09/94
     75  */
     76 
     77 #include "opt_irqstats.h"
     78 
     79 #include "assym.h"
     80 #include <machine/asm.h>
     81 #include <machine/cpu.h>
     82 #include <machine/frame.h>
     83 #include <dev/isa/isareg.h>
     84 #include <shark/isa/icu.h>
     85 #include <machine/irqhandler.h>
     86 
     87 	.text
     88 	.align	0
     89 
     90 /*
     91  *
     92  * irq_entry
     93  *
     94  * Main entry point for the IRQ vector
     95  *
     96  * This function reads the irq request bits in the IOMD registers
     97  * IRQRQA, IRQRQB and DMARQ
     98  * It then calls an installed handler for each bit that is set.
     99  * The function stray_irqhandler is called if a handler is not defined
    100  * for a particular interrupt.
    101  * If a interrupt handler is found then it is called with r0 containing
    102  * the argument defined in the handler structure. If the field ih_arg
    103  * is zero then a pointer to the IRQ frame on the stack is passed instead.
    104  */
    105 
    106 Ldisabled_mask:
    107 	.word	_C_LABEL(disabled_mask)
    108 
    109 Lcurrent_spl_level:
    110 	.word	_C_LABEL(current_spl_level)
    111 
    112 Lcurrent_intr_depth:
    113 	.word	_C_LABEL(current_intr_depth)
    114 
    115 Lvam_io_data:
    116 	.word	_C_LABEL(isa_io_bs_tag)
    117 
    118 Lspl_masks:
    119 	.word	_C_LABEL(spl_masks)
    120 
    121 /*
    122  * Register usage
    123  *
    124  *  r6  - Address of current handler
    125  *  r7  - Pointer to handler pointer list
    126  *  r8  - Current IRQ requests.
    127  *  r9  - Used to count through possible IRQ bits.
    128  *  r10 - Base address of IOMD
    129  */
    130 
    131 /* Some documentation is in isa_machdep.c */
    132 ASENTRY_NP(irq_entry)
    133 	sub	lr, lr, #0x00000004	/* Adjust the lr */
    134 
    135 	PUSHFRAMEINSVC			/* Push an interrupt frame */
    136 
    137 	/* Load r8 with the ISA 8259 irqs */
    138 	/* r8 <- irq's pending [15:0] */
    139 
    140 	/* address of 8259 #1 */
    141 	ldr	r0, Lvam_io_data
    142 	ldr	r0, [r0]
    143 	ldrb	r8, [r0, #IO_ICU1]                /* ocw3 = irr */
    144 
    145 	/* clear the IRR bits that are currently masked. */
    146 	ldr	r2, Li8259_mask
    147 	ldr	r2, [r2]
    148 	mvn	r2, r2                            /* disabled -> enabled */
    149 
    150 	/* address of 8259 #2 */
    151 	tst	r2, #(1 << IRQ_SLAVE)             /* if slave is enabled */
    152 	tstne	r8, #(1 << IRQ_SLAVE)             /* anything from slave? */
    153 	ldrneb	r1, [r0, #IO_ICU2]                /* ocw3 = irr */
    154 	orrne	r8, r8, r1, lsl #8
    155 
    156 	and	r8, r8, r2                        /* clear disabled */
    157 
    158 	/* clear IRQ 2, which is only used for slave 8259 */
    159 	bic	r8, r8, #(1 << IRQ_SLAVE)
    160 
    161 	/*
    162 	 * Note that we have entered the IRQ handler.
    163 	 * We are in SVC mode so we cannot use the processor mode
    164 	 * to determine if we are in an IRQ. Instead we will count the
    165 	 * each time the interrupt handler is nested.
    166 	 */
    167 
    168 	ldr	r0, Lcurrent_intr_depth
    169 	ldr	r1, [r0]
    170 	add	r1, r1, #1
    171 	str	r1, [r0]
    172 
    173 	/* Block the current requested interrupts */
    174 
    175 	ldr	r1, Ldisabled_mask
    176 	ldr	r0, [r1]
    177 	stmfd	sp!, {r0}
    178 	orr	r0, r0, r8
    179 
    180 	/*
    181  	 * Need to block all interrupts at the IPL or lower for
    182 	 * all asserted interrupts.
    183 	 * This basically emulates hardware interrupt priority levels.
    184 	 * Means we need to go through the interrupt mask and for
    185 	 * every asserted interrupt we need to mask out all other
    186 	 * interrupts at the same or lower IPL.
    187 	 * If only we could wait until the main loop but we need to sort
    188 	 * this out first so interrupts can be re-enabled.
    189 	 *
    190 	 * This would benefit from a special ffs type routine
    191 	 */
    192 
    193 	mov	r9, #(_SPL_LEVELS - 1)
    194 	ldr	r7, Lspl_masks
    195 
    196 Lfind_highest_ipl:
    197 	ldr	r2, [r7, r9, lsl #2]
    198 	tst	r8, r2
    199 	subeq	r9, r9, #1
    200 	beq	Lfind_highest_ipl
    201 
    202 	/* r9 = SPL level of highest priority interrupt */
    203 	add	r9, r9, #1
    204 	ldr	r2, [r7, r9, lsl #2]
    205 	mvn	r2, r2
    206 	orr	r0, r0, r2
    207 
    208 	str	r0, [r1]
    209 
    210 	ldr	r0, Lcurrent_spl_level
    211 	ldr	r1, [r0]
    212 	str	r9, [r0]
    213 	stmfd	sp!, {r1}
    214 
    215 	/* Update the IOMD irq masks */
    216 	bl	_C_LABEL(irq_setmasks)
    217 
    218         mrs     r0, cpsr_all		/* Enable IRQ's */
    219 	bic	r0, r0, #I32_bit
    220 	msr	cpsr_all, r0
    221 
    222 	ldr	r7, [pc, #Lirqhandlers - . - 8]
    223         mov	r9, #0x00000001
    224 
    225 irqloop:
    226 	/* This would benefit from a special ffs type routine */
    227 	tst	r8, r9			/* Is a bit set ? */
    228 	beq	nextirq			/* No ? try next bit */
    229 
    230 	ldr	r6, [r7]		/* Get address of first handler structure */
    231 
    232 	teq	r6, #0x00000000		/* Do we have a handler */
    233 	moveq	r0, r8			/* IRQ requests as arg 0 */
    234 	beq	_C_LABEL(stray_irqhandler) /* call special handler */
    235 
    236 	ldr	r0, Lcnt
    237 	ldr	r1, [r0, #(V_INTR)]
    238 	add	r1, r1, #0x00000001
    239 	str	r1, [r0, #(V_INTR)]
    240 
    241 	/*
    242 	 * XXX: Should stats be accumlated for every interrupt routine called
    243 	 * or for every physical interrupt that is serviced.
    244 	 */
    245 
    246 #ifdef IRQSTATS
    247         ldr	r0, Lintrcnt
    248 	ldr	r1, [r6, #(IH_NUM)]
    249 
    250 	add	r0, r0, r1, lsl #2
    251 	ldr	r1, [r0]
    252 	add	r1, r1, #0x00000001
    253 	str	r1, [r0]
    254 #endif	/* IRQSTATS */
    255 
    256 irqchainloop:
    257 	add	lr, pc, #nextinchain - . - 8	/* return address */
    258 	ldr	r0, [r6, #(IH_ARG)]	/* Get argument pointer */
    259 	teq	r0, #0x00000000		/* If arg is zero pass stack frame */
    260 	addeq	r0, sp, #8		/* ... stack frame */
    261 	ldr	pc, [r6, #(IH_FUNC)]	/* Call handler */
    262 
    263 nextinchain:
    264 	teq	r0, #0x00000001		/* Was the irq serviced ? */
    265 	beq	irqdone
    266 
    267 	ldr	r6, [r6, #(IH_NEXT)]
    268 	teq	r6, #0x00000000
    269 	bne	irqchainloop
    270 
    271 irqdone:
    272 nextirq:
    273 	add	r7, r7, #0x00000004	/* update pointer to handlers */
    274 	mov	r9, r9, lsl #1		/* move on to next bit */
    275 	teq	r9, #(1 << 16)		/* done the last bit ? */
    276 	bne	irqloop			/* no - loop back. */
    277 
    278 	ldmfd	sp!, {r2}
    279 	ldr	r1, Lcurrent_spl_level
    280 	str	r2, [r1]
    281 
    282 	/* Restore previous disabled mask */
    283 	ldmfd	sp!, {r2}
    284 	ldr	r1, Ldisabled_mask
    285 	str	r2, [r1]
    286 	bl	_C_LABEL(irq_setmasks)
    287 
    288 	bl	_C_LABEL(dosoftints)	/* Handle the soft interrupts */
    289 
    290 	/* Manage AST's. Maybe this should be done as a soft interrupt ? */
    291 	ldr	r0, [sp]		/* Get the SPSR from stack */
    292 
    293 	and	r0, r0, #(PSR_MODE)	/* Test for USR32 mode before the IRQ */
    294 	teq	r0, #(PSR_USR32_MODE)
    295 	ldreq	r0, Lastpending		/* Do we have an AST pending ? */
    296 	ldreq	r1, [r0]
    297 	teqeq	r1, #0x00000001
    298 
    299 	beq	irqast			/* call the AST handler */
    300 
    301 	/* Kill IRQ's in preparation for exit */
    302         mrs     r0, cpsr_all
    303         orr     r0, r0, #(I32_bit)
    304         msr     cpsr_all, r0
    305 
    306 	/* Decrement the nest count */
    307 	ldr	r0, Lcurrent_intr_depth
    308 	ldr	r1, [r0]
    309 	sub	r1, r1, #1
    310 	str	r1, [r0]
    311 
    312 	PULLFRAMEFROMSVCANDEXIT
    313 
    314 	/* NOT REACHED */
    315 	b	. - 8
    316 
    317 	/*
    318 	 * Ok, snag with current intr depth ...
    319 	 * If ast() calls mi_sleep() the current_intr_depth will not be
    320 	 * decremented until the process is woken up. This can result
    321 	 * in the system believing it is still in the interrupt handler.
    322 	 * If we are calling ast() then correct the current_intr_depth
    323 	 * before the call.
    324 	 */
    325 irqast:
    326 	mov	r1, #0x00000000		/* Clear ast_pending */
    327 	str	r1, [r0]
    328 
    329 	/* Kill IRQ's so we atomically decrement current_intr_depth */
    330         mrs     r2, cpsr_all
    331         orr     r3, r2, #(I32_bit)
    332         msr     cpsr_all, r3
    333 
    334 	/* Decrement the nest count */
    335 	ldr	r0, Lcurrent_intr_depth
    336 	ldr	r1, [r0]
    337 	sub	r1, r1, #1
    338 	str	r1, [r0]
    339 
    340 	/* Restore IRQ's */
    341         msr     cpsr_all, r2
    342 
    343 	mov	r0, sp
    344 	bl	_C_LABEL(ast)
    345 
    346 	/* Kill IRQ's in preparation for exit */
    347         mrs     r0, cpsr_all
    348         orr     r0, r0, #(I32_bit)
    349         msr     cpsr_all, r0
    350 
    351 	PULLFRAMEFROMSVCANDEXIT
    352 
    353 	/* NOT REACHED */
    354 	b	. - 8
    355 
    356 
    357 Lspl_mask:
    358 	.word	_C_LABEL(spl_mask)	/* irq's allowed at current spl level */
    359 
    360 Lcurrent_mask:
    361 	.word	_C_LABEL(current_mask)	/* irq's that are usable */
    362 
    363 ENTRY(irq_setmasks)
    364 	/* Disable interrupts */
    365 	mrs	r3, cpsr_all
    366 	orr	r1, r3,  #(I32_bit)
    367 	msr	cpsr_all, r1
    368 
    369 	/* Calculate interrupt mask */
    370 	ldr	r1, Lcurrent_mask	/* All the enabled interrupts */
    371 	ldrh	r1, [r1]		/* get hardware bits of mask */
    372 /*	.word	0xe0d110b0 */		/* hand-assembled ldrh r1, [r1] */
    373 	ldr	r2, Lspl_mask		/* Block due to current spl level */
    374 	ldr	r2, [r2]
    375 	and	r1, r1, r2
    376 	ldr	r2, Ldisabled_mask	/* Block due to active interrupts */
    377 	ldr	r2, [r2]
    378 	bic	r1, r1, r2
    379 
    380 	/* since 8259's are so slow to access, this code does everything
    381 	   possible to avoid them */
    382 
    383 	/* get current mask: these are the bits */
    384 	ldr	r0, Li8259_mask
    385 	ldr	r2, [r0]
    386 	/*       r2 = 0000.0000.0000.0000.ZZZZ.ZZZZ.ZZZZ.ZZZZ   */
    387 
    388 	/* see if there's anything enabled on 8259 #2 */
    389 	tst	r1, #0xff00
    390 
    391 	biceq	r1, r1, #(1 << IRQ_SLAVE)  /* no, so disable it */
    392 	orrne	r1, r1, #(1 << IRQ_SLAVE)  /* yes, so enable it */
    393 	/* eq => r1 = 0000.0000.0000.0000.0000.0000.MMMM.M0MM
    394            ne => r1 = 0000.0000.0000.0000.MMMM.MMMM.MMMM.M1MM   */
    395 
    396 	/* 8259 bit high => disable */
    397 	mvn	r1, r1
    398 	/* eq => r1 = 1111.1111.1111.1111.1111.1111.YYYY.Y1YY
    399            ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY
    400            (for each bit position Y = !M)                       */
    401 
    402 	orreq	r1, r2, r1, lsl #16
    403 	/* eq => r1 = 1111.1111.YYYY.Y1YY.ZZZZ.ZZZZ.ZZZZ.ZZZZ
    404            ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY   */
    405 	orreq	r1, r1, #0x000000FF
    406 	/* eq => r1 = 1111.1111.YYYY.Y1YY.ZZZZ.ZZZZ.1111.1111
    407            ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY   */
    408 	and	r1, r1, r1, lsr #16
    409 	/* eq => r1 = 0000.0000.0000.0000.ZZZZ.ZZZZ.YYYY.Y1YY
    410            ne => r1 = 0000.0000.0000.0000.YYYY.YYYY.YYYY.Y0YY   */
    411 
    412 	/* if old = new, don't bother to set again.
    413 	   fast path to exit, since 8259's are so slow anyway */
    414 	eors	r2, r1, r2                /* which bits are different? */
    415 	msreq	cpsr_all, r3              /* no bits are different, return */
    416 	moveq	pc, lr
    417 
    418 	/* have to set at least one of the 8259's, store new mask */
    419 	str	r1, [r0]
    420 	ldr	r0, Lvam_io_data
    421 	ldr	r0, [r0]
    422 
    423 	/* see if there's any change for 8259 #1 (master) */
    424 	tst	r2, #0x00FF               /* bottom 8 bits different? */
    425 	strneb	r1, [r0, #(IO_ICU1 + 1)]  /* icu1 / ocw1 */
    426 
    427 	/* anything for 8259 #2? */
    428 	tst	r2, #0xFF00
    429 	mov	r1, r1, lsr #8            /* next byte */
    430 	strneb	r1, [r0, #(IO_ICU2 + 1)]  /* icu2 / ocw1 */
    431 
    432 	/* Restore old cpsr and exit */
    433 	msr	cpsr_all, r3
    434 	mov	pc, lr
    435 
    436 Lcnt:
    437 	.word	_C_LABEL(uvmexp)
    438 
    439 Lintrcnt:
    440 	.word	_C_LABEL(intrcnt)
    441 
    442 Li8259_mask:
    443 	.word	_C_LABEL(i8259_mask)
    444 
    445 Lirqhandlers:
    446 	.word	_C_LABEL(irqhandlers)	/* Pointer to array of irqhandlers */
    447 
    448 Lastpending:
    449 	.word	_C_LABEL(astpending)
    450 
    451 #ifdef IRQSTATS
    452 /* These symbols are used by vmstat */
    453 
    454 	.text
    455 	.global	_C_LABEL(_intrnames)
    456 _C_LABEL(_intrnames):
    457 	.word	_C_LABEL(intrnames)
    458 
    459 	.data
    460 
    461 	/* XXX fix */
    462         .globl  _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(sintrcnt), _C_LABEL(eintrcnt)
    463 _C_LABEL(intrnames):
    464 	.asciz	"interrupt  0 "
    465 	.asciz	"interrupt  1 "
    466 	.asciz	"interrupt  2 "
    467 	.asciz	"interrupt  3 "
    468 	.asciz	"interrupt  4 "
    469 	.asciz	"interrupt  5 "
    470 	.asciz	"interrupt  6 "
    471 	.asciz	"interrupt  7 "
    472 	.asciz	"interrupt  8 "
    473 	.asciz	"interrupt  9 "
    474 	.asciz	"interrupt 10 "
    475 	.asciz	"interrupt 11 "
    476 	.asciz	"interrupt 12 "
    477 	.asciz	"interrupt 13 "
    478 	.asciz	"interrupt 14 "
    479 	.asciz	"interrupt 15 "
    480 	.asciz	"interrupt 16 "
    481 	.asciz	"interrupt 17 "
    482 	.asciz	"interrupt 18 "
    483 	.asciz	"interrupt 19 "
    484 	.asciz	"interrupt 20 "
    485 	.asciz	"interrupt 21 "
    486 	.asciz	"interrupt 22 "
    487 	.asciz	"interrupt 23 "
    488 	.asciz	"interrupt 24 "
    489 	.asciz	"interrupt 25 "
    490 	.asciz	"interrupt 26 "
    491 	.asciz	"interrupt 27 "
    492 	.asciz	"interrupt 28 "
    493 	.asciz	"interrupt 29 "
    494 	.asciz	"interrupt 30 "
    495 	.asciz	"interrupt 31 "
    496 
    497 _C_LABEL(sintrnames):
    498 	.asciz	"soft int  0  "
    499 	.asciz	"soft int  1  "
    500 	.asciz	"soft int  2  "
    501 	.asciz	"soft int  3  "
    502 	.asciz	"soft int  4  "
    503 	.asciz	"soft int  5  "
    504 	.asciz	"soft int  6  "
    505 	.asciz	"soft int  7  "
    506 	.asciz	"soft int  8  "
    507 	.asciz	"soft int  9  "
    508 	.asciz	"soft int 10  "
    509 	.asciz	"soft int 11  "
    510 	.asciz	"soft int 12  "
    511 	.asciz	"soft int 13  "
    512 	.asciz	"soft int 14  "
    513 	.asciz	"soft int 15  "
    514 	.asciz	"soft int 16  "
    515 	.asciz	"soft int 17  "
    516 	.asciz	"soft int 18  "
    517 	.asciz	"soft int 19  "
    518 	.asciz	"soft int 20  "
    519 	.asciz	"soft int 21  "
    520 	.asciz	"soft int 22  "
    521 	.asciz	"soft int 23  "
    522 	.asciz	"soft int 24  "
    523 	.asciz	"soft int 25  "
    524 	.asciz	"soft int 26  "
    525 	.asciz	"soft int 27  "
    526 	.asciz	"soft int 28  "
    527 	.asciz	"soft int 29  "
    528 	.asciz	"soft int 30  "
    529 	.asciz	"soft int 31  "
    530 _C_LABEL(eintrnames):
    531 
    532 	.bss
    533 	.align	0
    534 _C_LABEL(intrcnt):
    535 	.space	32*4	/* XXX Should be linked to number of interrupts */
    536 _C_LABEL(sintrcnt):
    537 	.space	32*4	/* XXX Should be linked to number of soft ints */
    538 _C_LABEL(eintrcnt):
    539 
    540 #else	/* IRQSTATS */
    541 	/* Dummy entries to keep vmstat happy */
    542 
    543 	.text
    544         .globl  _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(eintrcnt)
    545 _C_LABEL(intrnames):
    546 	.long	0
    547 _C_LABEL(eintrnames):
    548 
    549 _C_LABEL(intrcnt):
    550 	.long	0
    551 _C_LABEL(eintrcnt):
    552 #endif	/* IRQSTATS */
    553