isa_irq.S revision 1.16
1 /* $NetBSD: isa_irq.S,v 1.16 2013/12/02 18:36:11 joerg Exp $ */ 2 3 /* 4 * Copyright 1997 5 * Digital Equipment Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and 8 * copied only in accordance with the following terms and conditions. 9 * Subject to these conditions, you may download, copy, install, 10 * use, modify and distribute this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce 14 * and retain this copyright notice and list of conditions as 15 * they appear in the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Digital Equipment Corporation. Neither the "Digital Equipment 19 * Corporation" name nor any trademark or logo of Digital Equipment 20 * Corporation may be used to endorse or promote products derived 21 * from this software without the prior written permission of 22 * Digital Equipment Corporation. 23 * 24 * 3) This software is provided "AS-IS" and any express or implied 25 * warranties, including but not limited to, any implied warranties 26 * of merchantability, fitness for a particular purpose, or 27 * non-infringement are disclaimed. In no event shall DIGITAL be 28 * liable for any damages whatsoever, and in particular, DIGITAL 29 * shall not be liable for special, indirect, consequential, or 30 * incidental damages or damages for lost profits, loss of 31 * revenue or loss of use, whether such damages arise in contract, 32 * negligence, tort, under statute, in equity, at law or otherwise, 33 * even if advised of the possibility of such damage. 34 */ 35 36 /* 37 * Copyright (c) 1994-1998 Mark Brinicombe. 38 * Copyright (c) 1994 Brini. 39 * All rights reserved. 40 * 41 * This code is derived from software written for Brini by Mark Brinicombe 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Mark Brinicombe 54 * for the NetBSD Project. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 * 70 * from: irq.S 71 * 72 * Low level irq and fiq handlers 73 * 74 * Created : 27/09/94 75 */ 76 77 #include "assym.h" 78 #include <machine/asm.h> 79 #include <machine/cpu.h> 80 #include <machine/frame.h> 81 #include <dev/isa/isareg.h> 82 #include <shark/isa/icu.h> 83 #include <machine/irqhandler.h> 84 85 .text 86 .align 0 87 88 /* 89 * 90 * irq_entry 91 * 92 * Main entry point for the IRQ vector 93 * 94 * This function reads the irq request bits in the IOMD registers 95 * IRQRQA, IRQRQB and DMARQ 96 * It then calls an installed handler for each bit that is set. 97 * The function stray_irqhandler is called if a handler is not defined 98 * for a particular interrupt. 99 * If a interrupt handler is found then it is called with r0 containing 100 * the argument defined in the handler structure. If the field ih_arg 101 * is zero then a pointer to the IRQ frame on the stack is passed instead. 102 */ 103 104 .Ldisabled_mask: 105 .word _C_LABEL(disabled_mask) 106 107 .Lvam_io_data: 108 .word _C_LABEL(isa_io_bs_tag) 109 110 .Lspl_masks: 111 .word _C_LABEL(spl_masks) 112 113 /* 114 * Register usage 115 * 116 * r5 - Pointer to handler pointer list 117 * r6 - Address of current handler 118 * r8 - Current IRQ requests. 119 * r9 - Used to count through possible IRQ bits. 120 * r10 - Base address of IOMD 121 */ 122 123 /* Some documentation is in isa_machdep.c */ 124 ASENTRY_NP(irq_entry) 125 sub lr, lr, #0x00000004 /* Adjust the lr */ 126 127 PUSHFRAMEINSVC /* Push an interrupt frame */ 128 ENABLE_ALIGNMENT_FAULTS /* cpuinfo is in r4 after execution */ 129 130 /* Load r8 with the ISA 8259 irqs */ 131 /* r8 <- irq's pending [15:0] */ 132 133 /* address of 8259 #1 */ 134 ldr r0, .Lvam_io_data 135 ldr r0, [r0] 136 ldrb r8, [r0, #IO_ICU1] /* ocw3 = irr */ 137 138 /* clear the IRR bits that are currently masked. */ 139 ldr r2, .Li8259_mask 140 ldr r2, [r2] 141 mvn r2, r2 /* disabled -> enabled */ 142 143 /* address of 8259 #2 */ 144 tst r2, #(1 << IRQ_SLAVE) /* if slave is enabled */ 145 tstne r8, #(1 << IRQ_SLAVE) /* anything from slave? */ 146 ldrbne r1, [r0, #IO_ICU2] /* ocw3 = irr */ 147 orrne r8, r8, r1, lsl #8 148 149 and r8, r8, r2 /* clear disabled */ 150 151 /* clear IRQ 2, which is only used for slave 8259 */ 152 bic r8, r8, #(1 << IRQ_SLAVE) 153 154 /* 155 * Note that we have entered the IRQ handler. 156 * We are in SVC mode so we cannot use the processor mode 157 * to determine if we are in an IRQ. Instead we will count the 158 * each time the interrupt handler is nested. 159 */ 160 161 ldr r1, [r4, #CI_INTR_DEPTH] 162 add r1, r1, #1 163 str r1, [r4, #CI_INTR_DEPTH] 164 165 /* Block the current requested interrupts */ 166 167 ldr r1, .Ldisabled_mask 168 ldr r0, [r1] 169 stmfd sp!, {r0} 170 orr r0, r0, r8 171 172 /* 173 * Need to block all interrupts at the IPL or lower for 174 * all asserted interrupts. 175 * This basically emulates hardware interrupt priority levels. 176 * Means we need to go through the interrupt mask and for 177 * every asserted interrupt we need to mask out all other 178 * interrupts at the same or lower IPL. 179 * If only we could wait until the main loop but we need to sort 180 * this out first so interrupts can be re-enabled. 181 * 182 * This would benefit from a special ffs type routine 183 */ 184 185 mov r9, #(NIPL - 1) 186 ldr r5, .Lspl_masks 187 188 .Lfind_highest_ipl: 189 ldr r2, [r5, r9, lsl #2] 190 tst r8, r2 191 subeq r9, r9, #1 192 beq .Lfind_highest_ipl 193 194 /* r9 = SPL level of highest priority interrupt */ 195 add r9, r9, #1 196 ldr r2, [r5, r9, lsl #2] 197 mvn r2, r2 198 orr r0, r0, r2 199 200 str r0, [r1] 201 202 ldr r1, [r4, #CI_CPL] 203 str r9, [r4, #CI_CPL] 204 stmfd sp!, {r1} 205 206 /* Update the IOMD irq masks */ 207 bl _C_LABEL(irq_setmasks) 208 209 mrs r0, cpsr /* Enable IRQ's */ 210 bic r0, r0, #I32_bit 211 msr cpsr_all, r0 212 213 ldr r5, .Lirqhandlers 214 mov r9, #0x00000001 215 216 irqloop: 217 /* This would benefit from a special ffs type routine */ 218 tst r8, r9 /* Is a bit set ? */ 219 beq nextirq /* No ? try next bit */ 220 221 ldr r6, [r5] /* Get address of first handler structure */ 222 223 teq r6, #0x00000000 /* Do we have a handler */ 224 moveq r0, r8 /* IRQ requests as arg 0 */ 225 beq _C_LABEL(stray_irqhandler) /* call special handler */ 226 227 ldr r0, [r4, #(CI_CC_NINTR)] 228 ldr r1, [r4, #(CI_CC_NINTR+4)] 229 adds r0, r0, #0x00000001 230 adc r1, r1, #0x00000000 231 str r0, [r4, #(CI_CC_NINTR)] 232 ldr r1, [r4, #(CI_CC_NINTR+4)] 233 234 irqchainloop: 235 ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */ 236 teq r0, #0x00000000 /* If arg is zero pass stack frame */ 237 addeq r0, sp, #8 /* ... stack frame */ 238 239 mov lr, pc /* return address */ 240 ldr pc, [r6, #(IH_FUNC)] /* Call handler */ 241 242 teq r0, #0x00000001 /* Was the irq serviced ? */ 243 beq irqdone 244 245 ldr r6, [r6, #(IH_NEXT)] 246 teq r6, #0x00000000 247 bne irqchainloop 248 b nextirq 249 250 irqdone: 251 add r3, r6, #IH_EV_COUNT /* get address of ih's ev_count */ 252 ldmia r3, {r1-r2} /* load ev_count */ 253 adds r1, r1, #0x00000001 /* 64bit incr (lo) */ 254 adc r2, r2, #0x00000000 /* 64bit incr (hi) */ 255 stmia r3, {r1-r2} /* store ev_count */ 256 257 nextirq: 258 add r5, r5, #0x00000004 /* update pointer to handlers */ 259 mov r9, r9, lsl #1 /* move on to next bit */ 260 teq r9, #(1 << 16) /* done the last bit ? */ 261 bne irqloop /* no - loop back. */ 262 263 ldmfd sp!, {r2} 264 str r2, [r4, #CI_CPL] 265 266 /* Restore previous disabled mask */ 267 ldmfd sp!, {r2} 268 ldr r1, .Ldisabled_mask 269 str r2, [r1] 270 bl _C_LABEL(irq_setmasks) 271 272 #ifdef __HAVE_FAST_SOFTINTS 273 bl _C_LABEL(dosoftints) /* Handle the soft interrupts */ 274 #endif 275 276 /* Kill IRQ's in preparation for exit */ 277 mrs r0, cpsr 278 orr r0, r0, #(I32_bit) 279 msr cpsr_all, r0 280 281 /* Decrement the nest count */ 282 ldr r1, [r4, #CI_INTR_DEPTH] 283 sub r1, r1, #1 284 str r1, [r4, #CI_INTR_DEPTH] 285 286 LOCK_CAS_CHECK 287 288 DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 289 PULLFRAMEFROMSVCANDEXIT 290 291 /* NOT REACHED */ 292 b . - 8 293 294 .Lcurrent_mask: 295 .word _C_LABEL(current_mask) /* irq's that are usable */ 296 297 .Lcpu_info_store: 298 .word _C_LABEL(cpu_info_store) 299 300 LOCK_CAS_CHECK_LOCALS 301 302 AST_ALIGNMENT_FAULT_LOCALS 303 304 305 ENTRY(irq_setmasks) 306 /* Disable interrupts */ 307 mrs r3, cpsr 308 orr r1, r3, #(I32_bit) 309 msr cpsr_all, r1 310 311 /* Calculate interrupt mask */ 312 ldr r1, .Lcurrent_mask /* All the enabled interrupts */ 313 ldrh r1, [r1] /* get hardware bits of mask */ 314 /* .word 0xe0d110b0 */ /* hand-assembled ldrh r1, [r1] */ 315 ldr r0, .Lspl_masks 316 ldr r2, .Lcpu_info_store 317 ldr r2, [r2, #CI_CPL] 318 ldr r2, [r0, r2, lsl #2] 319 and r1, r1, r2 320 ldr r2, .Ldisabled_mask /* Block due to active interrupts */ 321 ldr r2, [r2] 322 bic r1, r1, r2 323 324 /* since 8259's are so slow to access, this code does everything 325 possible to avoid them */ 326 327 /* get current mask: these are the bits */ 328 ldr r0, .Li8259_mask 329 ldr r2, [r0] 330 /* r2 = 0000.0000.0000.0000.ZZZZ.ZZZZ.ZZZZ.ZZZZ */ 331 332 /* see if there's anything enabled on 8259 #2 */ 333 tst r1, #0xff00 334 335 biceq r1, r1, #(1 << IRQ_SLAVE) /* no, so disable it */ 336 orrne r1, r1, #(1 << IRQ_SLAVE) /* yes, so enable it */ 337 /* eq => r1 = 0000.0000.0000.0000.0000.0000.MMMM.M0MM 338 ne => r1 = 0000.0000.0000.0000.MMMM.MMMM.MMMM.M1MM */ 339 340 /* 8259 bit high => disable */ 341 mvn r1, r1 342 /* eq => r1 = 1111.1111.1111.1111.1111.1111.YYYY.Y1YY 343 ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY 344 (for each bit position Y = !M) */ 345 346 orreq r1, r2, r1, lsl #16 347 /* eq => r1 = 1111.1111.YYYY.Y1YY.ZZZZ.ZZZZ.ZZZZ.ZZZZ 348 ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY */ 349 orreq r1, r1, #0x000000FF 350 /* eq => r1 = 1111.1111.YYYY.Y1YY.ZZZZ.ZZZZ.1111.1111 351 ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY */ 352 and r1, r1, r1, lsr #16 353 /* eq => r1 = 0000.0000.0000.0000.ZZZZ.ZZZZ.YYYY.Y1YY 354 ne => r1 = 0000.0000.0000.0000.YYYY.YYYY.YYYY.Y0YY */ 355 356 /* if old = new, don't bother to set again. 357 fast path to exit, since 8259's are so slow anyway */ 358 eors r2, r1, r2 /* which bits are different? */ 359 msreq cpsr_all, r3 /* no bits are different, return */ 360 moveq pc, lr 361 362 /* have to set at least one of the 8259's, store new mask */ 363 str r1, [r0] 364 ldr r0, .Lvam_io_data 365 ldr r0, [r0] 366 367 /* see if there's any change for 8259 #1 (master) */ 368 tst r2, #0x00FF /* bottom 8 bits different? */ 369 strbne r1, [r0, #(IO_ICU1 + 1)] /* icu1 / ocw1 */ 370 371 /* anything for 8259 #2? */ 372 tst r2, #0xFF00 373 mov r1, r1, lsr #8 /* next byte */ 374 strbne r1, [r0, #(IO_ICU2 + 1)] /* icu2 / ocw1 */ 375 376 /* Restore old cpsr and exit */ 377 msr cpsr_all, r3 378 mov pc, lr 379 380 .Li8259_mask: 381 .word _C_LABEL(i8259_mask) 382 383 .Lirqhandlers: 384 .word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */ 385
Indexes created Tue Sep 30 20:09:53 GMT 2025