isa_irq.S revision 1.3
1 /* $NetBSD: isa_irq.S,v 1.3 2003/11/05 12:03:58 scw Exp $ */ 2 3 /* 4 * Copyright 1997 5 * Digital Equipment Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and 8 * copied only in accordance with the following terms and conditions. 9 * Subject to these conditions, you may download, copy, install, 10 * use, modify and distribute this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce 14 * and retain this copyright notice and list of conditions as 15 * they appear in the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Digital Equipment Corporation. Neither the "Digital Equipment 19 * Corporation" name nor any trademark or logo of Digital Equipment 20 * Corporation may be used to endorse or promote products derived 21 * from this software without the prior written permission of 22 * Digital Equipment Corporation. 23 * 24 * 3) This software is provided "AS-IS" and any express or implied 25 * warranties, including but not limited to, any implied warranties 26 * of merchantability, fitness for a particular purpose, or 27 * non-infringement are disclaimed. In no event shall DIGITAL be 28 * liable for any damages whatsoever, and in particular, DIGITAL 29 * shall not be liable for special, indirect, consequential, or 30 * incidental damages or damages for lost profits, loss of 31 * revenue or loss of use, whether such damages arise in contract, 32 * negligence, tort, under statute, in equity, at law or otherwise, 33 * even if advised of the possibility of such damage. 34 */ 35 36 /* 37 * Copyright (c) 1994-1998 Mark Brinicombe. 38 * Copyright (c) 1994 Brini. 39 * All rights reserved. 40 * 41 * This code is derived from software written for Brini by Mark Brinicombe 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Mark Brinicombe 54 * for the NetBSD Project. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 * 70 * from: irq.S 71 * 72 * Low level irq and fiq handlers 73 * 74 * Created : 27/09/94 75 */ 76 77 #include "opt_irqstats.h" 78 79 #include "assym.h" 80 #include <machine/asm.h> 81 #include <machine/cpu.h> 82 #include <machine/frame.h> 83 #include <dev/isa/isareg.h> 84 #include <shark/isa/icu.h> 85 #include <machine/irqhandler.h> 86 87 .text 88 .align 0 89 90 /* 91 * 92 * irq_entry 93 * 94 * Main entry point for the IRQ vector 95 * 96 * This function reads the irq request bits in the IOMD registers 97 * IRQRQA, IRQRQB and DMARQ 98 * It then calls an installed handler for each bit that is set. 99 * The function stray_irqhandler is called if a handler is not defined 100 * for a particular interrupt. 101 * If a interrupt handler is found then it is called with r0 containing 102 * the argument defined in the handler structure. If the field ih_arg 103 * is zero then a pointer to the IRQ frame on the stack is passed instead. 104 */ 105 106 Ldisabled_mask: 107 .word _C_LABEL(disabled_mask) 108 109 Lcurrent_spl_level: 110 .word _C_LABEL(current_spl_level) 111 112 Lcurrent_intr_depth: 113 .word _C_LABEL(current_intr_depth) 114 115 Lvam_io_data: 116 .word _C_LABEL(isa_io_bs_tag) 117 118 Lspl_masks: 119 .word _C_LABEL(spl_masks) 120 121 /* 122 * Register usage 123 * 124 * r6 - Address of current handler 125 * r7 - Pointer to handler pointer list 126 * r8 - Current IRQ requests. 127 * r9 - Used to count through possible IRQ bits. 128 * r10 - Base address of IOMD 129 */ 130 131 /* Some documentation is in isa_machdep.c */ 132 ASENTRY_NP(irq_entry) 133 sub lr, lr, #0x00000004 /* Adjust the lr */ 134 135 PUSHFRAMEINSVC /* Push an interrupt frame */ 136 ENABLE_ALIGNMENT_FAULTS 137 138 /* Load r8 with the ISA 8259 irqs */ 139 /* r8 <- irq's pending [15:0] */ 140 141 /* address of 8259 #1 */ 142 ldr r0, Lvam_io_data 143 ldr r0, [r0] 144 ldrb r8, [r0, #IO_ICU1] /* ocw3 = irr */ 145 146 /* clear the IRR bits that are currently masked. */ 147 ldr r2, Li8259_mask 148 ldr r2, [r2] 149 mvn r2, r2 /* disabled -> enabled */ 150 151 /* address of 8259 #2 */ 152 tst r2, #(1 << IRQ_SLAVE) /* if slave is enabled */ 153 tstne r8, #(1 << IRQ_SLAVE) /* anything from slave? */ 154 ldrneb r1, [r0, #IO_ICU2] /* ocw3 = irr */ 155 orrne r8, r8, r1, lsl #8 156 157 and r8, r8, r2 /* clear disabled */ 158 159 /* clear IRQ 2, which is only used for slave 8259 */ 160 bic r8, r8, #(1 << IRQ_SLAVE) 161 162 /* 163 * Note that we have entered the IRQ handler. 164 * We are in SVC mode so we cannot use the processor mode 165 * to determine if we are in an IRQ. Instead we will count the 166 * each time the interrupt handler is nested. 167 */ 168 169 ldr r0, Lcurrent_intr_depth 170 ldr r1, [r0] 171 add r1, r1, #1 172 str r1, [r0] 173 174 /* Block the current requested interrupts */ 175 176 ldr r1, Ldisabled_mask 177 ldr r0, [r1] 178 stmfd sp!, {r0} 179 orr r0, r0, r8 180 181 /* 182 * Need to block all interrupts at the IPL or lower for 183 * all asserted interrupts. 184 * This basically emulates hardware interrupt priority levels. 185 * Means we need to go through the interrupt mask and for 186 * every asserted interrupt we need to mask out all other 187 * interrupts at the same or lower IPL. 188 * If only we could wait until the main loop but we need to sort 189 * this out first so interrupts can be re-enabled. 190 * 191 * This would benefit from a special ffs type routine 192 */ 193 194 mov r9, #(_SPL_LEVELS - 1) 195 ldr r7, Lspl_masks 196 197 Lfind_highest_ipl: 198 ldr r2, [r7, r9, lsl #2] 199 tst r8, r2 200 subeq r9, r9, #1 201 beq Lfind_highest_ipl 202 203 /* r9 = SPL level of highest priority interrupt */ 204 add r9, r9, #1 205 ldr r2, [r7, r9, lsl #2] 206 mvn r2, r2 207 orr r0, r0, r2 208 209 str r0, [r1] 210 211 ldr r0, Lcurrent_spl_level 212 ldr r1, [r0] 213 str r9, [r0] 214 stmfd sp!, {r1} 215 216 /* Update the IOMD irq masks */ 217 bl _C_LABEL(irq_setmasks) 218 219 mrs r0, cpsr_all /* Enable IRQ's */ 220 bic r0, r0, #I32_bit 221 msr cpsr_all, r0 222 223 ldr r7, Lirqhandlers 224 mov r9, #0x00000001 225 226 irqloop: 227 /* This would benefit from a special ffs type routine */ 228 tst r8, r9 /* Is a bit set ? */ 229 beq nextirq /* No ? try next bit */ 230 231 ldr r6, [r7] /* Get address of first handler structure */ 232 233 teq r6, #0x00000000 /* Do we have a handler */ 234 moveq r0, r8 /* IRQ requests as arg 0 */ 235 beq _C_LABEL(stray_irqhandler) /* call special handler */ 236 237 ldr r0, Lcnt 238 ldr r1, [r0, #(V_INTR)] 239 add r1, r1, #0x00000001 240 str r1, [r0, #(V_INTR)] 241 242 /* 243 * XXX: Should stats be accumlated for every interrupt routine called 244 * or for every physical interrupt that is serviced. 245 */ 246 247 #ifdef IRQSTATS 248 ldr r0, Lintrcnt 249 ldr r1, [r6, #(IH_NUM)] 250 251 add r0, r0, r1, lsl #2 252 ldr r1, [r0] 253 add r1, r1, #0x00000001 254 str r1, [r0] 255 #endif /* IRQSTATS */ 256 257 irqchainloop: 258 ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */ 259 teq r0, #0x00000000 /* If arg is zero pass stack frame */ 260 addeq r0, sp, #8 /* ... stack frame */ 261 mov lr, pc /* return address */ 262 ldr pc, [r6, #(IH_FUNC)] /* Call handler */ 263 264 teq r0, #0x00000001 /* Was the irq serviced ? */ 265 beq irqdone 266 267 ldr r6, [r6, #(IH_NEXT)] 268 teq r6, #0x00000000 269 bne irqchainloop 270 271 irqdone: 272 nextirq: 273 add r7, r7, #0x00000004 /* update pointer to handlers */ 274 mov r9, r9, lsl #1 /* move on to next bit */ 275 teq r9, #(1 << 16) /* done the last bit ? */ 276 bne irqloop /* no - loop back. */ 277 278 ldmfd sp!, {r2} 279 ldr r1, Lcurrent_spl_level 280 str r2, [r1] 281 282 /* Restore previous disabled mask */ 283 ldmfd sp!, {r2} 284 ldr r1, Ldisabled_mask 285 str r2, [r1] 286 bl _C_LABEL(irq_setmasks) 287 288 bl _C_LABEL(dosoftints) /* Handle the soft interrupts */ 289 290 /* Kill IRQ's in preparation for exit */ 291 mrs r0, cpsr_all 292 orr r0, r0, #(I32_bit) 293 msr cpsr_all, r0 294 295 /* Decrement the nest count */ 296 ldr r0, Lcurrent_intr_depth 297 ldr r1, [r0] 298 sub r1, r1, #1 299 str r1, [r0] 300 301 DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 302 PULLFRAMEFROMSVCANDEXIT 303 304 /* NOT REACHED */ 305 b . - 8 306 307 Lspl_mask: 308 .word _C_LABEL(spl_mask) /* irq's allowed at current spl level */ 309 310 Lcurrent_mask: 311 .word _C_LABEL(current_mask) /* irq's that are usable */ 312 313 AST_ALIGNMENT_FAULT_LOCALS 314 315 316 ENTRY(irq_setmasks) 317 /* Disable interrupts */ 318 mrs r3, cpsr_all 319 orr r1, r3, #(I32_bit) 320 msr cpsr_all, r1 321 322 /* Calculate interrupt mask */ 323 ldr r1, Lcurrent_mask /* All the enabled interrupts */ 324 ldrh r1, [r1] /* get hardware bits of mask */ 325 /* .word 0xe0d110b0 */ /* hand-assembled ldrh r1, [r1] */ 326 ldr r2, Lspl_mask /* Block due to current spl level */ 327 ldr r2, [r2] 328 and r1, r1, r2 329 ldr r2, Ldisabled_mask /* Block due to active interrupts */ 330 ldr r2, [r2] 331 bic r1, r1, r2 332 333 /* since 8259's are so slow to access, this code does everything 334 possible to avoid them */ 335 336 /* get current mask: these are the bits */ 337 ldr r0, Li8259_mask 338 ldr r2, [r0] 339 /* r2 = 0000.0000.0000.0000.ZZZZ.ZZZZ.ZZZZ.ZZZZ */ 340 341 /* see if there's anything enabled on 8259 #2 */ 342 tst r1, #0xff00 343 344 biceq r1, r1, #(1 << IRQ_SLAVE) /* no, so disable it */ 345 orrne r1, r1, #(1 << IRQ_SLAVE) /* yes, so enable it */ 346 /* eq => r1 = 0000.0000.0000.0000.0000.0000.MMMM.M0MM 347 ne => r1 = 0000.0000.0000.0000.MMMM.MMMM.MMMM.M1MM */ 348 349 /* 8259 bit high => disable */ 350 mvn r1, r1 351 /* eq => r1 = 1111.1111.1111.1111.1111.1111.YYYY.Y1YY 352 ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY 353 (for each bit position Y = !M) */ 354 355 orreq r1, r2, r1, lsl #16 356 /* eq => r1 = 1111.1111.YYYY.Y1YY.ZZZZ.ZZZZ.ZZZZ.ZZZZ 357 ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY */ 358 orreq r1, r1, #0x000000FF 359 /* eq => r1 = 1111.1111.YYYY.Y1YY.ZZZZ.ZZZZ.1111.1111 360 ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY */ 361 and r1, r1, r1, lsr #16 362 /* eq => r1 = 0000.0000.0000.0000.ZZZZ.ZZZZ.YYYY.Y1YY 363 ne => r1 = 0000.0000.0000.0000.YYYY.YYYY.YYYY.Y0YY */ 364 365 /* if old = new, don't bother to set again. 366 fast path to exit, since 8259's are so slow anyway */ 367 eors r2, r1, r2 /* which bits are different? */ 368 msreq cpsr_all, r3 /* no bits are different, return */ 369 moveq pc, lr 370 371 /* have to set at least one of the 8259's, store new mask */ 372 str r1, [r0] 373 ldr r0, Lvam_io_data 374 ldr r0, [r0] 375 376 /* see if there's any change for 8259 #1 (master) */ 377 tst r2, #0x00FF /* bottom 8 bits different? */ 378 strneb r1, [r0, #(IO_ICU1 + 1)] /* icu1 / ocw1 */ 379 380 /* anything for 8259 #2? */ 381 tst r2, #0xFF00 382 mov r1, r1, lsr #8 /* next byte */ 383 strneb r1, [r0, #(IO_ICU2 + 1)] /* icu2 / ocw1 */ 384 385 /* Restore old cpsr and exit */ 386 msr cpsr_all, r3 387 mov pc, lr 388 389 Lcnt: 390 .word _C_LABEL(uvmexp) 391 392 Lintrcnt: 393 .word _C_LABEL(intrcnt) 394 395 Li8259_mask: 396 .word _C_LABEL(i8259_mask) 397 398 Lirqhandlers: 399 .word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */ 400 401 #ifdef IRQSTATS 402 /* These symbols are used by vmstat */ 403 404 .text 405 .global _C_LABEL(_intrnames) 406 _C_LABEL(_intrnames): 407 .word _C_LABEL(intrnames) 408 409 .data 410 411 /* XXX fix */ 412 .globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(sintrcnt), _C_LABEL(eintrcnt) 413 _C_LABEL(intrnames): 414 .asciz "interrupt 0 " 415 .asciz "interrupt 1 " 416 .asciz "interrupt 2 " 417 .asciz "interrupt 3 " 418 .asciz "interrupt 4 " 419 .asciz "interrupt 5 " 420 .asciz "interrupt 6 " 421 .asciz "interrupt 7 " 422 .asciz "interrupt 8 " 423 .asciz "interrupt 9 " 424 .asciz "interrupt 10 " 425 .asciz "interrupt 11 " 426 .asciz "interrupt 12 " 427 .asciz "interrupt 13 " 428 .asciz "interrupt 14 " 429 .asciz "interrupt 15 " 430 .asciz "interrupt 16 " 431 .asciz "interrupt 17 " 432 .asciz "interrupt 18 " 433 .asciz "interrupt 19 " 434 .asciz "interrupt 20 " 435 .asciz "interrupt 21 " 436 .asciz "interrupt 22 " 437 .asciz "interrupt 23 " 438 .asciz "interrupt 24 " 439 .asciz "interrupt 25 " 440 .asciz "interrupt 26 " 441 .asciz "interrupt 27 " 442 .asciz "interrupt 28 " 443 .asciz "interrupt 29 " 444 .asciz "interrupt 30 " 445 .asciz "interrupt 31 " 446 447 _C_LABEL(sintrnames): 448 .asciz "soft int 0 " 449 .asciz "soft int 1 " 450 .asciz "soft int 2 " 451 .asciz "soft int 3 " 452 .asciz "soft int 4 " 453 .asciz "soft int 5 " 454 .asciz "soft int 6 " 455 .asciz "soft int 7 " 456 .asciz "soft int 8 " 457 .asciz "soft int 9 " 458 .asciz "soft int 10 " 459 .asciz "soft int 11 " 460 .asciz "soft int 12 " 461 .asciz "soft int 13 " 462 .asciz "soft int 14 " 463 .asciz "soft int 15 " 464 .asciz "soft int 16 " 465 .asciz "soft int 17 " 466 .asciz "soft int 18 " 467 .asciz "soft int 19 " 468 .asciz "soft int 20 " 469 .asciz "soft int 21 " 470 .asciz "soft int 22 " 471 .asciz "soft int 23 " 472 .asciz "soft int 24 " 473 .asciz "soft int 25 " 474 .asciz "soft int 26 " 475 .asciz "soft int 27 " 476 .asciz "soft int 28 " 477 .asciz "soft int 29 " 478 .asciz "soft int 30 " 479 .asciz "soft int 31 " 480 _C_LABEL(eintrnames): 481 482 .bss 483 .align 0 484 _C_LABEL(intrcnt): 485 .space 32*4 /* XXX Should be linked to number of interrupts */ 486 _C_LABEL(sintrcnt): 487 .space 32*4 /* XXX Should be linked to number of soft ints */ 488 _C_LABEL(eintrcnt): 489 490 #else /* IRQSTATS */ 491 /* Dummy entries to keep vmstat happy */ 492 493 .text 494 .globl _C_LABEL(intrnames), _C_LABEL(eintrnames), _C_LABEL(intrcnt), _C_LABEL(eintrcnt) 495 _C_LABEL(intrnames): 496 .long 0 497 _C_LABEL(eintrnames): 498 499 _C_LABEL(intrcnt): 500 .long 0 501 _C_LABEL(eintrcnt): 502 #endif /* IRQSTATS */ 503
Indexes created Mon Sep 29 21:09:56 GMT 2025