isa_irq.S revision 1.7
1 /* $NetBSD: isa_irq.S,v 1.7 2007/03/09 19:21:59 thorpej Exp $ */ 2 3 /* 4 * Copyright 1997 5 * Digital Equipment Corporation. All rights reserved. 6 * 7 * This software is furnished under license and may be used and 8 * copied only in accordance with the following terms and conditions. 9 * Subject to these conditions, you may download, copy, install, 10 * use, modify and distribute this software in source and/or binary 11 * form. No title or ownership is transferred hereby. 12 * 13 * 1) Any source code used, modified or distributed must reproduce 14 * and retain this copyright notice and list of conditions as 15 * they appear in the source file. 16 * 17 * 2) No right is granted to use any trade name, trademark, or logo of 18 * Digital Equipment Corporation. Neither the "Digital Equipment 19 * Corporation" name nor any trademark or logo of Digital Equipment 20 * Corporation may be used to endorse or promote products derived 21 * from this software without the prior written permission of 22 * Digital Equipment Corporation. 23 * 24 * 3) This software is provided "AS-IS" and any express or implied 25 * warranties, including but not limited to, any implied warranties 26 * of merchantability, fitness for a particular purpose, or 27 * non-infringement are disclaimed. In no event shall DIGITAL be 28 * liable for any damages whatsoever, and in particular, DIGITAL 29 * shall not be liable for special, indirect, consequential, or 30 * incidental damages or damages for lost profits, loss of 31 * revenue or loss of use, whether such damages arise in contract, 32 * negligence, tort, under statute, in equity, at law or otherwise, 33 * even if advised of the possibility of such damage. 34 */ 35 36 /* 37 * Copyright (c) 1994-1998 Mark Brinicombe. 38 * Copyright (c) 1994 Brini. 39 * All rights reserved. 40 * 41 * This code is derived from software written for Brini by Mark Brinicombe 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Mark Brinicombe 54 * for the NetBSD Project. 55 * 4. The name of the company nor the name of the author may be used to 56 * endorse or promote products derived from this software without specific 57 * prior written permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 * 70 * from: irq.S 71 * 72 * Low level irq and fiq handlers 73 * 74 * Created : 27/09/94 75 */ 76 77 #include "assym.h" 78 #include <machine/asm.h> 79 #include <machine/cpu.h> 80 #include <machine/frame.h> 81 #include <dev/isa/isareg.h> 82 #include <shark/isa/icu.h> 83 #include <machine/irqhandler.h> 84 85 .text 86 .align 0 87 88 /* 89 * 90 * irq_entry 91 * 92 * Main entry point for the IRQ vector 93 * 94 * This function reads the irq request bits in the IOMD registers 95 * IRQRQA, IRQRQB and DMARQ 96 * It then calls an installed handler for each bit that is set. 97 * The function stray_irqhandler is called if a handler is not defined 98 * for a particular interrupt. 99 * If a interrupt handler is found then it is called with r0 containing 100 * the argument defined in the handler structure. If the field ih_arg 101 * is zero then a pointer to the IRQ frame on the stack is passed instead. 102 */ 103 104 Ldisabled_mask: 105 .word _C_LABEL(disabled_mask) 106 107 Lcurrent_spl_level: 108 .word _C_LABEL(current_spl_level) 109 110 Lcurrent_intr_depth: 111 .word _C_LABEL(current_intr_depth) 112 113 Lvam_io_data: 114 .word _C_LABEL(isa_io_bs_tag) 115 116 Lspl_masks: 117 .word _C_LABEL(spl_masks) 118 119 /* 120 * Register usage 121 * 122 * r6 - Address of current handler 123 * r7 - Pointer to handler pointer list 124 * r8 - Current IRQ requests. 125 * r9 - Used to count through possible IRQ bits. 126 * r10 - Base address of IOMD 127 */ 128 129 /* Some documentation is in isa_machdep.c */ 130 ASENTRY_NP(irq_entry) 131 sub lr, lr, #0x00000004 /* Adjust the lr */ 132 133 PUSHFRAMEINSVC /* Push an interrupt frame */ 134 ENABLE_ALIGNMENT_FAULTS 135 136 /* Load r8 with the ISA 8259 irqs */ 137 /* r8 <- irq's pending [15:0] */ 138 139 /* address of 8259 #1 */ 140 ldr r0, Lvam_io_data 141 ldr r0, [r0] 142 ldrb r8, [r0, #IO_ICU1] /* ocw3 = irr */ 143 144 /* clear the IRR bits that are currently masked. */ 145 ldr r2, Li8259_mask 146 ldr r2, [r2] 147 mvn r2, r2 /* disabled -> enabled */ 148 149 /* address of 8259 #2 */ 150 tst r2, #(1 << IRQ_SLAVE) /* if slave is enabled */ 151 tstne r8, #(1 << IRQ_SLAVE) /* anything from slave? */ 152 ldrneb r1, [r0, #IO_ICU2] /* ocw3 = irr */ 153 orrne r8, r8, r1, lsl #8 154 155 and r8, r8, r2 /* clear disabled */ 156 157 /* clear IRQ 2, which is only used for slave 8259 */ 158 bic r8, r8, #(1 << IRQ_SLAVE) 159 160 /* 161 * Note that we have entered the IRQ handler. 162 * We are in SVC mode so we cannot use the processor mode 163 * to determine if we are in an IRQ. Instead we will count the 164 * each time the interrupt handler is nested. 165 */ 166 167 ldr r0, Lcurrent_intr_depth 168 ldr r1, [r0] 169 add r1, r1, #1 170 str r1, [r0] 171 172 /* Block the current requested interrupts */ 173 174 ldr r1, Ldisabled_mask 175 ldr r0, [r1] 176 stmfd sp!, {r0} 177 orr r0, r0, r8 178 179 /* 180 * Need to block all interrupts at the IPL or lower for 181 * all asserted interrupts. 182 * This basically emulates hardware interrupt priority levels. 183 * Means we need to go through the interrupt mask and for 184 * every asserted interrupt we need to mask out all other 185 * interrupts at the same or lower IPL. 186 * If only we could wait until the main loop but we need to sort 187 * this out first so interrupts can be re-enabled. 188 * 189 * This would benefit from a special ffs type routine 190 */ 191 192 mov r9, #(_SPL_LEVELS - 1) 193 ldr r7, Lspl_masks 194 195 Lfind_highest_ipl: 196 ldr r2, [r7, r9, lsl #2] 197 tst r8, r2 198 subeq r9, r9, #1 199 beq Lfind_highest_ipl 200 201 /* r9 = SPL level of highest priority interrupt */ 202 add r9, r9, #1 203 ldr r2, [r7, r9, lsl #2] 204 mvn r2, r2 205 orr r0, r0, r2 206 207 str r0, [r1] 208 209 ldr r0, Lcurrent_spl_level 210 ldr r1, [r0] 211 str r9, [r0] 212 stmfd sp!, {r1} 213 214 /* Update the IOMD irq masks */ 215 bl _C_LABEL(irq_setmasks) 216 217 mrs r0, cpsr_all /* Enable IRQ's */ 218 bic r0, r0, #I32_bit 219 msr cpsr_all, r0 220 221 ldr r7, Lirqhandlers 222 mov r9, #0x00000001 223 224 irqloop: 225 /* This would benefit from a special ffs type routine */ 226 tst r8, r9 /* Is a bit set ? */ 227 beq nextirq /* No ? try next bit */ 228 229 ldr r6, [r7] /* Get address of first handler structure */ 230 231 teq r6, #0x00000000 /* Do we have a handler */ 232 moveq r0, r8 /* IRQ requests as arg 0 */ 233 beq _C_LABEL(stray_irqhandler) /* call special handler */ 234 235 ldr r0, Lcnt 236 ldr r1, [r0, #(V_INTR)] 237 add r1, r1, #0x00000001 238 str r1, [r0, #(V_INTR)] 239 240 irqchainloop: 241 ldr r0, [r6, #(IH_ARG)] /* Get argument pointer */ 242 teq r0, #0x00000000 /* If arg is zero pass stack frame */ 243 addeq r0, sp, #8 /* ... stack frame */ 244 245 mov lr, pc /* return address */ 246 ldr pc, [r6, #(IH_FUNC)] /* Call handler */ 247 248 teq r0, #0x00000001 /* Was the irq serviced ? */ 249 beq irqdone 250 251 ldr r6, [r6, #(IH_NEXT)] 252 teq r6, #0x00000000 253 bne irqchainloop 254 b nextirq 255 256 irqdone: 257 add r3, r6, #IH_EV_COUNT /* get address of ih's ev_count */ 258 ldmia r3, {r1-r2} /* load ev_count */ 259 adds r1, r1, #0x00000001 /* 64bit incr (lo) */ 260 adc r2, r2, #0x00000000 /* 64bit incr (hi) */ 261 stmia r3, {r1-r2} /* store ev_count */ 262 263 nextirq: 264 add r7, r7, #0x00000004 /* update pointer to handlers */ 265 mov r9, r9, lsl #1 /* move on to next bit */ 266 teq r9, #(1 << 16) /* done the last bit ? */ 267 bne irqloop /* no - loop back. */ 268 269 ldmfd sp!, {r2} 270 ldr r1, Lcurrent_spl_level 271 str r2, [r1] 272 273 /* Restore previous disabled mask */ 274 ldmfd sp!, {r2} 275 ldr r1, Ldisabled_mask 276 str r2, [r1] 277 bl _C_LABEL(irq_setmasks) 278 279 bl _C_LABEL(dosoftints) /* Handle the soft interrupts */ 280 281 /* Kill IRQ's in preparation for exit */ 282 mrs r0, cpsr_all 283 orr r0, r0, #(I32_bit) 284 msr cpsr_all, r0 285 286 /* Decrement the nest count */ 287 ldr r0, Lcurrent_intr_depth 288 ldr r1, [r0] 289 sub r1, r1, #1 290 str r1, [r0] 291 292 LOCK_CAS_CHECK 293 294 DO_AST_AND_RESTORE_ALIGNMENT_FAULTS 295 PULLFRAMEFROMSVCANDEXIT 296 297 /* NOT REACHED */ 298 b . - 8 299 300 Lspl_mask: 301 .word _C_LABEL(spl_mask) /* irq's allowed at current spl level */ 302 303 Lcurrent_mask: 304 .word _C_LABEL(current_mask) /* irq's that are usable */ 305 306 LOCK_CAS_CHECK_LOCALS 307 308 AST_ALIGNMENT_FAULT_LOCALS 309 310 311 ENTRY(irq_setmasks) 312 /* Disable interrupts */ 313 mrs r3, cpsr_all 314 orr r1, r3, #(I32_bit) 315 msr cpsr_all, r1 316 317 /* Calculate interrupt mask */ 318 ldr r1, Lcurrent_mask /* All the enabled interrupts */ 319 ldrh r1, [r1] /* get hardware bits of mask */ 320 /* .word 0xe0d110b0 */ /* hand-assembled ldrh r1, [r1] */ 321 ldr r2, Lspl_mask /* Block due to current spl level */ 322 ldr r2, [r2] 323 and r1, r1, r2 324 ldr r2, Ldisabled_mask /* Block due to active interrupts */ 325 ldr r2, [r2] 326 bic r1, r1, r2 327 328 /* since 8259's are so slow to access, this code does everything 329 possible to avoid them */ 330 331 /* get current mask: these are the bits */ 332 ldr r0, Li8259_mask 333 ldr r2, [r0] 334 /* r2 = 0000.0000.0000.0000.ZZZZ.ZZZZ.ZZZZ.ZZZZ */ 335 336 /* see if there's anything enabled on 8259 #2 */ 337 tst r1, #0xff00 338 339 biceq r1, r1, #(1 << IRQ_SLAVE) /* no, so disable it */ 340 orrne r1, r1, #(1 << IRQ_SLAVE) /* yes, so enable it */ 341 /* eq => r1 = 0000.0000.0000.0000.0000.0000.MMMM.M0MM 342 ne => r1 = 0000.0000.0000.0000.MMMM.MMMM.MMMM.M1MM */ 343 344 /* 8259 bit high => disable */ 345 mvn r1, r1 346 /* eq => r1 = 1111.1111.1111.1111.1111.1111.YYYY.Y1YY 347 ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY 348 (for each bit position Y = !M) */ 349 350 orreq r1, r2, r1, lsl #16 351 /* eq => r1 = 1111.1111.YYYY.Y1YY.ZZZZ.ZZZZ.ZZZZ.ZZZZ 352 ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY */ 353 orreq r1, r1, #0x000000FF 354 /* eq => r1 = 1111.1111.YYYY.Y1YY.ZZZZ.ZZZZ.1111.1111 355 ne => r1 = 1111.1111.1111.1111.YYYY.YYYY.YYYY.Y0YY */ 356 and r1, r1, r1, lsr #16 357 /* eq => r1 = 0000.0000.0000.0000.ZZZZ.ZZZZ.YYYY.Y1YY 358 ne => r1 = 0000.0000.0000.0000.YYYY.YYYY.YYYY.Y0YY */ 359 360 /* if old = new, don't bother to set again. 361 fast path to exit, since 8259's are so slow anyway */ 362 eors r2, r1, r2 /* which bits are different? */ 363 msreq cpsr_all, r3 /* no bits are different, return */ 364 moveq pc, lr 365 366 /* have to set at least one of the 8259's, store new mask */ 367 str r1, [r0] 368 ldr r0, Lvam_io_data 369 ldr r0, [r0] 370 371 /* see if there's any change for 8259 #1 (master) */ 372 tst r2, #0x00FF /* bottom 8 bits different? */ 373 strneb r1, [r0, #(IO_ICU1 + 1)] /* icu1 / ocw1 */ 374 375 /* anything for 8259 #2? */ 376 tst r2, #0xFF00 377 mov r1, r1, lsr #8 /* next byte */ 378 strneb r1, [r0, #(IO_ICU2 + 1)] /* icu2 / ocw1 */ 379 380 /* Restore old cpsr and exit */ 381 msr cpsr_all, r3 382 mov pc, lr 383 384 Lcnt: 385 .word _C_LABEL(uvmexp) 386 387 Li8259_mask: 388 .word _C_LABEL(i8259_mask) 389 390 Lirqhandlers: 391 .word _C_LABEL(irqhandlers) /* Pointer to array of irqhandlers */ 392
Indexes created Tue Sep 30 11:09:46 GMT 2025